RTEMS  5.0.0
if_em_hw.h
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2 
3  Copyright (c) 2001-2005, Intel Corporation
4  All rights reserved.
5 
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32 *******************************************************************************/
33 
34 /*$FreeBSD: /repoman/r/ncvs/src/sys/dev/em/if_em_hw.h,v 1.15 2005/05/26 23:32:02 tackerman Exp $*/
35 /* if_em_hw.h
36  * Structures, enums, and macros for the MAC
37  */
38 
39 #ifndef _EM_HW_H_
40 #define _EM_HW_H_
41 
42 #ifndef __rtems__
43 #include <dev/em/if_em_osdep.h>
44 #else
45 #include "if_em_osdep.h"
46 #endif
47 
48 
49 /* Forward declarations of structures used by the shared code */
50 struct em_hw;
51 struct em_hw_stats;
52 
53 /* Enumerated types specific to the e1000 hardware */
54 /* Media Access Controlers */
55 typedef enum {
56  em_undefined = 0,
57  em_82542_rev2_0,
58  em_82542_rev2_1,
59  em_82543,
60  em_82544,
61  em_82540,
62  em_82545,
63  em_82545_rev_3,
64  em_82546,
65  em_82546_rev_3,
66  em_82541,
67  em_82541_rev_2,
68  em_82547,
69  em_82547_rev_2,
70  em_82573,
71  em_num_macs
72 } em_mac_type;
73 
74 typedef enum {
75  em_eeprom_uninitialized = 0,
76  em_eeprom_spi,
77  em_eeprom_microwire,
78  em_eeprom_flash,
79  em_num_eeprom_types
80 } em_eeprom_type;
81 
82 /* Media Types */
83 typedef enum {
84  em_media_type_copper = 0,
85  em_media_type_fiber = 1,
86  em_media_type_internal_serdes = 2,
87  em_num_media_types
88 } em_media_type;
89 
90 typedef enum {
91  em_10_half = 0,
92  em_10_full = 1,
93  em_100_half = 2,
94  em_100_full = 3
95 } em_speed_duplex_type;
96 
97 /* Flow Control Settings */
98 typedef enum {
99  em_fc_none = 0,
100  em_fc_rx_pause = 1,
101  em_fc_tx_pause = 2,
102  em_fc_full = 3,
103  em_fc_default = 0xFF
104 } em_fc_type;
105 
106 /* PCI bus types */
107 typedef enum {
108  em_bus_type_unknown = 0,
109  em_bus_type_pci,
110  em_bus_type_pcix,
111  em_bus_type_pci_express,
112  em_bus_type_reserved
113 } em_bus_type;
114 
115 /* PCI bus speeds */
116 typedef enum {
117  em_bus_speed_unknown = 0,
118  em_bus_speed_33,
119  em_bus_speed_66,
120  em_bus_speed_100,
121  em_bus_speed_120,
122  em_bus_speed_133,
123  em_bus_speed_2500,
124  em_bus_speed_reserved
125 } em_bus_speed;
126 
127 /* PCI bus widths */
128 typedef enum {
129  em_bus_width_unknown = 0,
130  em_bus_width_32,
131  em_bus_width_64,
132  em_bus_width_pciex_1,
133  em_bus_width_pciex_4,
134  em_bus_width_reserved
135 } em_bus_width;
136 
137 /* PHY status info structure and supporting enums */
138 typedef enum {
139  em_cable_length_50 = 0,
140  em_cable_length_50_80,
141  em_cable_length_80_110,
142  em_cable_length_110_140,
143  em_cable_length_140,
144  em_cable_length_undefined = 0xFF
145 } em_cable_length;
146 
147 typedef enum {
148  em_igp_cable_length_10 = 10,
149  em_igp_cable_length_20 = 20,
150  em_igp_cable_length_30 = 30,
151  em_igp_cable_length_40 = 40,
152  em_igp_cable_length_50 = 50,
153  em_igp_cable_length_60 = 60,
154  em_igp_cable_length_70 = 70,
155  em_igp_cable_length_80 = 80,
156  em_igp_cable_length_90 = 90,
157  em_igp_cable_length_100 = 100,
158  em_igp_cable_length_110 = 110,
159  em_igp_cable_length_120 = 120,
160  em_igp_cable_length_130 = 130,
161  em_igp_cable_length_140 = 140,
162  em_igp_cable_length_150 = 150,
163  em_igp_cable_length_160 = 160,
164  em_igp_cable_length_170 = 170,
165  em_igp_cable_length_180 = 180
166 } em_igp_cable_length;
167 
168 typedef enum {
169  em_10bt_ext_dist_enable_normal = 0,
170  em_10bt_ext_dist_enable_lower,
171  em_10bt_ext_dist_enable_undefined = 0xFF
172 } em_10bt_ext_dist_enable;
173 
174 typedef enum {
175  em_rev_polarity_normal = 0,
176  em_rev_polarity_reversed,
177  em_rev_polarity_undefined = 0xFF
178 } em_rev_polarity;
179 
180 typedef enum {
181  em_downshift_normal = 0,
182  em_downshift_activated,
183  em_downshift_undefined = 0xFF
184 } em_downshift;
185 
186 typedef enum {
187  em_smart_speed_default = 0,
188  em_smart_speed_on,
189  em_smart_speed_off
190 } em_smart_speed;
191 
192 typedef enum {
193  em_polarity_reversal_enabled = 0,
194  em_polarity_reversal_disabled,
195  em_polarity_reversal_undefined = 0xFF
196 } em_polarity_reversal;
197 
198 typedef enum {
199  em_auto_x_mode_manual_mdi = 0,
200  em_auto_x_mode_manual_mdix,
201  em_auto_x_mode_auto1,
202  em_auto_x_mode_auto2,
203  em_auto_x_mode_undefined = 0xFF
204 } em_auto_x_mode;
205 
206 typedef enum {
207  em_1000t_rx_status_not_ok = 0,
208  em_1000t_rx_status_ok,
209  em_1000t_rx_status_undefined = 0xFF
210 } em_1000t_rx_status;
211 
212 typedef enum {
213  em_phy_m88 = 0,
214  em_phy_igp,
215  em_phy_igp_2,
216  em_phy_undefined = 0xFF
217 } em_phy_type;
218 
219 typedef enum {
220  em_ms_hw_default = 0,
221  em_ms_force_master,
222  em_ms_force_slave,
223  em_ms_auto
224 } em_ms_type;
225 
226 typedef enum {
227  em_ffe_config_enabled = 0,
228  em_ffe_config_active,
229  em_ffe_config_blocked
230 } em_ffe_config;
231 
232 typedef enum {
233  em_dsp_config_disabled = 0,
234  em_dsp_config_enabled,
235  em_dsp_config_activated,
236  em_dsp_config_undefined = 0xFF
237 } em_dsp_config;
238 
239 struct em_phy_info {
240  em_cable_length cable_length;
241  em_10bt_ext_dist_enable extended_10bt_distance;
242  em_rev_polarity cable_polarity;
243  em_downshift downshift;
244  em_polarity_reversal polarity_correction;
245  em_auto_x_mode mdix_mode;
246  em_1000t_rx_status local_rx;
247  em_1000t_rx_status remote_rx;
248 };
249 
250 struct em_phy_stats {
251  uint32_t idle_errors;
252  uint32_t receive_errors;
253 };
254 
255 struct em_eeprom_info {
256  em_eeprom_type type;
257  uint16_t word_size;
258  uint16_t opcode_bits;
259  uint16_t address_bits;
260  uint16_t delay_usec;
261  uint16_t page_size;
262  boolean_t use_eerd;
263  boolean_t use_eewr;
264 };
265 
266 /* Flex ASF Information */
267 #define E1000_HOST_IF_MAX_SIZE 2048
268 
269 typedef enum {
270  em_byte_align = 0,
271  em_word_align = 1,
272  em_dword_align = 2
273 } em_align_type;
274 
275 
276 
277 /* Error Codes */
278 #define E1000_SUCCESS 0
279 #define E1000_ERR_EEPROM 1
280 #define E1000_ERR_PHY 2
281 #define E1000_ERR_CONFIG 3
282 #define E1000_ERR_PARAM 4
283 #define E1000_ERR_MAC_TYPE 5
284 #define E1000_ERR_PHY_TYPE 6
285 #define E1000_ERR_RESET 9
286 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
287 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
288 #define E1000_BLK_PHY_RESET 12
289 
290 /* Function prototypes */
291 /* Initialization */
292 int32_t em_reset_hw(struct em_hw *hw);
293 int32_t em_init_hw(struct em_hw *hw);
294 int32_t em_id_led_init(struct em_hw * hw);
295 int32_t em_set_mac_type(struct em_hw *hw);
296 void em_set_media_type(struct em_hw *hw);
297 
298 /* Link Configuration */
299 int32_t em_setup_link(struct em_hw *hw);
300 int32_t em_phy_setup_autoneg(struct em_hw *hw);
301 void em_config_collision_dist(struct em_hw *hw);
302 int32_t em_config_fc_after_link_up(struct em_hw *hw);
303 int32_t em_check_for_link(struct em_hw *hw);
304 int32_t em_get_speed_and_duplex(struct em_hw *hw, uint16_t * speed, uint16_t * duplex);
305 int32_t em_wait_autoneg(struct em_hw *hw);
306 int32_t em_force_mac_fc(struct em_hw *hw);
307 
308 /* PHY */
309 int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
310 int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
311 int32_t em_phy_hw_reset(struct em_hw *hw);
312 int32_t em_phy_reset(struct em_hw *hw);
313 int32_t em_detect_gig_phy(struct em_hw *hw);
314 int32_t em_phy_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
315 int32_t em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
316 int32_t em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
317 int32_t em_get_cable_length(struct em_hw *hw, uint16_t *min_length, uint16_t *max_length);
318 int32_t em_check_polarity(struct em_hw *hw, uint16_t *polarity);
319 int32_t em_check_downshift(struct em_hw *hw);
320 int32_t em_validate_mdi_setting(struct em_hw *hw);
321 
322 /* EEPROM Functions */
323 int32_t em_init_eeprom_params(struct em_hw *hw);
324 boolean_t em_is_onboard_nvm_eeprom(struct em_hw *hw);
325 int32_t em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
326 int32_t em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
327 int32_t em_poll_eerd_eewr_done(struct em_hw *hw, int eerd);
328 
329 /* MNG HOST IF functions */
330 uint32_t em_enable_mng_pass_thru(struct em_hw *hw);
331 
332 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
333 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
334 
335 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
336 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
337 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
338 #define E1000_MNG_IAMT_MODE 0x3
339 #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
340 
341 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
342 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
343 #define E1000_VFTA_ENTRY_SHIFT 0x5
344 #define E1000_VFTA_ENTRY_MASK 0x7F
345 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
346 
347 struct em_host_mng_command_header {
348  uint8_t command_id;
349  uint8_t checksum;
350  uint16_t reserved1;
351  uint16_t reserved2;
352  uint16_t command_length;
353 };
354 
355 struct em_host_mng_command_info {
356  struct em_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
357  uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
358 };
359 #ifdef __BIG_ENDIAN
360 struct em_host_mng_dhcp_cookie{
361  uint32_t signature;
362  uint16_t vlan_id;
363  uint8_t reserved0;
364  uint8_t status;
365  uint32_t reserved1;
366  uint8_t checksum;
367  uint8_t reserved3;
368  uint16_t reserved2;
369 };
370 #else
371 struct em_host_mng_dhcp_cookie{
372  uint32_t signature;
373  uint8_t status;
374  uint8_t reserved0;
375  uint16_t vlan_id;
376  uint32_t reserved1;
377  uint16_t reserved2;
378  uint8_t reserved3;
379  uint8_t checksum;
380 };
381 #endif
382 
383 int32_t em_mng_write_dhcp_info(struct em_hw *hw, uint8_t *buffer,
384  uint16_t length);
385 boolean_t em_check_mng_mode(struct em_hw *hw);
386 boolean_t em_enable_tx_pkt_filtering(struct em_hw *hw);
387 int32_t em_mng_enable_host_if(struct em_hw *hw);
388 int32_t em_mng_host_if_write(struct em_hw *hw, uint8_t *buffer,
389  uint16_t length, uint16_t offset, uint8_t *sum);
390 int32_t em_mng_write_cmd_header(struct em_hw* hw,
391  struct em_host_mng_command_header* hdr);
392 
393 int32_t em_mng_write_commit(struct em_hw *hw);
394 
395 int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
396 int32_t em_validate_eeprom_checksum(struct em_hw *hw);
397 int32_t em_update_eeprom_checksum(struct em_hw *hw);
398 int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
399 int32_t em_read_part_num(struct em_hw *hw, uint32_t * part_num);
400 int32_t em_read_mac_addr(struct em_hw * hw);
401 int32_t em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask);
402 void em_swfw_sync_release(struct em_hw *hw, uint16_t mask);
403 
404 /* Filters (multicast, vlan, receive) */
405 void em_init_rx_addrs(struct em_hw *hw);
406 void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
407 uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t * mc_addr);
408 void em_mta_set(struct em_hw *hw, uint32_t hash_value);
409 void em_rar_set(struct em_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
410 void em_write_vfta(struct em_hw *hw, uint32_t offset, uint32_t value);
411 void em_clear_vfta(struct em_hw *hw);
412 
413 /* LED functions */
414 int32_t em_setup_led(struct em_hw *hw);
415 int32_t em_cleanup_led(struct em_hw *hw);
416 int32_t em_led_on(struct em_hw *hw);
417 int32_t em_led_off(struct em_hw *hw);
418 
419 /* Adaptive IFS Functions */
420 
421 /* Everything else */
422 void em_clear_hw_cntrs(struct em_hw *hw);
423 void em_reset_adaptive(struct em_hw *hw);
424 void em_update_adaptive(struct em_hw *hw);
425 void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
426 void em_get_bus_info(struct em_hw *hw);
427 void em_pci_set_mwi(struct em_hw *hw);
428 void em_pci_clear_mwi(struct em_hw *hw);
429 void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value);
430 void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value);
431 /* Port I/O is only supported on 82544 and newer */
432 uint32_t em_io_read(struct em_hw *hw, unsigned long port);
433 uint32_t em_read_reg_io(struct em_hw *hw, uint32_t offset);
434 void em_io_write(struct em_hw *hw, unsigned long port, uint32_t value);
435 void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);
436 int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up);
437 int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
438 int32_t em_set_d0_lplu_state(struct em_hw *hw, boolean_t active);
439 void em_set_pci_express_master_disable(struct em_hw *hw);
440 void em_enable_pciex_master(struct em_hw *hw);
441 int32_t em_disable_pciex_master(struct em_hw *hw);
442 int32_t em_get_auto_rd_done(struct em_hw *hw);
443 int32_t em_get_phy_cfg_done(struct em_hw *hw);
444 int32_t em_get_software_semaphore(struct em_hw *hw);
445 void em_release_software_semaphore(struct em_hw *hw);
446 int32_t em_check_phy_reset_block(struct em_hw *hw);
447 int32_t em_get_hw_eeprom_semaphore(struct em_hw *hw);
448 void em_put_hw_eeprom_semaphore(struct em_hw *hw);
449 int32_t em_commit_shadow_ram(struct em_hw *hw);
450 uint8_t em_arc_subsystem_valid(struct em_hw *hw);
451 
452 #define E1000_READ_REG_IO(a, reg) \
453  em_read_reg_io((a), E1000_##reg)
454 #define E1000_WRITE_REG_IO(a, reg, val) \
455  em_write_reg_io((a), E1000_##reg, val)
456 
457 /* PCI Device IDs */
458 #define E1000_DEV_ID_82542 0x1000
459 #define E1000_DEV_ID_82543GC_FIBER 0x1001
460 #define E1000_DEV_ID_82543GC_COPPER 0x1004
461 #define E1000_DEV_ID_82544EI_COPPER 0x1008
462 #define E1000_DEV_ID_82544EI_FIBER 0x1009
463 #define E1000_DEV_ID_82544GC_COPPER 0x100C
464 #define E1000_DEV_ID_82544GC_LOM 0x100D
465 #define E1000_DEV_ID_82540EM 0x100E
466 #define E1000_DEV_ID_82541ER_LOM 0x1014
467 #define E1000_DEV_ID_82540EM_LOM 0x1015
468 #define E1000_DEV_ID_82540EP_LOM 0x1016
469 #define E1000_DEV_ID_82540EP 0x1017
470 #define E1000_DEV_ID_82540EP_LP 0x101E
471 #define E1000_DEV_ID_82545EM_COPPER 0x100F
472 #define E1000_DEV_ID_82545EM_FIBER 0x1011
473 #define E1000_DEV_ID_82545GM_COPPER 0x1026
474 #define E1000_DEV_ID_82545GM_FIBER 0x1027
475 #define E1000_DEV_ID_82545GM_SERDES 0x1028
476 #define E1000_DEV_ID_82546EB_COPPER 0x1010
477 #define E1000_DEV_ID_82546EB_FIBER 0x1012
478 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
479 #define E1000_DEV_ID_82541EI 0x1013
480 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
481 #define E1000_DEV_ID_82541ER 0x1078
482 #define E1000_DEV_ID_82547GI 0x1075
483 #define E1000_DEV_ID_82541GI 0x1076
484 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
485 #define E1000_DEV_ID_82541GI_LF 0x107C
486 #define E1000_DEV_ID_82546GB_COPPER 0x1079
487 #define E1000_DEV_ID_82546GB_FIBER 0x107A
488 #define E1000_DEV_ID_82546GB_SERDES 0x107B
489 #define E1000_DEV_ID_82546GB_PCIE 0x108A
490 #define E1000_DEV_ID_82547EI 0x1019
491 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
492 #define E1000_DEV_ID_82573E 0x108B
493 #define E1000_DEV_ID_82573E_IAMT 0x108C
494 
495 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
496 
497 #define NODE_ADDRESS_SIZE 6
498 #define ETH_LENGTH_OF_ADDRESS 6
499 
500 /* MAC decode size is 128K - This is the size of BAR0 */
501 #define MAC_DECODE_SIZE (128 * 1024)
502 
503 #define E1000_82542_2_0_REV_ID 2
504 #define E1000_82542_2_1_REV_ID 3
505 #define E1000_REVISION_0 0
506 #define E1000_REVISION_1 1
507 #define E1000_REVISION_2 2
508 #define E1000_REVISION_3 3
509 
510 #define SPEED_10 10
511 #define SPEED_100 100
512 #define SPEED_1000 1000
513 #define HALF_DUPLEX 1
514 #define FULL_DUPLEX 2
515 
516 /* The sizes (in bytes) of a ethernet packet */
517 #define ENET_HEADER_SIZE 14
518 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
519 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
520 #define ETHERNET_FCS_SIZE 4
521 #define MAXIMUM_ETHERNET_PACKET_SIZE \
522  (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
523 #define MINIMUM_ETHERNET_PACKET_SIZE \
524  (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
525 #define CRC_LENGTH ETHERNET_FCS_SIZE
526 #define MAX_JUMBO_FRAME_SIZE 0x3F00
527 
528 
529 /* 802.1q VLAN Packet Sizes */
530 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
531 
532 /* Ethertype field values */
533 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
534 #define ETHERNET_IP_TYPE 0x0800 /* IP packets */
535 #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
536 
537 /* Packet Header defines */
538 #define IP_PROTOCOL_TCP 6
539 #define IP_PROTOCOL_UDP 0x11
540 
541 /* This defines the bits that are set in the Interrupt Mask
542  * Set/Read Register. Each bit is documented below:
543  * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
544  * o RXSEQ = Receive Sequence Error
545  */
546 #define POLL_IMS_ENABLE_MASK ( \
547  E1000_IMS_RXDMT0 | \
548  E1000_IMS_RXSEQ)
549 
550 /* This defines the bits that are set in the Interrupt Mask
551  * Set/Read Register. Each bit is documented below:
552  * o RXT0 = Receiver Timer Interrupt (ring 0)
553  * o TXDW = Transmit Descriptor Written Back
554  * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
555  * o RXSEQ = Receive Sequence Error
556  * o LSC = Link Status Change
557  */
558 #define IMS_ENABLE_MASK ( \
559  E1000_IMS_RXT0 | \
560  E1000_IMS_TXDW | \
561  E1000_IMS_RXDMT0 | \
562  E1000_IMS_RXSEQ | \
563  E1000_IMS_LSC)
564 
565 
566 /* Number of high/low register pairs in the RAR. The RAR (Receive Address
567  * Registers) holds the directed and multicast addresses that we monitor. We
568  * reserve one of these spots for our directed address, allowing us room for
569  * E1000_RAR_ENTRIES - 1 multicast addresses.
570  */
571 #define E1000_RAR_ENTRIES 15
572 
573 #define MIN_NUMBER_OF_DESCRIPTORS 8
574 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
575 
576 /* Receive Descriptor */
577 struct em_rx_desc {
578  uint64_t buffer_addr; /* Address of the descriptor's data buffer */
579  uint16_t length; /* Length of data DMAed into data buffer */
580  uint16_t csum; /* Packet checksum */
581  uint8_t status; /* Descriptor status */
582  uint8_t errors; /* Descriptor Errors */
583  uint16_t special;
584 };
585 
586 /* Receive Descriptor - Extended */
587 union em_rx_desc_extended {
588  struct {
589  uint64_t buffer_addr;
590  uint64_t reserved;
591  } read;
592  struct {
593  struct {
594  uint32_t mrq; /* Multiple Rx Queues */
595  union {
596  uint32_t rss; /* RSS Hash */
597  struct {
598  uint16_t ip_id; /* IP id */
599  uint16_t csum; /* Packet Checksum */
600  } csum_ip;
601  } hi_dword;
602  } lower;
603  struct {
604  uint32_t status_error; /* ext status/error */
605  uint16_t length;
606  uint16_t vlan; /* VLAN tag */
607  } upper;
608  } wb; /* writeback */
609 };
610 
611 #define MAX_PS_BUFFERS 4
612 /* Receive Descriptor - Packet Split */
613 union em_rx_desc_packet_split {
614  struct {
615  /* one buffer for protocol header(s), three data buffers */
616  uint64_t buffer_addr[MAX_PS_BUFFERS];
617  } read;
618  struct {
619  struct {
620  uint32_t mrq; /* Multiple Rx Queues */
621  union {
622  uint32_t rss; /* RSS Hash */
623  struct {
624  uint16_t ip_id; /* IP id */
625  uint16_t csum; /* Packet Checksum */
626  } csum_ip;
627  } hi_dword;
628  } lower;
629  struct {
630  uint32_t status_error; /* ext status/error */
631  uint16_t length0; /* length of buffer 0 */
632  uint16_t vlan; /* VLAN tag */
633  } middle;
634  struct {
635  uint16_t header_status;
636  uint16_t length[3]; /* length of buffers 1-3 */
637  } upper;
638  uint64_t reserved;
639  } wb; /* writeback */
640 };
641 
642 /* Receive Decriptor bit definitions */
643 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
644 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
645 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
646 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
647 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
648 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
649 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
650 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
651 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
652 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
653 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
654 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
655 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
656 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
657 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
658 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
659 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
660 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
661 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
662 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
663 #define E1000_RXD_SPC_PRI_SHIFT 13
664 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
665 #define E1000_RXD_SPC_CFI_SHIFT 12
666 
667 #define E1000_RXDEXT_STATERR_CE 0x01000000
668 #define E1000_RXDEXT_STATERR_SE 0x02000000
669 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
670 #define E1000_RXDEXT_STATERR_CXE 0x10000000
671 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
672 #define E1000_RXDEXT_STATERR_IPE 0x40000000
673 #define E1000_RXDEXT_STATERR_RXE 0x80000000
674 
675 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
676 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
677 
678 /* mask to determine if packets should be dropped due to frame errors */
679 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
680  E1000_RXD_ERR_CE | \
681  E1000_RXD_ERR_SE | \
682  E1000_RXD_ERR_SEQ | \
683  E1000_RXD_ERR_CXE | \
684  E1000_RXD_ERR_RXE)
685 
686 
687 /* Same mask, but for extended and packet split descriptors */
688 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
689  E1000_RXDEXT_STATERR_CE | \
690  E1000_RXDEXT_STATERR_SE | \
691  E1000_RXDEXT_STATERR_SEQ | \
692  E1000_RXDEXT_STATERR_CXE | \
693  E1000_RXDEXT_STATERR_RXE)
694 
695 /* Transmit Descriptor */
696 struct em_tx_desc {
697  uint64_t buffer_addr; /* Address of the descriptor's data buffer */
698  union {
699  uint32_t data;
700  struct {
701  uint16_t length; /* Data buffer length */
702  uint8_t cso; /* Checksum offset */
703  uint8_t cmd; /* Descriptor control */
704  } flags;
705  } lower;
706  union {
707  uint32_t data;
708  struct {
709  uint8_t status; /* Descriptor status */
710  uint8_t css; /* Checksum start */
711  uint16_t special;
712  } fields;
713  } upper;
714 };
715 
716 /* Transmit Descriptor bit definitions */
717 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
718 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
719 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
720 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
721 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
722 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
723 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
724 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
725 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
726 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
727 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
728 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
729 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
730 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
731 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
732 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
733 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
734 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
735 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
736 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
737 
738 /* Offload Context Descriptor */
739 struct em_context_desc {
740  union {
741  uint32_t ip_config;
742  struct {
743  uint8_t ipcss; /* IP checksum start */
744  uint8_t ipcso; /* IP checksum offset */
745  uint16_t ipcse; /* IP checksum end */
746  } ip_fields;
747  } lower_setup;
748  union {
749  uint32_t tcp_config;
750  struct {
751  uint8_t tucss; /* TCP checksum start */
752  uint8_t tucso; /* TCP checksum offset */
753  uint16_t tucse; /* TCP checksum end */
754  } tcp_fields;
755  } upper_setup;
756  uint32_t cmd_and_length; /* */
757  union {
758  uint32_t data;
759  struct {
760  uint8_t status; /* Descriptor status */
761  uint8_t hdr_len; /* Header length */
762  uint16_t mss; /* Maximum segment size */
763  } fields;
764  } tcp_seg_setup;
765 };
766 
767 /* Offload data descriptor */
768 struct em_data_desc {
769  uint64_t buffer_addr; /* Address of the descriptor's buffer address */
770  union {
771  uint32_t data;
772  struct {
773  uint16_t length; /* Data buffer length */
774  uint8_t typ_len_ext; /* */
775  uint8_t cmd; /* */
776  } flags;
777  } lower;
778  union {
779  uint32_t data;
780  struct {
781  uint8_t status; /* Descriptor status */
782  uint8_t popts; /* Packet Options */
783  uint16_t special; /* */
784  } fields;
785  } upper;
786 };
787 
788 /* Filters */
789 #define E1000_NUM_UNICAST 16 /* Unicast filter entries */
790 #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
791 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
792 
793 
794 /* Receive Address Register */
795 struct em_rar {
796  volatile uint32_t low; /* receive address low */
797  volatile uint32_t high; /* receive address high */
798 };
799 
800 /* Number of entries in the Multicast Table Array (MTA). */
801 #define E1000_NUM_MTA_REGISTERS 128
802 
803 /* IPv4 Address Table Entry */
804 struct em_ipv4_at_entry {
805  volatile uint32_t ipv4_addr; /* IP Address (RW) */
806  volatile uint32_t reserved;
807 };
808 
809 /* Four wakeup IP addresses are supported */
810 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
811 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
812 #define E1000_IP6AT_SIZE 1
813 
814 /* IPv6 Address Table Entry */
815 struct em_ipv6_at_entry {
816  volatile uint8_t ipv6_addr[16];
817 };
818 
819 /* Flexible Filter Length Table Entry */
820 struct em_fflt_entry {
821  volatile uint32_t length; /* Flexible Filter Length (RW) */
822  volatile uint32_t reserved;
823 };
824 
825 /* Flexible Filter Mask Table Entry */
826 struct em_ffmt_entry {
827  volatile uint32_t mask; /* Flexible Filter Mask (RW) */
828  volatile uint32_t reserved;
829 };
830 
831 /* Flexible Filter Value Table Entry */
832 struct em_ffvt_entry {
833  volatile uint32_t value; /* Flexible Filter Value (RW) */
834  volatile uint32_t reserved;
835 };
836 
837 /* Four Flexible Filters are supported */
838 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
839 
840 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
841 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
842 
843 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
844 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
845 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
846 
847 /* Register Set. (82543, 82544)
848  *
849  * Registers are defined to be 32 bits and should be accessed as 32 bit values.
850  * These registers are physically located on the NIC, but are mapped into the
851  * host memory address space.
852  *
853  * RW - register is both readable and writable
854  * RO - register is read only
855  * WO - register is write only
856  * R/clr - register is read only and is cleared when read
857  * A - register array
858  */
859 #define E1000_CTRL 0x00000 /* Device Control - RW */
860 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
861 #define E1000_STATUS 0x00008 /* Device Status - RO */
862 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
863 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
864 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
865 #define E1000_FLA 0x0001C /* Flash Access - RW */
866 #define E1000_MDIC 0x00020 /* MDI Control - RW */
867 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
868 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
869 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
870 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
871 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
872 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
873 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
874 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
875 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
876 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
877 #define E1000_RCTL 0x00100 /* RX Control - RW */
878 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
879 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
880 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
881 #define E1000_TCTL 0x00400 /* TX Control - RW */
882 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
883 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
884 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
885 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
886 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
887 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
888 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
889 #define E1000_PBS 0x01008 /* Packet Buffer Size */
890 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
891 #define E1000_FLASH_UPDATES 1000
892 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
893 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */
894 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
895 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
896 #define E1000_FLSWDATA 0x01034 /* FLASH data register */
897 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
898 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */
899 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
900 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
901 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
902 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
903 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
904 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
905 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
906 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
907 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
908 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
909 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
910 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
911 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
912 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
913 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
914 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
915 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
916 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
917 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
918 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
919 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
920 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
921 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
922 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
923 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
924 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
925 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
926 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
927 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
928 #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
929 #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
930 #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
931 #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
932 #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
933 #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
934 #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
935 #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
936 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
937 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
938 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
939 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
940 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
941 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
942 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
943 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
944 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
945 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
946 #define E1000_DC 0x04030 /* Defer Count - R/clr */
947 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
948 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
949 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
950 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
951 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
952 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
953 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
954 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
955 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
956 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
957 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
958 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
959 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
960 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
961 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
962 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
963 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
964 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
965 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
966 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
967 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
968 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
969 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
970 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
971 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
972 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
973 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
974 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
975 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
976 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
977 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
978 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
979 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
980 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
981 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
982 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
983 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
984 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
985 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
986 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
987 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
988 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
989 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
990 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
991 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
992 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
993 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
994 #define E1000_IAC 0x4100 /* Interrupt Assertion Count */
995 #define E1000_ICRXPTC 0x4104 /* Interrupt Cause Rx Packet Timer Expire Count */
996 #define E1000_ICRXATC 0x4108 /* Interrupt Cause Rx Absolute Timer Expire Count */
997 #define E1000_ICTXPTC 0x410C /* Interrupt Cause Tx Packet Timer Expire Count */
998 #define E1000_ICTXATC 0x4110 /* Interrupt Cause Tx Absolute Timer Expire Count */
999 #define E1000_ICTXQEC 0x4118 /* Interrupt Cause Tx Queue Empty Count */
1000 #define E1000_ICTXQMTC 0x411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
1001 #define E1000_ICRXDMTC 0x4120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
1002 #define E1000_ICRXOC 0x4124 /* Interrupt Cause Receiver Overrun Count */
1003 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
1004 #define E1000_RFCTL 0x05008 /* Receive Filter Control*/
1005 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
1006 #define E1000_RA 0x05400 /* Receive Address - RW Array */
1007 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
1008 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
1009 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
1010 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
1011 #define E1000_MANC 0x05820 /* Management Control - RW */
1012 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
1013 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
1014 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
1015 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
1016 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
1017 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
1018 #define E1000_HOST_IF 0x08800 /* Host Interface */
1019 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
1020 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1021 
1022 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
1023 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1024 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1025 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1026 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1027 #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1028 #define E1000_SWSM 0x05B50 /* SW Semaphore */
1029 #define E1000_FWSM 0x05B54 /* FW Semaphore */
1030 #define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1031 #define E1000_HICR 0x08F00 /* Host Inteface Control */
1032 /* Register Set (82542)
1033  *
1034  * Some of the 82542 registers are located at different offsets than they are
1035  * in more current versions of the 8254x. Despite the difference in location,
1036  * the registers function in the same manner.
1037  */
1038 #define E1000_82542_CTRL E1000_CTRL
1039 #define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1040 #define E1000_82542_STATUS E1000_STATUS
1041 #define E1000_82542_EECD E1000_EECD
1042 #define E1000_82542_EERD E1000_EERD
1043 #define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1044 #define E1000_82542_FLA E1000_FLA
1045 #define E1000_82542_MDIC E1000_MDIC
1046 #define E1000_82542_FCAL E1000_FCAL
1047 #define E1000_82542_FCAH E1000_FCAH
1048 #define E1000_82542_FCT E1000_FCT
1049 #define E1000_82542_VET E1000_VET
1050 #define E1000_82542_RA 0x00040
1051 #define E1000_82542_ICR E1000_ICR
1052 #define E1000_82542_ITR E1000_ITR
1053 #define E1000_82542_ICS E1000_ICS
1054 #define E1000_82542_IMS E1000_IMS
1055 #define E1000_82542_IMC E1000_IMC
1056 #define E1000_82542_RCTL E1000_RCTL
1057 #define E1000_82542_RDTR 0x00108
1058 #define E1000_82542_RDBAL 0x00110
1059 #define E1000_82542_RDBAH 0x00114
1060 #define E1000_82542_RDLEN 0x00118
1061 #define E1000_82542_RDH 0x00120
1062 #define E1000_82542_RDT 0x00128
1063 #define E1000_82542_FCRTH 0x00160
1064 #define E1000_82542_FCRTL 0x00168
1065 #define E1000_82542_FCTTV E1000_FCTTV
1066 #define E1000_82542_TXCW E1000_TXCW
1067 #define E1000_82542_RXCW E1000_RXCW
1068 #define E1000_82542_MTA 0x00200
1069 #define E1000_82542_TCTL E1000_TCTL
1070 #define E1000_82542_TIPG E1000_TIPG
1071 #define E1000_82542_TDBAL 0x00420
1072 #define E1000_82542_TDBAH 0x00424
1073 #define E1000_82542_TDLEN 0x00428
1074 #define E1000_82542_TDH 0x00430
1075 #define E1000_82542_TDT 0x00438
1076 #define E1000_82542_TIDV 0x00440
1077 #define E1000_82542_TBT E1000_TBT
1078 #define E1000_82542_AIT E1000_AIT
1079 #define E1000_82542_VFTA 0x00600
1080 #define E1000_82542_LEDCTL E1000_LEDCTL
1081 #define E1000_82542_PBA E1000_PBA
1082 #define E1000_82542_PBS E1000_PBS
1083 #define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1084 #define E1000_82542_EEARBC E1000_EEARBC
1085 #define E1000_82542_FLASHT E1000_FLASHT
1086 #define E1000_82542_EEWR E1000_EEWR
1087 #define E1000_82542_FLSWCTL E1000_FLSWCTL
1088 #define E1000_82542_FLSWDATA E1000_FLSWDATA
1089 #define E1000_82542_FLSWCNT E1000_FLSWCNT
1090 #define E1000_82542_FLOP E1000_FLOP
1091 #define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1092 #define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1093 #define E1000_82542_ERT E1000_ERT
1094 #define E1000_82542_RXDCTL E1000_RXDCTL
1095 #define E1000_82542_RADV E1000_RADV
1096 #define E1000_82542_RSRPD E1000_RSRPD
1097 #define E1000_82542_TXDMAC E1000_TXDMAC
1098 #define E1000_82542_TDFHS E1000_TDFHS
1099 #define E1000_82542_TDFTS E1000_TDFTS
1100 #define E1000_82542_TDFPC E1000_TDFPC
1101 #define E1000_82542_TXDCTL E1000_TXDCTL
1102 #define E1000_82542_TADV E1000_TADV
1103 #define E1000_82542_TSPMT E1000_TSPMT
1104 #define E1000_82542_CRCERRS E1000_CRCERRS
1105 #define E1000_82542_ALGNERRC E1000_ALGNERRC
1106 #define E1000_82542_SYMERRS E1000_SYMERRS
1107 #define E1000_82542_RXERRC E1000_RXERRC
1108 #define E1000_82542_MPC E1000_MPC
1109 #define E1000_82542_SCC E1000_SCC
1110 #define E1000_82542_ECOL E1000_ECOL
1111 #define E1000_82542_MCC E1000_MCC
1112 #define E1000_82542_LATECOL E1000_LATECOL
1113 #define E1000_82542_COLC E1000_COLC
1114 #define E1000_82542_DC E1000_DC
1115 #define E1000_82542_TNCRS E1000_TNCRS
1116 #define E1000_82542_SEC E1000_SEC
1117 #define E1000_82542_CEXTERR E1000_CEXTERR
1118 #define E1000_82542_RLEC E1000_RLEC
1119 #define E1000_82542_XONRXC E1000_XONRXC
1120 #define E1000_82542_XONTXC E1000_XONTXC
1121 #define E1000_82542_XOFFRXC E1000_XOFFRXC
1122 #define E1000_82542_XOFFTXC E1000_XOFFTXC
1123 #define E1000_82542_FCRUC E1000_FCRUC
1124 #define E1000_82542_PRC64 E1000_PRC64
1125 #define E1000_82542_PRC127 E1000_PRC127
1126 #define E1000_82542_PRC255 E1000_PRC255
1127 #define E1000_82542_PRC511 E1000_PRC511
1128 #define E1000_82542_PRC1023 E1000_PRC1023
1129 #define E1000_82542_PRC1522 E1000_PRC1522
1130 #define E1000_82542_GPRC E1000_GPRC
1131 #define E1000_82542_BPRC E1000_BPRC
1132 #define E1000_82542_MPRC E1000_MPRC
1133 #define E1000_82542_GPTC E1000_GPTC
1134 #define E1000_82542_GORCL E1000_GORCL
1135 #define E1000_82542_GORCH E1000_GORCH
1136 #define E1000_82542_GOTCL E1000_GOTCL
1137 #define E1000_82542_GOTCH E1000_GOTCH
1138 #define E1000_82542_RNBC E1000_RNBC
1139 #define E1000_82542_RUC E1000_RUC
1140 #define E1000_82542_RFC E1000_RFC
1141 #define E1000_82542_ROC E1000_ROC
1142 #define E1000_82542_RJC E1000_RJC
1143 #define E1000_82542_MGTPRC E1000_MGTPRC
1144 #define E1000_82542_MGTPDC E1000_MGTPDC
1145 #define E1000_82542_MGTPTC E1000_MGTPTC
1146 #define E1000_82542_TORL E1000_TORL
1147 #define E1000_82542_TORH E1000_TORH
1148 #define E1000_82542_TOTL E1000_TOTL
1149 #define E1000_82542_TOTH E1000_TOTH
1150 #define E1000_82542_TPR E1000_TPR
1151 #define E1000_82542_TPT E1000_TPT
1152 #define E1000_82542_PTC64 E1000_PTC64
1153 #define E1000_82542_PTC127 E1000_PTC127
1154 #define E1000_82542_PTC255 E1000_PTC255
1155 #define E1000_82542_PTC511 E1000_PTC511
1156 #define E1000_82542_PTC1023 E1000_PTC1023
1157 #define E1000_82542_PTC1522 E1000_PTC1522
1158 #define E1000_82542_MPTC E1000_MPTC
1159 #define E1000_82542_BPTC E1000_BPTC
1160 #define E1000_82542_TSCTC E1000_TSCTC
1161 #define E1000_82542_TSCTFC E1000_TSCTFC
1162 #define E1000_82542_RXCSUM E1000_RXCSUM
1163 #define E1000_82542_WUC E1000_WUC
1164 #define E1000_82542_WUFC E1000_WUFC
1165 #define E1000_82542_WUS E1000_WUS
1166 #define E1000_82542_MANC E1000_MANC
1167 #define E1000_82542_IPAV E1000_IPAV
1168 #define E1000_82542_IP4AT E1000_IP4AT
1169 #define E1000_82542_IP6AT E1000_IP6AT
1170 #define E1000_82542_WUPL E1000_WUPL
1171 #define E1000_82542_WUPM E1000_WUPM
1172 #define E1000_82542_FFLT E1000_FFLT
1173 #define E1000_82542_TDFH 0x08010
1174 #define E1000_82542_TDFT 0x08018
1175 #define E1000_82542_FFMT E1000_FFMT
1176 #define E1000_82542_FFVT E1000_FFVT
1177 #define E1000_82542_HOST_IF E1000_HOST_IF
1178 #define E1000_82542_IAM E1000_IAM
1179 #define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1180 #define E1000_82542_PSRCTL E1000_PSRCTL
1181 #define E1000_82542_RAID E1000_RAID
1182 #define E1000_82542_TARC0 E1000_TARC0
1183 #define E1000_82542_TDBAL1 E1000_TDBAL1
1184 #define E1000_82542_TDBAH1 E1000_TDBAH1
1185 #define E1000_82542_TDLEN1 E1000_TDLEN1
1186 #define E1000_82542_TDH1 E1000_TDH1
1187 #define E1000_82542_TDT1 E1000_TDT1
1188 #define E1000_82542_TXDCTL1 E1000_TXDCTL1
1189 #define E1000_82542_TARC1 E1000_TARC1
1190 #define E1000_82542_RFCTL E1000_RFCTL
1191 #define E1000_82542_GCR E1000_GCR
1192 #define E1000_82542_GSCL_1 E1000_GSCL_1
1193 #define E1000_82542_GSCL_2 E1000_GSCL_2
1194 #define E1000_82542_GSCL_3 E1000_GSCL_3
1195 #define E1000_82542_GSCL_4 E1000_GSCL_4
1196 #define E1000_82542_FACTPS E1000_FACTPS
1197 #define E1000_82542_SWSM E1000_SWSM
1198 #define E1000_82542_FWSM E1000_FWSM
1199 #define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1200 #define E1000_82542_IAC E1000_IAC
1201 #define E1000_82542_ICRXPTC E1000_ICRXPTC
1202 #define E1000_82542_ICRXATC E1000_ICRXATC
1203 #define E1000_82542_ICTXPTC E1000_ICTXPTC
1204 #define E1000_82542_ICTXATC E1000_ICTXATC
1205 #define E1000_82542_ICTXQEC E1000_ICTXQEC
1206 #define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1207 #define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1208 #define E1000_82542_ICRXOC E1000_ICRXOC
1209 #define E1000_82542_HICR E1000_HICR
1210 
1211 /* Statistics counters collected by the MAC */
1212 struct em_hw_stats {
1213  uint64_t crcerrs;
1214  uint64_t algnerrc;
1215  uint64_t symerrs;
1216  uint64_t rxerrc;
1217  uint64_t mpc;
1218  uint64_t scc;
1219  uint64_t ecol;
1220  uint64_t mcc;
1221  uint64_t latecol;
1222  uint64_t colc;
1223  uint64_t dc;
1224  uint64_t tncrs;
1225  uint64_t sec;
1226  uint64_t cexterr;
1227  uint64_t rlec;
1228  uint64_t xonrxc;
1229  uint64_t xontxc;
1230  uint64_t xoffrxc;
1231  uint64_t xofftxc;
1232  uint64_t fcruc;
1233  uint64_t prc64;
1234  uint64_t prc127;
1235  uint64_t prc255;
1236  uint64_t prc511;
1237  uint64_t prc1023;
1238  uint64_t prc1522;
1239  uint64_t gprc;
1240  uint64_t bprc;
1241  uint64_t mprc;
1242  uint64_t gptc;
1243  uint64_t gorcl;
1244  uint64_t gorch;
1245  uint64_t gotcl;
1246  uint64_t gotch;
1247  uint64_t rnbc;
1248  uint64_t ruc;
1249  uint64_t rfc;
1250  uint64_t roc;
1251  uint64_t rjc;
1252  uint64_t mgprc;
1253  uint64_t mgpdc;
1254  uint64_t mgptc;
1255  uint64_t torl;
1256  uint64_t torh;
1257  uint64_t totl;
1258  uint64_t toth;
1259  uint64_t tpr;
1260  uint64_t tpt;
1261  uint64_t ptc64;
1262  uint64_t ptc127;
1263  uint64_t ptc255;
1264  uint64_t ptc511;
1265  uint64_t ptc1023;
1266  uint64_t ptc1522;
1267  uint64_t mptc;
1268  uint64_t bptc;
1269  uint64_t tsctc;
1270  uint64_t tsctfc;
1271  uint64_t iac;
1272  uint64_t icrxptc;
1273  uint64_t icrxatc;
1274  uint64_t ictxptc;
1275  uint64_t ictxatc;
1276  uint64_t ictxqec;
1277  uint64_t ictxqmtc;
1278  uint64_t icrxdmtc;
1279  uint64_t icrxoc;
1280 };
1281 
1282 /* Structure containing variables used by the shared code (em_hw.c) */
1283 struct em_hw {
1284  uint8_t *hw_addr;
1285  uint8_t *flash_address;
1286  em_mac_type mac_type;
1287  em_phy_type phy_type;
1288  uint32_t phy_init_script;
1289  em_media_type media_type;
1290  void *back;
1291  em_fc_type fc;
1292  em_bus_speed bus_speed;
1293  em_bus_width bus_width;
1294  em_bus_type bus_type;
1295  struct em_eeprom_info eeprom;
1296  em_ms_type master_slave;
1297  em_ms_type original_master_slave;
1298  em_ffe_config ffe_config_state;
1299  uint32_t asf_firmware_present;
1300  uint32_t eeprom_semaphore_present;
1301  unsigned long io_base;
1302  uint32_t phy_id;
1303  uint32_t phy_revision;
1304  uint32_t phy_addr;
1305  uint32_t original_fc;
1306  uint32_t txcw;
1307  uint32_t autoneg_failed;
1308  uint32_t max_frame_size;
1309  uint32_t min_frame_size;
1310  uint32_t mc_filter_type;
1311  uint32_t num_mc_addrs;
1312  uint32_t collision_delta;
1313  uint32_t tx_packet_delta;
1314  uint32_t ledctl_default;
1315  uint32_t ledctl_mode1;
1316  uint32_t ledctl_mode2;
1317  boolean_t tx_pkt_filtering;
1318  struct em_host_mng_dhcp_cookie mng_cookie;
1319  uint16_t phy_spd_default;
1320  uint16_t autoneg_advertised;
1321  uint16_t pci_cmd_word;
1322  uint16_t fc_high_water;
1323  uint16_t fc_low_water;
1324  uint16_t fc_pause_time;
1325  uint16_t current_ifs_val;
1326  uint16_t ifs_min_val;
1327  uint16_t ifs_max_val;
1328  uint16_t ifs_step_size;
1329  uint16_t ifs_ratio;
1330  uint16_t device_id;
1331  uint16_t vendor_id;
1332  uint16_t subsystem_id;
1333  uint16_t subsystem_vendor_id;
1334  uint8_t revision_id;
1335  uint8_t autoneg;
1336  uint8_t mdix;
1337  uint8_t forced_speed_duplex;
1338  uint8_t wait_autoneg_complete;
1339  uint8_t dma_fairness;
1340  uint8_t mac_addr[NODE_ADDRESS_SIZE];
1341  uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
1342  boolean_t disable_polarity_correction;
1343  boolean_t speed_downgraded;
1344  em_smart_speed smart_speed;
1345  em_dsp_config dsp_config_state;
1346  boolean_t get_link_status;
1347  boolean_t serdes_link_down;
1348  boolean_t tbi_compatibility_en;
1349  boolean_t tbi_compatibility_on;
1350  boolean_t phy_reset_disable;
1351  boolean_t fc_send_xon;
1352  boolean_t fc_strict_ieee;
1353  boolean_t report_tx_early;
1354  boolean_t adaptive_ifs;
1355  boolean_t ifs_params_forced;
1356  boolean_t in_ifs_mode;
1357  boolean_t mng_reg_access_disabled;
1358 };
1359 
1360 
1361 #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1362 #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1363 #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1364 #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1365 #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1366 #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1367 #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1368 #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1369 /* Register Bit Masks */
1370 /* Device Control */
1371 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1372 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1373 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1374 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1375 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1376 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1377 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1378 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1379 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1380 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1381 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1382 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1383 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1384 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1385 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1386 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1387 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1388 #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1389 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1390 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1391 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1392 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1393 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1394 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1395 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1396 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1397 #define E1000_CTRL_RST 0x04000000 /* Global reset */
1398 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1399 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1400 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1401 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1402 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1403 
1404 /* Device Status */
1405 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1406 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1407 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1408 #define E1000_STATUS_FUNC_SHIFT 2
1409 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1410 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1411 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1412 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1413 #define E1000_STATUS_SPEED_MASK 0x000000C0
1414 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1415 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1416 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1417 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1418 #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1419 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1420 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1421 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1422 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1423 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1424 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1425 
1426 /* Constants used to intrepret the masked PCI-X bus speed. */
1427 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1428 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1429 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1430 
1431 /* EEPROM/Flash Control */
1432 #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1433 #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1434 #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1435 #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1436 #define E1000_EECD_FWE_MASK 0x00000030
1437 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1438 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1439 #define E1000_EECD_FWE_SHIFT 4
1440 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1441 #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1442 #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1443 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1444 #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1445  * (0-small, 1-large) */
1446 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1447 #ifndef E1000_EEPROM_GRANT_ATTEMPTS
1448 #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1449 #endif
1450 #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1451 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1452 #define E1000_EECD_SIZE_EX_SHIFT 11
1453 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1454 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1455 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1456 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1457 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1458 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1459 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1460 #define E1000_STM_OPCODE 0xDB00
1461 #define E1000_HICR_FW_RESET 0xC0
1462 
1463 /* EEPROM Read */
1464 #define E1000_EERD_START 0x00000001 /* Start Read */
1465 #define E1000_EERD_DONE 0x00000010 /* Read Done */
1466 #define E1000_EERD_ADDR_SHIFT 8
1467 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1468 #define E1000_EERD_DATA_SHIFT 16
1469 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1470 
1471 /* SPI EEPROM Status Register */
1472 #define EEPROM_STATUS_RDY_SPI 0x01
1473 #define EEPROM_STATUS_WEN_SPI 0x02
1474 #define EEPROM_STATUS_BP0_SPI 0x04
1475 #define EEPROM_STATUS_BP1_SPI 0x08
1476 #define EEPROM_STATUS_WPEN_SPI 0x80
1477 
1478 /* Extended Device Control */
1479 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1480 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1481 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1482 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1483 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1484 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1485 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1486 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1487 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1488 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1489 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1490 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1491 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1492 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1493 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1494 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1495 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1496 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1497 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1498 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1499 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1500 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1501 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1502 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1503 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1504 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1505 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1506 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1507 
1508 /* MDI Control */
1509 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1510 #define E1000_MDIC_REG_MASK 0x001F0000
1511 #define E1000_MDIC_REG_SHIFT 16
1512 #define E1000_MDIC_PHY_MASK 0x03E00000
1513 #define E1000_MDIC_PHY_SHIFT 21
1514 #define E1000_MDIC_OP_WRITE 0x04000000
1515 #define E1000_MDIC_OP_READ 0x08000000
1516 #define E1000_MDIC_READY 0x10000000
1517 #define E1000_MDIC_INT_EN 0x20000000
1518 #define E1000_MDIC_ERROR 0x40000000
1519 
1520 /* LED Control */
1521 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1522 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
1523 #define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
1524 #define E1000_LEDCTL_LED0_IVRT 0x00000040
1525 #define E1000_LEDCTL_LED0_BLINK 0x00000080
1526 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1527 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
1528 #define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
1529 #define E1000_LEDCTL_LED1_IVRT 0x00004000
1530 #define E1000_LEDCTL_LED1_BLINK 0x00008000
1531 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1532 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
1533 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
1534 #define E1000_LEDCTL_LED2_IVRT 0x00400000
1535 #define E1000_LEDCTL_LED2_BLINK 0x00800000
1536 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1537 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
1538 #define E1000_LEDCTL_LED3_IVRT 0x40000000
1539 #define E1000_LEDCTL_LED3_BLINK 0x80000000
1540 
1541 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1542 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1543 #define E1000_LEDCTL_MODE_LINK_UP 0x2
1544 #define E1000_LEDCTL_MODE_ACTIVITY 0x3
1545 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1546 #define E1000_LEDCTL_MODE_LINK_10 0x5
1547 #define E1000_LEDCTL_MODE_LINK_100 0x6
1548 #define E1000_LEDCTL_MODE_LINK_1000 0x7
1549 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1550 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1551 #define E1000_LEDCTL_MODE_COLLISION 0xA
1552 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1553 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1554 #define E1000_LEDCTL_MODE_PAUSED 0xD
1555 #define E1000_LEDCTL_MODE_LED_ON 0xE
1556 #define E1000_LEDCTL_MODE_LED_OFF 0xF
1557 
1558 /* Receive Address */
1559 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1560 
1561 /* Interrupt Cause Read */
1562 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1563 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1564 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1565 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1566 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1567 #define E1000_ICR_RXO 0x00000040 /* rx overrun */
1568 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1569 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1570 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1571 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1572 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1573 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1574 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1575 #define E1000_ICR_TXD_LOW 0x00008000
1576 #define E1000_ICR_SRPD 0x00010000
1577 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1578 #define E1000_ICR_MNG 0x00040000 /* Manageability event */
1579 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1580 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1581 
1582 /* Interrupt Cause Set */
1583 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1584 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1585 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1586 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1587 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1588 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1589 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1590 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1591 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1592 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1593 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1594 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1595 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1596 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1597 #define E1000_ICS_SRPD E1000_ICR_SRPD
1598 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1599 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1600 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1601 
1602 /* Interrupt Mask Set */
1603 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1604 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1605 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1606 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1607 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1608 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1609 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1610 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1611 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1612 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1613 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1614 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1615 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1616 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1617 #define E1000_IMS_SRPD E1000_ICR_SRPD
1618 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1619 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1620 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1621 
1622 /* Interrupt Mask Clear */
1623 #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1624 #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1625 #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1626 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1627 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1628 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1629 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1630 #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1631 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1632 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1633 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1634 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1635 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1636 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1637 #define E1000_IMC_SRPD E1000_ICR_SRPD
1638 #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1639 #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1640 #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1641 
1642 /* Receive Control */
1643 #define E1000_RCTL_RST 0x00000001 /* Software reset */
1644 #define E1000_RCTL_EN 0x00000002 /* enable */
1645 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1646 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1647 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1648 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1649 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1650 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1651 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1652 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1653 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1654 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1655 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1656 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1657 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1658 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1659 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1660 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1661 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1662 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1663 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1664 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1665 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1666 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1667 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1668 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1669 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1670 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1671 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1672 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1673 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1674 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1675 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1676 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1677 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1678 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1679 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1680 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1681 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1682 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1683 
1684 /* Use byte values for the following shift parameters
1685  * Usage:
1686  * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1687  * E1000_PSRCTL_BSIZE0_MASK) |
1688  * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1689  * E1000_PSRCTL_BSIZE1_MASK) |
1690  * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1691  * E1000_PSRCTL_BSIZE2_MASK) |
1692  * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1693  * E1000_PSRCTL_BSIZE3_MASK))
1694  * where value0 = [128..16256], default=256
1695  * value1 = [1024..64512], default=4096
1696  * value2 = [0..64512], default=4096
1697  * value3 = [0..64512], default=0
1698  */
1699 
1700 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1701 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1702 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1703 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1704 
1705 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1706 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1707 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1708 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1709 
1710 /* Receive Descriptor */
1711 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1712 #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1713 #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1714 #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1715 #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1716 
1717 /* Flow Control */
1718 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1719 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1720 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1721 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1722 
1723 /* Header split receive */
1724 #define E1000_RFCTL_ISCSI_DIS 0x00000001
1725 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1726 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1727 #define E1000_RFCTL_NFSW_DIS 0x00000040
1728 #define E1000_RFCTL_NFSR_DIS 0x00000080
1729 #define E1000_RFCTL_NFS_VER_MASK 0x00000300
1730 #define E1000_RFCTL_NFS_VER_SHIFT 8
1731 #define E1000_RFCTL_IPV6_DIS 0x00000400
1732 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1733 #define E1000_RFCTL_ACK_DIS 0x00001000
1734 #define E1000_RFCTL_ACKD_DIS 0x00002000
1735 #define E1000_RFCTL_IPFRSP_DIS 0x00004000
1736 #define E1000_RFCTL_EXTEN 0x00008000
1737 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1738 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1739 
1740 /* Receive Descriptor Control */
1741 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1742 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1743 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1744 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1745 
1746 /* Transmit Descriptor Control */
1747 #define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1748 #define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1749 #define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1750 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1751 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1752 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1753 #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1754  still to be processed. */
1755 
1756 /* Transmit Configuration Word */
1757 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1758 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1759 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1760 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1761 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1762 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1763 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1764 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1765 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1766 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1767 
1768 /* Receive Configuration Word */
1769 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1770 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1771 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1772 #define E1000_RXCW_CC 0x10000000 /* Receive config change */
1773 #define E1000_RXCW_C 0x20000000 /* Receive config */
1774 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1775 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1776 
1777 /* Transmit Control */
1778 #define E1000_TCTL_RST 0x00000001 /* software reset */
1779 #define E1000_TCTL_EN 0x00000002 /* enable tx */
1780 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1781 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1782 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1783 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1784 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1785 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1786 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1787 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1788 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
1789 
1790 /* Receive Checksum Control */
1791 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1792 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1793 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1794 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1795 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1796 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1797 
1798 
1799 /* Definitions for power management and wakeup registers */
1800 /* Wake Up Control */
1801 #define E1000_WUC_APME 0x00000001 /* APM Enable */
1802 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1803 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1804 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1805 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */
1806 
1807 /* Wake Up Filter Control */
1808 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1809 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1810 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1811 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1812 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1813 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1814 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1815 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1816 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
1817 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1818 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1819 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1820 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1821 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1822 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1823 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1824 
1825 /* Wake Up Status */
1826 #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1827 #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1828 #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1829 #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1830 #define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1831 #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1832 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1833 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1834 #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1835 #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1836 #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1837 #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1838 #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1839 
1840 /* Management Control */
1841 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1842 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1843 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1844 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1845 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1846 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1847 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1848 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1849 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1850 #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1851  * Filtering */
1852 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
1853 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1854 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1855 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
1856 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
1857 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
1858  * filtering */
1859 #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
1860  * memory */
1861 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
1862  * filtering */
1863 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
1864 #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
1865 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1866 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1867 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1868 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
1869 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
1870 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
1871 
1872 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1873 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1874 
1875 /* SW Semaphore Register */
1876 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1877 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1878 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1879 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
1880 
1881 /* FW Semaphore Register */
1882 #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
1883 #define E1000_FWSM_MODE_SHIFT 1
1884 #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
1885 
1886 /* FFLT Debug Register */
1887 #define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
1888 
1889 typedef enum {
1890  em_mng_mode_none = 0,
1891  em_mng_mode_asf,
1892  em_mng_mode_pt,
1893  em_mng_mode_ipmi,
1894  em_mng_mode_host_interface_only
1895 } em_mng_mode;
1896 
1897 /* Host Inteface Control Register */
1898 #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
1899 #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
1900  * to put command in RAM */
1901 #define E1000_HICR_SV 0x00000004 /* Status Validity */
1902 #define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
1903 
1904 /* Host Interface Command Interface - Address range 0x8800-0x8EFF */
1905 #define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
1906 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
1907 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
1908 #define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
1909 
1910 struct em_host_command_header {
1911  uint8_t command_id;
1912  uint8_t command_length;
1913  uint8_t command_options; /* I/F bits for command, status for return */
1914  uint8_t checksum;
1915 };
1916 struct em_host_command_info {
1917  struct em_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
1918  uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
1919 };
1920 
1921 /* Host SMB register #0 */
1922 #define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
1923 #define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
1924 #define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
1925 #define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
1926 
1927 /* Host SMB register #1 */
1928 #define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
1929 #define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
1930 #define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
1931 #define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
1932 
1933 /* FW Status Register */
1934 #define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
1935 
1936 /* Wake Up Packet Length */
1937 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1938 
1939 #define E1000_MDALIGN 4096
1940 
1941 #define E1000_GCR_BEM32 0x00400000
1942 /* Function Active and Power State to MNG */
1943 #define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
1944 #define E1000_FACTPS_LAN0_VALID 0x00000004
1945 #define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
1946 #define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
1947 #define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
1948 #define E1000_FACTPS_LAN1_VALID 0x00000100
1949 #define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
1950 #define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
1951 #define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
1952 #define E1000_FACTPS_IDE_ENABLE 0x00004000
1953 #define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
1954 #define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
1955 #define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
1956 #define E1000_FACTPS_SP_ENABLE 0x00100000
1957 #define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
1958 #define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
1959 #define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
1960 #define E1000_FACTPS_IPMI_ENABLE 0x04000000
1961 #define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
1962 #define E1000_FACTPS_MNGCG 0x20000000
1963 #define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
1964 #define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
1965 
1966 /* EEPROM Commands - Microwire */
1967 #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
1968 #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
1969 #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
1970 #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
1971 #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
1972 
1973 /* EEPROM Commands - SPI */
1974 #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1975 #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1976 #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1977 #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1978 #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
1979 #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
1980 #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
1981 #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
1982 #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1983 #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1984 #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1985 
1986 /* EEPROM Size definitions */
1987 #define EEPROM_WORD_SIZE_SHIFT 6
1988 #define EEPROM_SIZE_SHIFT 10
1989 #define EEPROM_SIZE_MASK 0x1C00
1990 
1991 /* EEPROM Word Offsets */
1992 #define EEPROM_COMPAT 0x0003
1993 #define EEPROM_ID_LED_SETTINGS 0x0004
1994 #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
1995 #define EEPROM_PHY_CLASS_WORD 0x0007
1996 #define EEPROM_INIT_CONTROL1_REG 0x000A
1997 #define EEPROM_INIT_CONTROL2_REG 0x000F
1998 #define EEPROM_INIT_CONTROL3_PORT_B 0x0014
1999 #define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2000 #define EEPROM_CFG 0x0012
2001 #define EEPROM_FLASH_VERSION 0x0032
2002 #define EEPROM_CHECKSUM_REG 0x003F
2003 
2004 /* Word definitions for ID LED Settings */
2005 #define ID_LED_RESERVED_0000 0x0000
2006 #define ID_LED_RESERVED_FFFF 0xFFFF
2007 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2008  (ID_LED_OFF1_OFF2 << 8) | \
2009  (ID_LED_DEF1_DEF2 << 4) | \
2010  (ID_LED_DEF1_DEF2))
2011 #define ID_LED_DEF1_DEF2 0x1
2012 #define ID_LED_DEF1_ON2 0x2
2013 #define ID_LED_DEF1_OFF2 0x3
2014 #define ID_LED_ON1_DEF2 0x4
2015 #define ID_LED_ON1_ON2 0x5
2016 #define ID_LED_ON1_OFF2 0x6
2017 #define ID_LED_OFF1_DEF2 0x7
2018 #define ID_LED_OFF1_ON2 0x8
2019 #define ID_LED_OFF1_OFF2 0x9
2020 
2021 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2022 #define IGP_ACTIVITY_LED_ENABLE 0x0300
2023 #define IGP_LED3_MODE 0x07000000
2024 
2025 
2026 /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2027 #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2028 
2029 /* Mask bit for PHY class in Word 7 of the EEPROM */
2030 #define EEPROM_PHY_CLASS_A 0x8000
2031 
2032 /* Mask bits for fields in Word 0x0a of the EEPROM */
2033 #define EEPROM_WORD0A_ILOS 0x0010
2034 #define EEPROM_WORD0A_SWDPIO 0x01E0
2035 #define EEPROM_WORD0A_LRST 0x0200
2036 #define EEPROM_WORD0A_FD 0x0400
2037 #define EEPROM_WORD0A_66MHZ 0x0800
2038 
2039 /* Mask bits for fields in Word 0x0f of the EEPROM */
2040 #define EEPROM_WORD0F_PAUSE_MASK 0x3000
2041 #define EEPROM_WORD0F_PAUSE 0x1000
2042 #define EEPROM_WORD0F_ASM_DIR 0x2000
2043 #define EEPROM_WORD0F_ANE 0x0800
2044 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2045 
2046 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
2047 #define EEPROM_SUM 0xBABA
2048 
2049 /* EEPROM Map defines (WORD OFFSETS)*/
2050 #define EEPROM_NODE_ADDRESS_BYTE_0 0
2051 #define EEPROM_PBA_BYTE_1 8
2052 
2053 #define EEPROM_RESERVED_WORD 0xFFFF
2054 
2055 /* EEPROM Map Sizes (Byte Counts) */
2056 #define PBA_SIZE 4
2057 
2058 /* Collision related configuration parameters */
2059 #define E1000_COLLISION_THRESHOLD 15
2060 #define E1000_CT_SHIFT 4
2061 #define E1000_COLLISION_DISTANCE 64
2062 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2063 #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2064 #define E1000_COLD_SHIFT 12
2065 
2066 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2067 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
2068 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
2069 
2070 /* Default values for the transmit IPG register */
2071 #define DEFAULT_82542_TIPG_IPGT 10
2072 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
2073 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
2074 
2075 #define E1000_TIPG_IPGT_MASK 0x000003FF
2076 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
2077 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
2078 
2079 #define DEFAULT_82542_TIPG_IPGR1 2
2080 #define DEFAULT_82543_TIPG_IPGR1 8
2081 #define E1000_TIPG_IPGR1_SHIFT 10
2082 
2083 #define DEFAULT_82542_TIPG_IPGR2 10
2084 #define DEFAULT_82543_TIPG_IPGR2 6
2085 #define E1000_TIPG_IPGR2_SHIFT 20
2086 
2087 #define E1000_TXDMAC_DPP 0x00000001
2088 
2089 /* Adaptive IFS defines */
2090 #define TX_THRESHOLD_START 8
2091 #define TX_THRESHOLD_INCREMENT 10
2092 #define TX_THRESHOLD_DECREMENT 1
2093 #define TX_THRESHOLD_STOP 190
2094 #define TX_THRESHOLD_DISABLE 0
2095 #define TX_THRESHOLD_TIMER_MS 10000
2096 #define MIN_NUM_XMITS 1000
2097 #define IFS_MAX 80
2098 #define IFS_STEP 10
2099 #define IFS_MIN 40
2100 #define IFS_RATIO 4
2101 
2102 /* Extended Configuration Control and Size */
2103 #define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2104 #define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2105 #define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2106 #define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2107 #define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2108 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2109 #define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2110 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000
2111 
2112 #define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2113 #define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2114 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2115 
2116 /* PBA constants */
2117 #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2118 #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2119 #define E1000_PBA_22K 0x0016
2120 #define E1000_PBA_24K 0x0018
2121 #define E1000_PBA_30K 0x001E
2122 #define E1000_PBA_40K 0x0028
2123 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2124 
2125 /* Flow Control Constants */
2126 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2127 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2128 #define FLOW_CONTROL_TYPE 0x8808
2129 
2130 /* The historical defaults for the flow control values are given below. */
2131 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2132 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2133 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2134 
2135 /* PCIX Config space */
2136 #define PCIX_COMMAND_REGISTER 0xE6
2137 #define PCIX_STATUS_REGISTER_LO 0xE8
2138 #define PCIX_STATUS_REGISTER_HI 0xEA
2139 
2140 #define PCIX_COMMAND_MMRBC_MASK 0x000C
2141 #define PCIX_COMMAND_MMRBC_SHIFT 0x2
2142 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
2143 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
2144 #define PCIX_STATUS_HI_MMRBC_4K 0x3
2145 #define PCIX_STATUS_HI_MMRBC_2K 0x2
2146 
2147 
2148 /* Number of bits required to shift right the "pause" bits from the
2149  * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2150  */
2151 #define PAUSE_SHIFT 5
2152 
2153 /* Number of bits required to shift left the "SWDPIO" bits from the
2154  * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
2155  */
2156 #define SWDPIO_SHIFT 17
2157 
2158 /* Number of bits required to shift left the "SWDPIO_EXT" bits from the
2159  * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
2160  */
2161 #define SWDPIO__EXT_SHIFT 4
2162 
2163 /* Number of bits required to shift left the "ILOS" bit from the EEPROM
2164  * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
2165  */
2166 #define ILOS_SHIFT 3
2167 
2168 
2169 #define RECEIVE_BUFFER_ALIGN_SIZE (256)
2170 
2171 /* Number of milliseconds we wait for auto-negotiation to complete */
2172 #define LINK_UP_TIMEOUT 500
2173 
2174 /* Number of 100 microseconds we wait for PCI Express master disable */
2175 #define MASTER_DISABLE_TIMEOUT 800
2176 /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2177 #define AUTO_READ_DONE_TIMEOUT 10
2178 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
2179 #define PHY_CFG_TIMEOUT 40
2180 
2181 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
2182 
2183 /* The carrier extension symbol, as received by the NIC. */
2184 #define CARRIER_EXTENSION 0x0F
2185 
2186 /* TBI_ACCEPT macro definition:
2187  *
2188  * This macro requires:
2189  * adapter = a pointer to struct em_hw
2190  * status = the 8 bit status field of the RX descriptor with EOP set
2191  * error = the 8 bit error field of the RX descriptor with EOP set
2192  * length = the sum of all the length fields of the RX descriptors that
2193  * make up the current frame
2194  * last_byte = the last byte of the frame DMAed by the hardware
2195  * max_frame_length = the maximum frame length we want to accept.
2196  * min_frame_length = the minimum frame length we want to accept.
2197  *
2198  * This macro is a conditional that should be used in the interrupt
2199  * handler's Rx processing routine when RxErrors have been detected.
2200  *
2201  * Typical use:
2202  * ...
2203  * if (TBI_ACCEPT) {
2204  * accept_frame = TRUE;
2205  * em_tbi_adjust_stats(adapter, MacAddress);
2206  * frame_length--;
2207  * } else {
2208  * accept_frame = FALSE;
2209  * }
2210  * ...
2211  */
2212 
2213 #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2214  ((adapter)->tbi_compatibility_on && \
2215  (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2216  ((last_byte) == CARRIER_EXTENSION) && \
2217  (((status) & E1000_RXD_STAT_VP) ? \
2218  (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2219  ((length) <= ((adapter)->max_frame_size + 1))) : \
2220  (((length) > (adapter)->min_frame_size) && \
2221  ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2222 
2223 
2224 /* Structures, enums, and macros for the PHY */
2225 
2226 /* Bit definitions for the Management Data IO (MDIO) and Management Data
2227  * Clock (MDC) pins in the Device Control Register.
2228  */
2229 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
2230 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
2231 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
2232 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
2233 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
2234 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
2235 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2236 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
2237 
2238 /* PHY 1000 MII Register/Bit Definitions */
2239 /* PHY Registers defined by IEEE */
2240 #define PHY_CTRL 0x00 /* Control Register */
2241 #define PHY_STATUS 0x01 /* Status Regiser */
2242 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2243 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2244 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2245 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2246 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2247 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2248 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2249 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2250 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2251 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2252 
2253 /* M88E1000 Specific Registers */
2254 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2255 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2256 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2257 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2258 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2259 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2260 
2261 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2262 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2263 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2264 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2265 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2266 
2267 #define IGP01E1000_IEEE_REGS_PAGE 0x0000
2268 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2269 #define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2270 
2271 /* IGP01E1000 Specific Registers */
2272 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2273 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2274 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2275 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2276 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2277 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2278 #define IGP02E1000_PHY_POWER_MGMT 0x19
2279 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2280 
2281 /* IGP01E1000 AGC Registers - stores the cable length values*/
2282 #define IGP01E1000_PHY_AGC_A 0x1172
2283 #define IGP01E1000_PHY_AGC_B 0x1272
2284 #define IGP01E1000_PHY_AGC_C 0x1472
2285 #define IGP01E1000_PHY_AGC_D 0x1872
2286 
2287 /* IGP02E1000 AGC Registers for cable length values */
2288 #define IGP02E1000_PHY_AGC_A 0x11B1
2289 #define IGP02E1000_PHY_AGC_B 0x12B1
2290 #define IGP02E1000_PHY_AGC_C 0x14B1
2291 #define IGP02E1000_PHY_AGC_D 0x18B1
2292 
2293 /* IGP01E1000 DSP Reset Register */
2294 #define IGP01E1000_PHY_DSP_RESET 0x1F33
2295 #define IGP01E1000_PHY_DSP_SET 0x1F71
2296 #define IGP01E1000_PHY_DSP_FFE 0x1F35
2297 
2298 #define IGP01E1000_PHY_CHANNEL_NUM 4
2299 #define IGP02E1000_PHY_CHANNEL_NUM 4
2300 
2301 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171
2302 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271
2303 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471
2304 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871
2305 
2306 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
2307 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2308 
2309 #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
2310 #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
2311 #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
2312 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
2313 
2314 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2315 /* IGP01E1000 PCS Initialization register - stores the polarity status when
2316  * speed = 1000 Mbps. */
2317 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2318 #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2319 
2320 #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2321 
2322 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2323 #define MAX_PHY_MULTI_PAGE_REG 0xF /*Registers that are equal on all pages*/
2324 /* PHY Control Register */
2325 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2326 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2327 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2328 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2329 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2330 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
2331 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2332 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2333 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2334 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2335 
2336 /* PHY Status Register */
2337 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2338 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2339 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2340 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2341 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2342 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2343 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2344 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2345 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2346 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2347 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2348 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2349 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2350 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2351 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2352 
2353 /* Autoneg Advertisement Register */
2354 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2355 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2356 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2357 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2358 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2359 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2360 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2361 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2362 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2363 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2364 
2365 /* Link Partner Ability Register (Base Page) */
2366 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2367 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2368 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2369 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2370 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2371 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2372 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2373 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2374 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2375 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2376 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2377 
2378 /* Autoneg Expansion Register */
2379 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2380 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2381 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2382 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2383 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2384 
2385 /* Next Page TX Register */
2386 #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2387 #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2388  * of different NP
2389  */
2390 #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2391  * 0 = cannot comply with msg
2392  */
2393 #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2394 #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2395  * 0 = sending last NP
2396  */
2397 
2398 /* Link Partner Next Page Register */
2399 #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2400 #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2401  * of different NP
2402  */
2403 #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2404  * 0 = cannot comply with msg
2405  */
2406 #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2407 #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2408 #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2409  * 0 = sending last NP
2410  */
2411 
2412 /* 1000BASE-T Control Register */
2413 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2414 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2415 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2416 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2417  /* 0=DTE device */
2418 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2419  /* 0=Configure PHY as Slave */
2420 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2421  /* 0=Automatic Master/Slave config */
2422 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2423 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2424 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2425 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2426 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2427 
2428 /* 1000BASE-T Status Register */
2429 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2430 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2431 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2432 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2433 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2434 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2435 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2436 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2437 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2438 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2439 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
2440 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
2441 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2442 
2443 /* Extended Status Register */
2444 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2445 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2446 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2447 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2448 
2449 #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2450 #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2451 
2452 #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2453  /* (0=enable, 1=disable) */
2454 
2455 /* M88E1000 PHY Specific Control Register */
2456 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2457 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2458 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2459 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2460  * 0=CLK125 toggling
2461  */
2462 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2463  /* Manual MDI configuration */
2464 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2465 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2466  * 100BASE-TX/10BASE-T:
2467  * MDI Mode
2468  */
2469 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2470  * all speeds.
2471  */
2472 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2473  /* 1=Enable Extended 10BASE-T distance
2474  * (Lower 10BASE-T RX Threshold)
2475  * 0=Normal 10BASE-T RX Threshold */
2476 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2477  /* 1=5-Bit interface in 100BASE-TX
2478  * 0=MII interface in 100BASE-TX */
2479 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2480 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2481 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2482 
2483 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2484 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2485 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2486 
2487 /* M88E1000 PHY Specific Status Register */
2488 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2489 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2490 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2491 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2492 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2493  * 3=110-140M;4=>140M */
2494 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2495 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2496 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2497 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2498 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2499 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2500 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2501 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2502 
2503 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2504 #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
2505 #define M88E1000_PSSR_MDIX_SHIFT 6
2506 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2507 
2508 /* M88E1000 Extended PHY Specific Control Register */
2509 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2510 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2511  * Will assert lost lock and bring
2512  * link down if idle not seen
2513  * within 1ms in 1000BASE-T
2514  */
2515 /* Number of times we will attempt to autonegotiate before downshifting if we
2516  * are the master */
2517 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2518 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2519 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2520 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2521 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2522 /* Number of times we will attempt to autonegotiate before downshifting if we
2523  * are the slave */
2524 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2525 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2526 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2527 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2528 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2529 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2530 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2531 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2532 
2533 /* IGP01E1000 Specific Port Config Register - R/W */
2534 #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2535 #define IGP01E1000_PSCFR_PRE_EN 0x0020
2536 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2537 #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2538 #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2539 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2540 
2541 /* IGP01E1000 Specific Port Status Register - R/O */
2542 #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2543 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2544 #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2545 #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2546 #define IGP01E1000_PSSR_LINK_UP 0x0400
2547 #define IGP01E1000_PSSR_MDIX 0x0800
2548 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2549 #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2550 #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2551 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2552 #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2553 #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2554 
2555 /* IGP01E1000 Specific Port Control Register - R/W */
2556 #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2557 #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2558 #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2559 #define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2560 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2561 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2562 
2563 /* IGP01E1000 Specific Port Link Health Register */
2564 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2565 #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2566 #define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2567 #define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2568 #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2569 #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2570 #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2571 #define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2572 #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2573 #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2574 #define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2575 #define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2576 #define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2577 #define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2578 
2579 /* IGP01E1000 Channel Quality Register */
2580 #define IGP01E1000_MSE_CHANNEL_D 0x000F
2581 #define IGP01E1000_MSE_CHANNEL_C 0x00F0
2582 #define IGP01E1000_MSE_CHANNEL_B 0x0F00
2583 #define IGP01E1000_MSE_CHANNEL_A 0xF000
2584 
2585 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2586 #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2587 #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2588 
2589 /* IGP01E1000 DSP reset macros */
2590 #define DSP_RESET_ENABLE 0x0
2591 #define DSP_RESET_DISABLE 0x2
2592 #define E1000_MAX_DSP_RESETS 10
2593 
2594 /* IGP01E1000 & IGP02E1000 AGC Registers */
2595 
2596 #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2597 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2598 
2599 /* IGP02E1000 AGC Register Length 9-bit mask */
2600 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
2601 
2602 /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2603 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
2604 #define IGP02E1000_AGC_LENGTH_TABLE_SIZE 128
2605 
2606 /* The precision error of the cable length is +/- 10 meters */
2607 #define IGP01E1000_AGC_RANGE 10
2608 #define IGP02E1000_AGC_RANGE 10
2609 
2610 /* IGP01E1000 PCS Initialization register */
2611 /* bits 3:6 in the PCS registers stores the channels polarity */
2612 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
2613 
2614 /* IGP01E1000 GMII FIFO Register */
2615 #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2616  * on Link-Up */
2617 #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2618 
2619 /* IGP01E1000 Analog Register */
2620 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2621 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2622 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2623 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2624 
2625 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2626 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2627 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2628 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2629 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2630 
2631 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2632 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2633 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2634 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2635 
2636 
2637 /* Bit definitions for valid PHY IDs. */
2638 /* I = Integrated
2639  * E = External
2640  */
2641 #define M88E1000_E_PHY_ID 0x01410C50
2642 #define M88E1000_I_PHY_ID 0x01410C30
2643 #define M88E1011_I_PHY_ID 0x01410C20
2644 #define IGP01E1000_I_PHY_ID 0x02A80380
2645 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2646 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2647 #define M88E1011_I_REV_4 0x04
2648 #define M88E1111_I_PHY_ID 0x01410CC0
2649 #define L1LXT971A_PHY_ID 0x001378E0
2650 
2651 /* Miscellaneous PHY bit definitions. */
2652 #define PHY_PREAMBLE 0xFFFFFFFF
2653 #define PHY_SOF 0x01
2654 #define PHY_OP_READ 0x02
2655 #define PHY_OP_WRITE 0x01
2656 #define PHY_TURNAROUND 0x02
2657 #define PHY_PREAMBLE_SIZE 32
2658 #define MII_CR_SPEED_1000 0x0040
2659 #define MII_CR_SPEED_100 0x2000
2660 #define MII_CR_SPEED_10 0x0000
2661 #define E1000_PHY_ADDRESS 0x01
2662 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
2663 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */
2664 #define PHY_REVISION_MASK 0xFFFFFFF0
2665 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
2666 #define REG4_SPEED_MASK 0x01E0
2667 #define REG9_SPEED_MASK 0x0300
2668 #define ADVERTISE_10_HALF 0x0001
2669 #define ADVERTISE_10_FULL 0x0002
2670 #define ADVERTISE_100_HALF 0x0004
2671 #define ADVERTISE_100_FULL 0x0008
2672 #define ADVERTISE_1000_HALF 0x0010
2673 #define ADVERTISE_1000_FULL 0x0020
2674 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
2675 #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
2676 #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
2677 
2678 #endif /* _EM_HW_H_ */
read
ssize_t read(int fd, void *buffer, size_t count)
Definition: read.c:27
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Definition: if_em_hw.h:1910
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Definition: if_em_hw.h:613
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Definition: if_em_hw.h:1916
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Definition: if_em_hw.h:739
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Definition: if_em_hw.h:795
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Definition: if_em_hw.h:371
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Definition: if_em_hw.h:820
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Definition: if_em_hw.h:347
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Definition: if_em_hw.h:826
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Definition: nislib.h:49
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Definition: if_em_hw.h:250
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Definition: if_em_hw.h:1212
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Definition: if_em_hw.h:355
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Definition: if_em_hw.h:815
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Definition: if_em_hw.h:832
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Definition: if_em_hw.h:1283
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Definition: if_em_hw.h:804
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Definition: if_em_hw.h:239
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Definition: 8xx_immap.h:312
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Definition: if_em_hw.h:255
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Definition: if_em_hw.h:768
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Definition: if_em_hw.h:696
em_rx_desc
Definition: if_em_hw.h:577
em_rx_desc_extended
Definition: if_em_hw.h:587
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