RTEMS  5.0.0
gtethreg.h
1 /* $NetBSD: gtethreg.h,v 1.2.10.1 2005/04/29 11:28:55 kent Exp $ */
2 
3 /*
4  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  * must display the following acknowledgement:
17  * This product includes software developed for the NetBSD Project by
18  * Allegro Networks, Inc., and Wasabi Systems, Inc.
19  * 4. The name of Allegro Networks, Inc. may not be used to endorse
20  * or promote products derived from this software without specific prior
21  * written permission.
22  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
23  * or promote products derived from this software without specific prior
24  * written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
27  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
28  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
29  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGE.
38  */
39 
40 #ifndef _DEV_GTETHREG_H_
41 #define _DEV_GTETHREG_H_
42 
43 #define ETH__BIT(bit) (1U << (bit))
44 #define ETH__LLBIT(bit) (1LLU << (bit))
45 #define ETH__MASK(bit) (ETH__BIT(bit) - 1)
46 #define ETH__LLMASK(bit) (ETH__LLBIT(bit) - 1)
47 #define ETH__GEN(n, off) (0x2400+((n) << 10)+(ETH__ ## off))
48 #define ETH__EXT(data, bit, len) (((data) >> (bit)) & ETH__MASK(len))
49 #define ETH__LLEXT(data, bit, len) (((data) >> (bit)) & ETH__LLMASK(len))
50 #define ETH__CLR(data, bit, len) ((data) &= ~(ETH__MASK(len) << (bit)))
51 #define ETH__INS(new, bit) ((new) << (bit))
52 #define ETH__LLINS(new, bit) ((uint64_t)(new) << (bit))
53 
54 /*
55  * Descriptors used for both receive & transmit data. Note that the descriptor
56  * must start on a 4LW boundary. Since the GT accesses the descriptor as
57  * two 64-bit quantities, we must present them 32bit quantities in the right
58  * order based on endianess.
59  */
60 
61 struct gt_eth_desc {
62 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
63  u_int32_t ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */
64  u_int32_t ed_cmdsts; /* command (hi16)/status (lo16) bits */
65  u_int32_t ed_nxtptr; /* next descriptor (must be 4LW aligned) */
66  u_int32_t ed_bufptr; /* pointer to packet buffer */
67 #endif
68 #if defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN
69  u_int32_t ed_cmdsts; /* command (hi16)/status (lo16) bits */
70  u_int32_t ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */
71  u_int32_t ed_bufptr; /* pointer to packet buffer */
72  u_int32_t ed_nxtptr; /* next descriptor (must be 4LW aligned) */
73 #endif
74 };
75 
76 /* Table 578: Ethernet TX Descriptor - Command/Status word
77  * All bits except F, EI, AM, O are only valid if TX_CMD_L is also set,
78  * otherwise should be 0 (tx).
79  */
80 #define TX_STS_LC ETH__BIT(5) /* Late Collision */
81 #define TX_STS_UR ETH__BIT(6) /* Underrun error */
82 #define TX_STS_RL ETH__BIT(8) /* Retransmit Limit (excession coll) */
83 #define TX_STS_COL ETH__BIT(9) /* Collision Occurred */
84 #define TX_STS_RC(v) ETH__GETBITS(v, 10, 4) /* Retransmit Count */
85 #define TX_STS_ES ETH__BIT(15) /* Error Summary (LC|UR|RL) */
86 #define TX_CMD_L ETH__BIT(16) /* Last - End Of Packet */
87 #define TX_CMD_F ETH__BIT(17) /* First - Start Of Packet */
88 #define TX_CMD_P ETH__BIT(18) /* Pad Packet */
89 #define TX_CMD_GC ETH__BIT(22) /* Generate CRC */
90 #define TX_CMD_EI ETH__BIT(23) /* Enable Interrupt */
91 #define TX_CMD_AM ETH__BIT(30) /* Auto Mode */
92 #define TX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */
93 
94 #define TX_CMD_FIRST (TX_CMD_F|TX_CMD_O)
95 #define TX_CMD_LAST (TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O)
96 
97 /* Table 582: Ethernet RX Descriptor - Command/Status Word
98  * All bits except F, EI, AM, O are only valid if RX_CMD_L is also set,
99  * otherwise should be ignored (rx).
100  */
101 #define RX_STS_CE ETH__BIT(0) /* CRC Error */
102 #define RX_STS_COL ETH__BIT(1) /* Collision sensed during reception */
103 #define RX_STS_LC ETH__BIT(5) /* Late Collision (Reserved) */
104 #define RX_STS_OR ETH__BIT(6) /* Overrun Error */
105 #define RX_STS_MFL ETH__BIT(7) /* Max Frame Len Error */
106 #define RX_STS_SF ETH__BIT(8) /* Short Frame Error (< 64 bytes) */
107 #define RX_STS_FT ETH__BIT(11) /* Frame Type (1 = 802.3) */
108 #define RX_STS_M ETH__BIT(12) /* Missed Frame */
109 #define RX_STS_HE ETH__BIT(13) /* Hash Expired (manual match) */
110 #define RX_STS_IGMP ETH__BIT(14) /* IGMP Packet */
111 #define RX_STS_ES ETH__BIT(15) /* Error Summary (CE|COL|LC|OR|MFL|SF) */
112 #define RX_CMD_L ETH__BIT(16) /* Last - End Of Packet */
113 #define RX_CMD_F ETH__BIT(17) /* First - Start Of Packet */
114 #define RX_CMD_EI ETH__BIT(23) /* Enable Interrupt */
115 #define RX_CMD_AM ETH__BIT(30) /* Auto Mode */
116 #define RX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */
117 
118 /* Table 586: Hash Table Entry Fields
119  */
120 #define HSH_V ETH__LLBIT(0) /* Entry is valid */
121 #define HSH_S ETH__LLBIT(1) /* Skip this entry */
122 #define HSH_RD ETH__LLBIT(2) /* Receive(1) / Discard (0) */
123 #define HSH_R ETH__LLBIT(2) /* Receive(1) */
124 #define HSH_PRIO_GET(v) ETH__LLEXT(v, 51, 2)
125 #define HSH_PRIO_INS(v) ETH__LLINS(v, 51)
126 #define HSH_ADDR_MASK 0x7fffff8LLU
127 #define HSH_LIMIT 12
128 
129 
130 #define ETH_EPAR 0x2000 /* PHY Address Register */
131 #define ETH_ESMIR 0x2010 /* SMI Register */
132 
133 #define ETH_BASE_ETH0 0x2400 /* Ethernet0 Register Base */
134 #define ETH_BASE_ETH1 0x2800 /* Ethernet1 Register Base */
135 #define ETH_BASE_ETH2 0x2c00 /* Ethernet2 Register Base */
136 #define ETH_SIZE 0x0400 /* Register Space */
137 
138 #define ETH__EBASE 0x0000 /* Base of Registers */
139 #define ETH__EPCR 0x0000 /* Port Config. Register */
140 #define ETH__EPCXR 0x0008 /* Port Config. Extend Reg */
141 #define ETH__EPCMR 0x0010 /* Port Command Register */
142 #define ETH__EPSR 0x0018 /* Port Status Register */
143 #define ETH__ESPR 0x0020 /* Port Serial Parameters Reg */
144 #define ETH__EHTPR 0x0028 /* Port Hash Table Pointer Reg*/
145 #define ETH__EFCSAL 0x0030 /* Flow Control Src Addr Low */
146 #define ETH__EFCSAH 0x0038 /* Flow Control Src Addr High */
147 #define ETH__ESDCR 0x0040 /* SDMA Configuration Reg */
148 #define ETH__ESDCMR 0x0048 /* SDMA Command Register */
149 #define ETH__EICR 0x0050 /* Interrupt Cause Register */
150 #define ETH__EIMR 0x0058 /* Interrupt Mask Register */
151 #define ETH__EFRDP0 0x0080 /* First Rx Desc Pointer 0 */
152 #define ETH__EFRDP1 0x0084 /* First Rx Desc Pointer 1 */
153 #define ETH__EFRDP2 0x0088 /* First Rx Desc Pointer 2 */
154 #define ETH__EFRDP3 0x008c /* First Rx Desc Pointer 3 */
155 #define ETH__ECRDP0 0x00a0 /* Current Rx Desc Pointer 0 */
156 #define ETH__ECRDP1 0x00a4 /* Current Rx Desc Pointer 1 */
157 #define ETH__ECRDP2 0x00a8 /* Current Rx Desc Pointer 2 */
158 #define ETH__ECRDP3 0x00ac /* Current Rx Desc Pointer 3 */
159 #define ETH__ECTDP0 0x00e0 /* Current Tx Desc Pointer 0 */
160 #define ETH__ECTDP1 0x00e4 /* Current Tx Desc Pointer 1 */
161 #define ETH__EDSCP2P0L 0x0060 /* IP Differentiated Services
162  CodePoint to Priority0 low */
163 #define ETH__EDSCP2P0H 0x0064 /* IP Differentiated Services
164  CodePoint to Priority0 high*/
165 #define ETH__EDSCP2P1L 0x0068 /* IP Differentiated Services
166  CodePoint to Priority1 low */
167 #define ETH__EDSCP2P1H 0x006c /* IP Differentiated Services
168  CodePoint to Priority1 high*/
169 #define ETH__EVPT2P 0x0068 /* VLAN Prio. Tag to Priority */
170 #define ETH__EMIBCTRS 0x0100 /* MIB Counters */
171 
172 #define ETH_BASE(n) ETH__GEN(n, EBASE)
173 #define ETH_EPCR(n) ETH__GEN(n, EPCR) /* Port Config. Register */
174 #define ETH_EPCXR(n) ETH__GEN(n, EPCXR) /* Port Config. Extend Reg */
175 #define ETH_EPCMR(n) ETH__GEN(n, EPCMR) /* Port Command Register */
176 #define ETH_EPSR(n) ETH__GEN(n, EPSR) /* Port Status Register */
177 #define ETH_ESPR(n) ETH__GEN(n, ESPR) /* Port Serial Parameters Reg */
178 #define ETH_EHTPR(n) ETH__GEN(n, EHPTR) /* Port Hash Table Pointer Reg*/
179 #define ETH_EFCSAL(n) ETH__GEN(n, EFCSAL) /* Flow Control Src Addr Low */
180 #define ETH_EFCSAH(n) ETH__GEN(n, EFCSAH) /* Flow Control Src Addr High */
181 #define ETH_ESDCR(n) ETH__GEN(n, ESDCR) /* SDMA Configuration Reg */
182 #define ETH_ESDCMR(n) ETH__GEN(n, ESDCMR) /* SDMA Command Register */
183 #define ETH_EICR(n) ETH__GEN(n, EICR) /* Interrupt Cause Register */
184 #define ETH_EIMR(n) ETH__GEN(n, EIMR) /* Interrupt Mask Register */
185 #define ETH_EFRDP0(n) ETH__GEN(n, EFRDP0) /* First Rx Desc Pointer 0 */
186 #define ETH_EFRDP1(n) ETH__GEN(n, EFRDP1) /* First Rx Desc Pointer 1 */
187 #define ETH_EFRDP2(n) ETH__GEN(n, EFRDP2) /* First Rx Desc Pointer 2 */
188 #define ETH_EFRDP3(n) ETH__GEN(n, EFRDP3) /* First Rx Desc Pointer 3 */
189 #define ETH_ECRDP0(n) ETH__GEN(n, ECRDP0) /* Current Rx Desc Pointer 0 */
190 #define ETH_ECRDP1(n) ETH__GEN(n, ECRDP1) /* Current Rx Desc Pointer 1 */
191 #define ETH_ECRDP2(n) ETH__GEN(n, ECRDP2) /* Current Rx Desc Pointer 2 */
192 #define ETH_ECRDP3(n) ETH__GEN(n, ECRDP3) /* Current Rx Desc Pointer 3 */
193 #define ETH_ECTDP0(n) ETH__GEN(n, ECTDP0) /* Current Tx Desc Pointer 0 */
194 #define ETH_ECTDP1(n) ETH__GEN(n, ECTDP1) /* Current Tx Desc Pointer 1 */
195 #define ETH_EDSCP2P0L(n) ETH__GEN(n, EDSCP2P0L) /* IP Differentiated Services
196  CodePoint to Priority0 low */
197 #define ETH_EDSCP2P0H(n) ETH__GEN(n, EDSCP2P0H) /* IP Differentiated Services
198  CodePoint to Priority0 high*/
199 #define ETH_EDSCP2P1L(n) ETH__GEN(n, EDSCP2P1L) /* IP Differentiated Services
200  CodePoint to Priority1 low */
201 #define ETH_EDSCP2P1H(n) ETH__GEN(n, EDSCP1P1H) /* IP Differentiated Services
202  CodePoint to Priority1 high*/
203 #define ETH_EVPT2P(n) ETH__GEN(n, EVPT2P) /* VLAN Prio. Tag to Priority */
204 #define ETH_EMIBCTRS(n) ETH__GEN(n, EMIBCTRS) /* MIB Counters */
205 
206 #define ETH_EPAR_PhyAD_GET(v, n) (((v) >> ((n) * 5)) & 0x1f)
207 
208 #define ETH_ESMIR_READ(phy, reg) (ETH__INS(phy, 16)|\
209  ETH__INS(reg, 21)|\
210  ETH_ESMIR_ReadOpcode)
211 #define ETH_ESMIR_WRITE(phy, reg, val) (ETH__INS(phy, 16)|\
212  ETH__INS(reg, 21)|\
213  ETH__INS(val, 0)|\
214  ETH_ESMIR_WriteOpcode)
215 #define ETH_ESMIR_Value_GET(v) ETH__EXT(v, 0, 16)
216 #define ETH_ESMIR_WriteOpcode 0
217 #define ETH_ESMIR_ReadOpcode ETH__BIT(26)
218 #define ETH_ESMIR_ReadValid ETH__BIT(27)
219 #define ETH_ESMIR_Busy ETH__BIT(28)
220 
221 /*
222  * Table 597: Port Configuration Register (PCR)
223  * 00:00 PM Promiscuous mode
224  * 0: Normal mode (Frames are only received if the
225  * destination address is found in the hash
226  * table)
227  * 1: Promiscuous mode (Frames are received
228  * regardless of their destination address.
229  * Errored frames are discarded unless the Port
230  * Configuration register's PBF bit is set)
231  * 01:01 RBM Reject Broadcast Mode
232  * 0: Receive broadcast address
233  * 1: Reject frames with broadcast address
234  * Overridden by the promiscuous mode.
235  * 02:02 PBF Pass Bad Frames
236  * (0: Normal mode, 1: Pass bad Frames)
237  * The Ethernet receiver passes to the CPU errored
238  * frames (like fragments and collided packets)
239  * that are normally rejected.
240  * NOTE: Frames are only passed if they
241  * successfully pass address filtering.
242  * 06:03 Reserved
243  * 07:07 EN Enable (0: Disabled, 1: Enable)
244  * When enabled, the ethernet port is ready to
245  * transmit/receive.
246  * 09:08 LPBK Loop Back Mode
247  * 00: Normal mode
248  * 01: Internal loop back mode (TX data is looped
249  * back to the RX lines. No transition is seen
250  * on the interface pins)
251  * 10: External loop back mode (TX data is looped
252  * back to the RX lines and also transmitted
253  * out to the MII interface pins)
254  * 11: Reserved
255  * 10:10 FC Force Collision
256  * 0: Normal mode.
257  * 1: Force Collision on any TX frame.
258  * For RXM test (in Loopback mode).
259  * 11:11 Reserved.
260  * 12:12 HS Hash Size
261  * 0: 8K address filtering
262  * (256KB of memory space required).
263  * 1: 512 address filtering
264  * ( 16KB of memory space required).
265  * 13:13 HM Hash Mode (0: Hash Func. 0; 1: Hash Func. 1)
266  * 14:14 HDM Hash Default Mode
267  * 0: Discard addresses not found in address table
268  * 1: Pass addresses not found in address table
269  * 15:15 HD Duplex Mode (0: Half Duplex, 1: Full Duplex)
270  * NOTE: Valid only when auto-negotiation for
271  * duplex mode is disabled.
272  * 30:16 Reserved
273  * 31:31 ACCS Accelerate Slot Time
274  * (0: Normal mode, 1: Reserved)
275  */
276 #define ETH_EPCR_PM ETH__BIT(0)
277 #define ETH_EPCR_RBM ETH__BIT(1)
278 #define ETH_EPCR_PBF ETH__BIT(2)
279 #define ETH_EPCR_EN ETH__BIT(7)
280 #define ETH_EPCR_LPBK_GET(v) ETH__BIT(v, 8, 2)
281 #define ETH_EPCR_LPBK_Normal 0
282 #define ETH_EPCR_LPBK_Internal 1
283 #define ETH_EPCR_LPBK_External 2
284 #define ETH_EPCR_FC ETH__BIT(10)
285 
286 #define ETH_EPCR_HS ETH__BIT(12)
287 #define ETH_EPCR_HS_8K 0
288 #define ETH_EPCR_HS_512 ETH_EPCR_HS
289 
290 #define ETH_EPCR_HM ETH__BIT(13)
291 #define ETH_EPCR_HM_0 0
292 #define ETH_EPCR_HM_1 ETH_EPCR_HM
293 
294 #define ETH_EPCR_HDM ETH__BIT(14)
295 #define ETH_EPCR_HDM_Discard 0
296 #define ETH_EPCR_HDM_Pass ETH_EPCR_HDM
297 
298 #define ETH_EPCR_HD_Half 0
299 #define ETH_EPCR_HD_Full ETH_EPCR_HD_Full
300 
301 #define ETH_EPCR_ACCS ETH__BIT(31)
302 
303 
304 
305 /*
306  * Table 598: Port Configuration Extend Register (PCXR)
307  * 00:00 IGMP IGMP Packets Capture Enable
308  * 0: IGMP packets are treated as normal Multicast
309  * packets.
310  * 1: IGMP packets on IPv4/Ipv6 over Ethernet/802.3
311  * are trapped and sent to high priority RX
312  * queue.
313  * 01:01 SPAN Spanning Tree Packets Capture Enable
314  * 0: BPDU (Bridge Protocol Data Unit) packets are
315  * treated as normal Multicast packets.
316  * 1: BPDU packets are trapped and sent to high
317  * priority RX queue.
318  * 02:02 PAR Partition Enable (0: Normal, 1: Partition)
319  * When more than 61 collisions occur while
320  * transmitting, the port enters Partition mode.
321  * It waits for the first good packet from the
322  * wire and then goes back to Normal mode. Under
323  * Partition mode it continues transmitting, but
324  * it does not receive.
325  * 05:03 PRIOtx Priority weight in the round-robin between high
326  * and low priority TX queues.
327  * 000: 1 pkt from HIGH, 1 pkt from LOW.
328  * 001: 2 pkt from HIGH, 1 pkt from LOW.
329  * 010: 4 pkt from HIGH, 1 pkt from LOW.
330  * 011: 6 pkt from HIGH, 1 pkt from LOW.
331  * 100: 8 pkt from HIGH, 1 pkt from LOW.
332  * 101: 10 pkt from HIGH, 1 pkt from LOW.
333  * 110: 12 pkt from HIGH, 1 pkt from LOW.
334  * 111: All pkt from HIGH, 0 pkt from LOW. LOW is
335  * served only if HIGH is empty.
336  * NOTE: If the HIGH queue is emptied before
337  * finishing the count, the count is reset
338  * until the next first HIGH comes in.
339  * 07:06 PRIOrx Default Priority for Packets Received on this
340  * Port (00: Lowest priority, 11: Highest priority)
341  * 08:08 PRIOrx_Override Override Priority for Packets Received on this
342  * Port (0: Do not override, 1: Override with
343  * <PRIOrx> field)
344  * 09:09 DPLXen Enable Auto-negotiation for Duplex Mode
345  * (0: Enable, 1: Disable)
346  * 11:10 FCTLen Enable Auto-negotiation for 802.3x Flow-control
347  * 0: Enable; When enabled, 1 is written (through
348  * SMI access) to the PHY's register 4 bit 10
349  * to advertise flow-control capability.
350  * 1: Disable; Only enables flow control after the
351  * PHY address is set by the CPU. When changing
352  * the PHY address the flow control
353  * auto-negotiation must be disabled.
354  * 11:11 FLP Force Link Pass
355  * (0: Force Link Pass, 1: Do NOT Force Link pass)
356  * 12:12 FCTL 802.3x Flow-Control Mode (0: Enable, 1: Disable)
357  * NOTE: Only valid when auto negotiation for flow
358  * control is disabled.
359  * 13:13 Reserved
360  * 15:14 MFL Max Frame Length
361  * Maximum packet allowed for reception (including
362  * CRC): 00: 1518 bytes, 01: 1536 bytes,
363  * 10: 2048 bytes, 11: 64K bytes
364  * 16:16 MIBclrMode MIB Counters Clear Mode (0: Clear, 1: No effect)
365  * 17:17 MIBctrMode Reserved. (MBZ)
366  * 18:18 Speed Port Speed (0: 10Mbit/Sec, 1: 100Mbit/Sec)
367  * NOTE: Only valid if SpeedEn bit is set.
368  * 19:19 SpeedEn Enable Auto-negotiation for Speed
369  * (0: Enable, 1: Disable)
370  * 20:20 RMIIen RMII enable
371  * 0: Port functions as MII port
372  * 1: Port functions as RMII port
373  * 21:21 DSCPen DSCP enable
374  * 0: IP DSCP field decoding is disabled.
375  * 1: IP DSCP field decoding is enabled.
376  * 31:22 Reserved
377  */
378 #define ETH_EPCXR_IGMP ETH__BIT(0)
379 #define ETH_EPCXR_SPAN ETH__BIT(1)
380 #define ETH_EPCXR_PAR ETH__BIT(2)
381 #define ETH_EPCXR_PRIOtx_GET(v) ETH__EXT(v, 3, 3)
382 #define ETH_EPCXR_PRIOrx_GET(v) ETH__EXT(v, 3, 3)
383 #define ETH_EPCXR_PRIOrx_Override ETH__BIT(8)
384 #define ETH_EPCXR_DLPXen ETH__BIT(9)
385 #define ETH_EPCXR_FCTLen ETH__BIT(10)
386 #define ETH_EPCXR_FLP ETH__BIT(11)
387 #define ETH_EPCXR_FCTL ETH__BIT(12)
388 #define ETH_EPCXR_MFL_GET(v) ETH__EXT(v, 14, 2)
389 #define ETH_EPCXR_MFL_1518 0
390 #define ETH_EPCXR_MFL_1536 1
391 #define ETH_EPCXR_MFL_2084 2
392 #define ETH_EPCXR_MFL_64K 3
393 #define ETH_EPCXR_MIBclrMode ETH__BIT(16)
394 #define ETH_EPCXR_MIBctrMode ETH__BIT(17)
395 #define ETH_EPCXR_Speed ETH__BIT(18)
396 #define ETH_EPCXR_SpeedEn ETH__BIT(19)
397 #define ETH_EPCXR_RMIIEn ETH__BIT(20)
398 #define ETH_EPCXR_DSCPEn ETH__BIT(21)
399 
400 
401 
402 /*
403  * Table 599: Port Command Register (PCMR)
404  * 14:00 Reserved
405  * 15:15 FJ Force Jam / Flow Control
406  * When in half-duplex mode, the CPU uses this bit
407  * to force collisions on the Ethernet segment.
408  * When the CPU recognizes that it is going to run
409  * out of receive buffers, it can force the
410  * transmitter to send jam frames, forcing
411  * collisions on the wire. To allow transmission
412  * on the Ethernet segment, the CPU must clear the
413  * FJ bit when more resources are available. When
414  * in full-duplex and flow-control is enabled, this
415  * bit causes the port's transmitter to send
416  * flow-control PAUSE packets. The CPU must reset
417  * this bit when more resources are available.
418  * 31:16 Reserved
419  */
420 
421 #define ETH_EPCMR_FJ ETH__BIT(15)
422 
423 
424 /*
425  * Table 600: Port Status Register (PSR) -- Read Only
426  * 00:00 Speed Indicates Port Speed (0: 10Mbs, 1: 100Mbs)
427  * 01:01 Duplex Indicates Port Duplex Mode (0: Half, 1: Full)
428  * 02:02 Fctl Indicates Flow-control Mode
429  * (0: enabled, 1: disabled)
430  * 03:03 Link Indicates Link Status (0: down, 1: up)
431  * 04:04 Pause Indicates that the port is in flow-control
432  * disabled state. This bit is set when an IEEE
433  * 802.3x flow-control PAUSE (XOFF) packet is
434  * received (assuming that flow-control is
435  * enabled and the port is in full-duplex mode).
436  * Reset when XON is received, or when the XOFF
437  * timer has expired.
438  * 05:05 TxLow Tx Low Priority Status
439  * Indicates the status of the low priority
440  * transmit queue: (0: Stopped, 1: Running)
441  * 06:06 TxHigh Tx High Priority Status
442  * Indicates the status of the high priority
443  * transmit queue: (0: Stopped, 1: Running)
444  * 07:07 TXinProg TX in Progress
445  * Indicates that the port's transmitter is in an
446  * active transmission state.
447  * 31:08 Reserved
448  */
449 #define ETH_EPSR_Speed ETH__BIT(0)
450 #define ETH_EPSR_Duplex ETH__BIT(1)
451 #define ETH_EPSR_Fctl ETH__BIT(2)
452 #define ETH_EPSR_Link ETH__BIT(3)
453 #define ETH_EPSR_Pause ETH__BIT(4)
454 #define ETH_EPSR_TxLow ETH__BIT(5)
455 #define ETH_EPSR_TxHigh ETH__BIT(6)
456 #define ETH_EPSR_TXinProg ETH__BIT(7)
457 
458 
459 /*
460  * Table 601: Serial Parameters Register (SPR)
461  * 01:00 JAM_LENGTH Two bits to determine the JAM Length
462  * (in Backpressure) as follows:
463  * 00 = 12K bit-times
464  * 01 = 24K bit-times
465  * 10 = 32K bit-times
466  * 11 = 48K bit-times
467  * 06:02 JAM_IPG Five bits to determine the JAM IPG.
468  * The step is four bit-times. The value may vary
469  * between 4 bit time to 124.
470  * 11:07 IPG_JAM_TO_DATA Five bits to determine the IPG JAM to DATA.
471  * The step is four bit-times. The value may vary
472  * between 4 bit time to 124.
473  * 16:12 IPG_DATA Inter-Packet Gap (IPG)
474  * The step is four bit-times. The value may vary
475  * between 12 bit time to 124.
476  * NOTE: These bits may be changed only when the
477  * Ethernet ports is disabled.
478  * 21:17 Data_Blind Data Blinder
479  * The number of nibbles from the beginning of the
480  * IPG, in which the IPG counter is restarted when
481  * detecting a carrier activity. Following this
482  * value, the port enters the Data Blinder zone and
483  * does not reset the IPG counter. This ensures
484  * fair access to the medium.
485  * The default is 10 hex (64 bit times - 2/3 of the
486  * default IPG). The step is 4 bit-times. Valid
487  * range is 3 to 1F hex nibbles.
488  * NOTE: These bits may be only changed when the
489  * Ethernet port is disabled.
490  * 22:22 Limit4 The number of consecutive packet collisions that
491  * occur before the collision counter is reset.
492  * 0: The port resets its collision counter after
493  * 16 consecutive retransmit trials and
494  * restarts the Backoff algorithm.
495  * 1: The port resets its collision counter and
496  * restarts the Backoff algorithm after 4
497  * consecutive transmit trials.
498  * 31:23 Reserved
499  */
500 #define ETH_ESPR_JAM_LENGTH_GET(v) ETH__EXT(v, 0, 2)
501 #define ETH_ESPR_JAM_IPG_GET(v) ETH__EXT(v, 2, 5)
502 #define ETH_ESPR_IPG_JAM_TO_DATA_GET(v) ETH__EXT(v, 7, 5)
503 #define ETH_ESPR_IPG_DATA_GET(v) ETH__EXT(v, 12, 5)
504 #define ETH_ESPR_Data_Bilnd_GET(v) ETH__EXT(v, 17, 5)
505 #define ETH_ESPR_Limit4(v) ETH__BIT(22)
506 
507 /*
508  * Table 602: Hash Table Pointer Register (HTPR)
509  * 31:00 HTP 32-bit pointer to the address table.
510  * Bits [2:0] must be set to zero.
511  */
512 
513 /*
514  * Table 603: Flow Control Source Address Low (FCSAL)
515  * 15:0 SA[15:0] Source Address
516  * The least significant bits of the source
517  * address for the port. This address is used for
518  * Flow Control.
519  * 31:16 Reserved
520  */
521 
522 /*
523  * Table 604: Flow Control Source Address High (FCSAH)
524  * 31:0 SA[47:16] Source Address
525  * The most significant bits of the source address
526  * for the port. This address is used for Flow
527  * Control.
528  */
529 
530 
531 /*
532  * Table 605: SDMA Configuration Register (SDCR)
533  * 01:00 Reserved
534  * 05:02 RC Retransmit Count
535  * Sets the maximum number of retransmits per
536  * packet. After executing retransmit for RC
537  * times, the TX SDMA closes the descriptor with a
538  * Retransmit Limit error indication and processes
539  * the next packet. When RC is set to 0, the
540  * number of retransmits is unlimited. In this
541  * case, the retransmit process is only terminated
542  * if CPU issues an Abort command.
543  * 06:06 BLMR Big/Little Endian Receive Mode
544  * The DMA supports Big or Little Endian
545  * configurations on a per channel basis. The BLMR
546  * bit only affects data transfer to memory.
547  * 0: Big Endian
548  * 1: Little Endian
549  * 07:07 BLMT Big/Little Endian Transmit Mode
550  * The DMA supports Big or Little Endian
551  * configurations on a per channel basis. The BLMT
552  * bit only affects data transfer from memory.
553  * 0: Big Endian
554  * 1: Little Endian
555  * 08:08 POVR PCI Override
556  * When set, causes the SDMA to direct all its
557  * accesses in PCI_0 direction and overrides
558  * normal address decoding process.
559  * 09:09 RIFB Receive Interrupt on Frame Boundaries
560  * When set, the SDMA Rx generates interrupts only
561  * on frame boundaries (i.e. after writing the
562  * frame status to the descriptor).
563  * 11:10 Reserved
564  * 13:12 BSZ Burst Size
565  * Sets the maximum burst size for SDMA
566  * transactions:
567  * 00: Burst is limited to 1 64bit words.
568  * 01: Burst is limited to 2 64bit words.
569  * 10: Burst is limited to 4 64bit words.
570  * 11: Burst is limited to 8 64bit words.
571  * 31:14 Reserved
572  */
573 #define ETH_ESDCR_RC_GET(v) ETH__EXT(v, 2, 4)
574 #define ETH_ESDCR_BLMR ETH__BIT(6)
575 #define ETH_ESDCR_BLMT ETH__BIT(7)
576 #define ETH_ESDCR_POVR ETH__BIT(8)
577 #define ETH_ESDCR_RIFB ETH__BIT(9)
578 #define ETH_ESDCR_BSZ_GET(v) ETH__EXT(v, 12, 2)
579 #define ETH_ESDCR_BSZ_SET(v, n) (ETH__CLR(v, 12, 2),\
580  (v) |= ETH__INS(n, 12))
581 #define ETH_ESDCR_BSZ_1 0
582 #define ETH_ESDCR_BSZ_2 1
583 #define ETH_ESDCR_BSZ_4 2
584 #define ETH_ESDCR_BSZ_8 3
585 
586 #define ETH_ESDCR_BSZ_Strings { "1 64-bit word", "2 64-bit words", \
587  "4 64-bit words", "8 64-bit words" }
588 
589 /*
590  * Table 606: SDMA Command Register (SDCMR)
591  * 06:00 Reserved
592  * 07:07 ERD Enable RX DMA.
593  * Set to 1 by the CPU to cause the SDMA to start
594  * a receive process. Cleared when the CPU issues
595  * an Abort Receive command.
596  * 14:08 Reserved
597  * 15:15 AR Abort Receive
598  * Set to 1 by the CPU to abort a receive SDMA
599  * operation. When the AR bit is set, the SDMA
600  * aborts its current operation and moves to IDLE.
601  * No descriptor is closed. The AR bit is cleared
602  * upon entering IDLE. After setting the AR bit,
603  * the CPU must poll the bit to verify that the
604  * abort sequence is completed.
605  * 16:16 STDH Stop TX High
606  * Set to 1 by the CPU to stop the transmission
607  * process from the high priority queue at the end
608  * of the current frame. An interrupt is generated
609  * when the stop command has been executed.
610  * Writing 1 to STDH resets TXDH bit.
611  * Writing 0 to this bit has no effect.
612  * 17:17 STDL Stop TX Low
613  * Set to 1 by the CPU to stop the transmission
614  * process from the low priority queue at the end
615  * of the current frame. An interrupt is generated
616  * when the stop command has been executed.
617  * Writing 1 to STDL resets TXDL bit.
618  * Writing 0 to this bit has no effect.
619  * 22:18 Reserved
620  * 23:23 TXDH Start Tx High
621  * Set to 1 by the CPU to cause the SDMA to fetch
622  * the first descriptor and start a transmit
623  * process from the high priority Tx queue.
624  * Writing 1 to TXDH resets STDH bit.
625  * Writing 0 to this bit has no effect.
626  * 24:24 TXDL Start Tx Low
627  * Set to 1 by the CPU to cause the SDMA to fetch
628  * the first descriptor and start a transmit
629  * process from the low priority Tx queue.
630  * Writing 1 to TXDL resets STDL bit.
631  * Writing 0 to this bit has no effect.
632  * 30:25 Reserved
633  * 31:31 AT Abort Transmit
634  * Set to 1 by the CPU to abort a transmit DMA
635  * operation. When the AT bit is set, the SDMA
636  * aborts its current operation and moves to IDLE.
637  * No descriptor is closed. Cleared upon entering
638  * IDLE. After setting AT bit, the CPU must poll
639  * it in order to verify that the abort sequence
640  * is completed.
641  */
642 #define ETH_ESDCMR_ERD ETH__BIT(7)
643 #define ETH_ESDCMR_AR ETH__BIT(15)
644 #define ETH_ESDCMR_STDH ETH__BIT(16)
645 #define ETH_ESDCMR_STDL ETH__BIT(17)
646 #define ETH_ESDCMR_TXDH ETH__BIT(23)
647 #define ETH_ESDCMR_TXDL ETH__BIT(24)
648 #define ETH_ESDCMR_AT ETH__BIT(31)
649 
650 /*
651  * Table 607: Interrupt Cause Register (ICR)
652  * 00:00 RxBuffer Rx Buffer Return
653  * Indicates an Rx buffer returned to CPU ownership
654  * or that the port finished reception of a Rx
655  * frame in either priority queues.
656  * NOTE: In order to get a Rx Buffer return per
657  * priority queue, use bit 19:16. This bit is
658  * set upon closing any Rx descriptor which
659  * has its EI bit set. To limit the
660  * interrupts to frame (rather than buffer)
661  * boundaries, the user must set SDMA
662  * Configuration register's RIFB bit. When
663  * the RIFB bit is set, an interrupt
664  * generates only upon closing the first
665  * descriptor of a received packet, if this
666  * descriptor has it EI bit set.
667  * 01:01 Reserved
668  * 02:02 TxBufferHigh Tx Buffer for High priority Queue
669  * Indicates a Tx buffer returned to CPU ownership
670  * or that the port finished transmission of a Tx
671  * frame.
672  * NOTE: This bit is set upon closing any Tx
673  * descriptor which has its EI bit set. To
674  * limit the interrupts to frame (rather than
675  * buffer) boundaries, the user must set EI
676  * only in the last descriptor.
677  * 03:03 TxBufferLow Tx Buffer for Low Priority Queue
678  * Indicates a Tx buffer returned to CPU ownership
679  * or that the port finished transmission of a Tx
680  * frame.
681  * NOTE: This bit is set upon closing any Tx
682  * descriptor which has its EI bit set. To
683  * limit the interrupts to frame (rather than
684  * buffer) boundaries, the user must set EI
685  * only in the last descriptor.
686  * 05:04 Reserved
687  * 06:06 TxEndHigh Tx End for High Priority Queue
688  * Indicates that the Tx DMA stopped processing the
689  * high priority queue after stop command, or that
690  * it reached the end of the high priority
691  * descriptor chain.
692  * 07:07 TxEndLow Tx End for Low Priority Queue
693  * Indicates that the Tx DMA stopped processing the
694  * low priority queue after stop command, or that
695  * it reached the end of the low priority
696  * descriptor chain.
697  * 08:08 RxError Rx Resource Error
698  * Indicates a Rx resource error event in one of
699  * the priority queues.
700  * NOTE: To get a Rx Resource Error Indication per
701  * priority queue, use bit 23:20.
702  * 09:09 Reserved
703  * 10:10 TxErrorHigh Tx Resource Error for High Priority Queue
704  * Indicates a Tx resource error event during
705  * packet transmission from the high priority queue
706  * 11:11 TxErrorLow Tx Resource Error for Low Priority Queue
707  * Indicates a Tx resource error event during
708  * packet transmission from the low priority queue
709  * 12:12 RxOVR Rx Overrun
710  * Indicates an overrun event that occurred during
711  * reception of a packet.
712  * 13:13 TxUdr Tx Underrun
713  * Indicates an underrun event that occurred during
714  * transmission of packet from either queue.
715  * 15:14 Reserved
716  * 16:16 RxBuffer-Queue[0] Rx Buffer Return in Priority Queue[0]
717  * Indicates a Rx buffer returned to CPU ownership
718  * or that the port completed reception of a Rx
719  * frame in a receive priority queue[0]
720  * 17:17 RxBuffer-Queue[1] Rx Buffer Return in Priority Queue[1]
721  * Indicates a Rx buffer returned to CPU ownership
722  * or that the port completed reception of a Rx
723  * frame in a receive priority queue[1].
724  * 18:18 RxBuffer-Queue[2] Rx Buffer Return in Priority Queue[2]
725  * Indicates a Rx buffer returned to CPU ownership
726  * or that the port completed reception of a Rx
727  * frame in a receive priority queue[2].
728  * 19:19 RxBuffer-Queue[3] Rx Buffer Return in Priority Queue[3]
729  * Indicates a Rx buffer returned to CPU ownership
730  * or that the port completed reception of a Rx
731  * frame in a receive priority queue[3].
732  * 20:20 RxError-Queue[0] Rx Resource Error in Priority Queue[0]
733  * Indicates a Rx resource error event in receive
734  * priority queue[0].
735  * 21:21 RxError-Queue[1] Rx Resource Error in Priority Queue[1]
736  * Indicates a Rx resource error event in receive
737  * priority queue[1].
738  * 22:22 RxError-Queue[2] Rx Resource Error in Priority Queue[2]
739  * Indicates a Rx resource error event in receive
740  * priority queue[2].
741  * 23:23 RxError-Queue[3] Rx Resource Error in Priority Queue[3]
742  * Indicates a Rx resource error event in receive
743  * priority queue[3].
744  * 27:24 Reserved
745  * 28:29 MIIPhySTC MII PHY Status Change
746  * Indicates a status change reported by the PHY
747  * connected to this port. Set when the MII
748  * management interface block identifies a change
749  * in PHY's register 1.
750  * 29:29 SMIdone SMI Command Done
751  * Indicates that the SMI completed a MII
752  * management command (either read or write) that
753  * was initiated by the CPU writing to the SMI
754  * register.
755  * 30:30 Reserved
756  * 31:31 EtherIntSum Ethernet Interrupt Summary
757  * This bit is a logical OR of the (unmasked) bits
758  * [30:04] in the Interrupt Cause register.
759  */
760 
761 #define ETH_IR_RxBuffer ETH__BIT(0)
762 #define ETH_IR_TxBufferHigh ETH__BIT(2)
763 #define ETH_IR_TxBufferLow ETH__BIT(3)
764 #define ETH_IR_TxEndHigh ETH__BIT(6)
765 #define ETH_IR_TxEndLow ETH__BIT(7)
766 #define ETH_IR_RxError ETH__BIT(8)
767 #define ETH_IR_TxErrorHigh ETH__BIT(10)
768 #define ETH_IR_TxErrorLow ETH__BIT(11)
769 #define ETH_IR_RxOVR ETH__BIT(12)
770 #define ETH_IR_TxUdr ETH__BIT(13)
771 #define ETH_IR_RxBuffer_0 ETH__BIT(16)
772 #define ETH_IR_RxBuffer_1 ETH__BIT(17)
773 #define ETH_IR_RxBuffer_2 ETH__BIT(18)
774 #define ETH_IR_RxBuffer_3 ETH__BIT(19)
775 #define ETH_IR_RxBuffer_GET(v) ETH__EXT(v, 16, 4)
776 #define ETH_IR_RxError_0 ETH__BIT(20)
777 #define ETH_IR_RxError_1 ETH__BIT(21)
778 #define ETH_IR_RxError_2 ETH__BIT(22)
779 #define ETH_IR_RxError_3 ETH__BIT(23)
780 #define ETH_IR_RxError_GET(v) ETH__EXT(v, 20, 4)
781 #define ETH_IR_RxBits (ETH_IR_RxBuffer_0|\
782  ETH_IR_RxBuffer_1|\
783  ETH_IR_RxBuffer_2|\
784  ETH_IR_RxBuffer_3|\
785  ETH_IR_RxError_0|\
786  ETH_IR_RxError_1|\
787  ETH_IR_RxError_2|\
788  ETH_IR_RxError_3)
789 #define ETH_IR_MIIPhySTC ETH__BIT(28)
790 #define ETH_IR_SMIdone ETH__BIT(29)
791 #define ETH_IR_EtherIntSum ETH__BIT(31)
792 #define ETH_IR_Summary ETH__BIT(31)
793 
794 /*
795  * Table 608: Interrupt Mask Register (IMR)
796  * 31:00 Various Mask bits for the Interrupt Cause register.
797  */
798 
799 /*
800  * Table 609: IP Differentiated Services CodePoint to Priority0 low (DSCP2P0L),
801  * 31:00 Priority0_low The LSB priority bits for DSCP[31:0] entries.
802  */
803 
804 /*
805  * Table 610: IP Differentiated Services CodePoint to Priority0 high (DSCP2P0H)
806  * 31:00 Priority0_high The LSB priority bits for DSCP[63:32] entries.
807  */
808 
809 /*
810  * Table 611: IP Differentiated Services CodePoint to Priority1 low (DSCP2P1L)
811  * 31:00 Priority1_low The MSB priority bits for DSCP[31:0] entries.
812  */
813 
814 /*
815  * Table 612: IP Differentiated Services CodePoint to Priority1 high (DSCP2P1H)
816  * 31:00 Priority1_high The MSB priority bit for DSCP[63:32] entries.
817  */
818 
819 /*
820  * Table 613: VLAN Priority Tag to Priority (VPT2P)
821  * 07:00 Priority0 The LSB priority bits for VLAN Priority[7:0]
822  * entries.
823  * 15:08 Priority1 The MSB priority bits for VLAN Priority[7:0]
824  * entries.
825  * 31:16 Reserved
826  */
827 
828 /* Address control registers -- these are offsets from the GT base
829  * and NOT from the ethernet port base. <tss>
830  */
831 #define ETH_ACTL_0_LO 0xf200
832 
833 /* Enable hardware cache snooping;
834  * Copyright Shuchen K. Feng <feng1@bnl.gov>, 2004
835  */
836 
837 /* Ethernet address control (Low) snoop bits */
838 #define RxBSnoopEn ETH__BIT(6) /* Rx buffer snoop enable,1=enable*/
839 #define TxBSnoopEn ETH__BIT(14) /* Tx buffer snoop enable */
840 #define RxDSnoopEn ETH__BIT(22) /* Rx descriptor snoop enable */
841 #define TxDSnoopEn ETH__BIT(30) /* Tx descriptor snoop enable */
842 
843 #define ETH_ACTL_0_HI 0xf204
844 /* Ethernet address control (High), snoop bits */
845 #define HashSnoopEn ETH__BIT(6) /* Hash Table snoop enable */
846 
847 
848 #define ETH_ACTL_1_LO 0xf220
849 #define ETH_ACTL_1_HI 0xf224
850 #define ETH_ACTL_2_LO 0xf240
851 #define ETH_ACTL_2_HI 0xf244
852 
853 
854 #endif /* _DEV_GTETHREG_H_ */
gt_eth_desc
Definition: gtethreg.h:61
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