RISCV Architecture Support.
More...
|
#define | RISCV_CONTEXT_ISR_DISPATCH_DISABLE 4 |
|
#define | RISCV_EXCEPTION_FRAME_MCAUSE RISCV_EXCEPTION_FRAME_X( 0 ) |
|
#define | RISCV_EXCEPTION_FRAME_SP RISCV_EXCEPTION_FRAME_X( 1 ) |
|
#define | RISCV_EXCEPTION_FRAME_GP RISCV_EXCEPTION_FRAME_X( 2 ) |
|
#define | RISCV_EXCEPTION_FRAME_TP RISCV_EXCEPTION_FRAME_X( 3 ) |
|
#define | RISCV_EXCEPTION_FRAME_S2 RISCV_EXCEPTION_FRAME_X( 4 ) |
|
#define | RISCV_EXCEPTION_FRAME_S3 RISCV_EXCEPTION_FRAME_X( 5 ) |
|
#define | RISCV_EXCEPTION_FRAME_S4 RISCV_EXCEPTION_FRAME_X( 6 ) |
|
#define | RISCV_EXCEPTION_FRAME_S5 RISCV_EXCEPTION_FRAME_X( 7 ) |
|
#define | RISCV_EXCEPTION_FRAME_S6 RISCV_EXCEPTION_FRAME_X( 8 ) |
|
#define | RISCV_EXCEPTION_FRAME_S7 RISCV_EXCEPTION_FRAME_X( 9 ) |
|
#define | RISCV_EXCEPTION_FRAME_S8 RISCV_EXCEPTION_FRAME_X( 10 ) |
|
#define | RISCV_EXCEPTION_FRAME_S9 RISCV_EXCEPTION_FRAME_X( 11 ) |
|
#define | RISCV_EXCEPTION_FRAME_S10 RISCV_EXCEPTION_FRAME_X( 12 ) |
|
#define | RISCV_EXCEPTION_FRAME_S11 RISCV_EXCEPTION_FRAME_X( 13 ) |
|
#define | RISCV_PLIC_MAX_INTERRUPTS 1024 |
|
|
void | _RISCV_Interrupt_dispatch (uintptr_t mcause, struct Per_CPU_Control *cpu_self) |
|
void | _CPU_Context_volatile_clobber (uintptr_t pattern) |
|
void | _CPU_Context_validate (uintptr_t pattern) |
|
RTEMS_INLINE_ROUTINE void | _CPU_Instruction_illegal (void) |
|
RTEMS_INLINE_ROUTINE void | _CPU_Instruction_no_operation (void) |
|
|
volatile uint32_t * | _RISCV_Counter_mutable |
|
volatile uint32_t | _RISCV_Counter_register |
|
RISCV Architecture Support.