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#define | VAR(i) (i) |
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#define | VAR_COUNT 24 |
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#define | INC(i) (24 + (i)) |
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#define | INC_COUNT 8 |
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#define | IDX(i) (48 + (i)) |
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#define | IDX_COUNT 8 |
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#define | COND_ONCE 0 |
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#define | COND_LT 1 |
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#define | COND_GT 2 |
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#define | COND_NE 3 |
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#define | COND_EQ 4 |
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#define | COND_LE 5 |
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#define | COND_GE 6 |
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#define | COND_FOREVER 7 |
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#define | INC_INIT(cond, val) |
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#define | TERM_FIRST 0 |
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#define | TERM_SECOND 1 |
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#define | TERM_INIT 2 |
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#define | TERM_UNUSED 3 |
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#define | DEREF 1 |
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#define | LCD_TERM(val) BSP_FLD32(val, 13, 14) |
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#define | LCD(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) |
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#define | LCDEXT(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) |
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#define | LCDPLUS(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) |
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#define | LCDINIT(val) |
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#define | MORE 0x4 |
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#define | TFD 0x2 |
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#define | INT 0x1 |
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#define | DRD_FLAGS(val) BSP_FLD32(val, 26, 28) |
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#define | INIT_ALWAYS 0 |
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#define | INIT_SCTMR_0 1 |
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#define | INIT_SCTMR_1 2 |
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#define | INIT_FEC_RX 3 |
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#define | INIT_FEC_TX 4 |
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#define | INIT_ATA_RX 5 |
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#define | INIT_ATA_TX 6 |
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#define | INIT_SCPCI_RX 7 |
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#define | INIT_SCPCI_TX 8 |
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#define | INIT_PSC3_RX 9 |
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#define | INIT_PSC3_TX 10 |
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#define | INIT_PSC2_RX 11 |
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#define | INIT_PSC2_TX 12 |
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#define | INIT_PSC1_RX 13 |
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#define | INIT_PSC1_TX 14 |
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#define | INIT_SCTMR_2 15 |
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#define | INIT_SCLPC 16 |
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#define | INIT_PSC5_RX 17 |
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#define | INIT_PSC5_TX 18 |
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#define | INIT_PSC4_RX 19 |
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#define | INIT_PSC4_TX 20 |
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#define | INIT_I2C2_RX 21 |
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#define | INIT_I2C2_TX 22 |
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#define | INIT_I2C1_RX 23 |
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#define | INIT_I2C1_TX 24 |
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#define | INIT_PSC6_RX 25 |
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#define | INIT_PSC6_TX 26 |
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#define | INIT_IRDA_RX 25 |
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#define | INIT_IRDA_TX 26 |
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#define | INIT_SCTMR_3 27 |
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#define | INIT_SCTMR_4 28 |
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#define | INIT_SCTMR_5 29 |
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#define | INIT_SCTMR_6 30 |
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#define | INIT_SCTMR_7 31 |
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#define | DRD_INIT(val) BSP_FLD32(val, 21, 25) |
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#define | SZ_8 1 |
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#define | SZ_16 2 |
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#define | SZ_32 0 |
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#define | SZ_DYN 3 |
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#define | DRD_RS(val) BSP_FLD32(val, 19, 20) |
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#define | DRD_WS(val) BSP_FLD32(val, 17, 18) |
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#define | DEST_VAR(val) (val) |
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#define | DEST_IDX(val) (BSP_BIT32(5) | (val)) |
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#define | DEST_DEREF_IDX(val) (BSP_BIT32(5) | BSP_BIT32(4) | (val)) |
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#define | SRC_VAR(val) (val) |
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#define | SRC_INC(val) (BSP_BIT32(5) | (val)) |
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#define | SRC_EU_RESULT (BSP_BIT32(5) | BSP_BIT32(4) | BSP_BIT32(1) | BSP_BIT32(0)) |
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#define | SRC_DEREF_EU_RESULT (BSP_BIT32(6) | BSP_BIT32(4) | BSP_BIT32(1) | BSP_BIT32(0)) |
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#define | SRC_IDX(val) (BSP_BIT32(6) | BSP_BIT32(5) | (val)) |
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#define | SRC_DEREF_IDX(val) (BSP_BIT32(6) | BSP_BIT32(5) | BSP_BIT32(4) | (val)) |
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#define | SRC_NONE (BSP_BIT32(5) | BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(2) | BSP_BIT32(1) | BSP_BIT32(0)) |
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#define | DRD1A(flags, init, dest, ws, src, rs) |
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#define | DRD1AEURESULT(flags, init, dest, ws, rs) |
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#define | FUNC_LOAD_ACC 0 |
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#define | FUNC_UNLOAD_ACC 1 |
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#define | FUNC_AND 2 |
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#define | FUNC_OR 3 |
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#define | FUNC_XOR 4 |
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#define | FUNC_ANDN 5 |
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#define | FUNC_NOT 6 |
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#define | FUNC_ADD 7 |
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#define | FUNC_SUB 8 |
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#define | FUNC_LSH 9 |
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#define | FUNC_RSH 10 |
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#define | FUNC_CRC8 11 |
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#define | FUNC_CRC16 12 |
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#define | FUNC_CRC32 13 |
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#define | FUNC_ENDIAN32 14 |
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#define | FUNC_ENDIAN16 15 |
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#define | DRD2A(flags, func) |
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#define | DRD2A5(flags, init, func, ws, rs) |
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#define | OP_VAR(val) (val) |
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#define | OP_EU_RESULT (BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(1) | BSP_BIT32(0)) |
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#define | OP_NONE (BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(2) | BSP_BIT32(1) | BSP_BIT32(0)) |
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#define | OP_IDX(val) (BSP_BIT32(5) | (val)) |
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#define | OP_DEREF_IDX(val) (BSP_BIT32(5) | BSP_BIT32(4) | (val)) |
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#define | DRD2B1(dest, op0, op1) |
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#define | DRD2B2(op0, op1) |
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#define | NOP 0x1f8 |
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BestComm ops.