RTEMS  5.0.0
edid.h
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1 
16 /*
17  * Copyright (C) 2014 Jan Doležal (dolezj21@fel.cvut.cz)
18  * CTU in Prague.
19  *
20  * The license and distribution terms for this file may be
21  * found in the file LICENSE in this distribution or at
22  * http://www.rtems.org/license/LICENSE.
23  */
24 
25 #ifndef _EDID_H
26 #define _EDID_H
27 
28 #ifndef ASM /* ASM */
29 
30 #include <stdint.h>
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif /* __cplusplus */
35 
36 #include <rtems/score/basedefs.h>
37 #define EDID_INLINE_ROUTINE RTEMS_INLINE_ROUTINE
38 
39 /* VESA Enhanced Extended Display Identification Data (E-EDID) Proposed
40  Release A, March 27, 2007 */
41 
42 /* *** Detailed Timing Descriptor Flags *** */
43 #define EDID1_DTD_Flag_InterlacedOff 7
44 #define EDID1_DTD_Flag_InterlacedMask 0x1
45 #define EDID1_DTD_Flag_StereoModeOff 0
46 #define EDID1_DTD_Flag_StereoModeMask 0xC1
47 /* values for stereo flag */
48 #define EDID1_DTD_Stereo_FldSeqRightOnSync 0x40
49 #define EDID1_DTD_Stereo_FldSeqLeftOnSync 0x80
50 #define EDID1_DTD_Stereo_2wItlvdRightOnEven 0x41
51 #define EDID1_DTD_Stereo_2wItlvdLeftOnEven 0x81
52 #define EDID1_DTD_Stereo_4wInterleaved 0xC0
53 #define EDID1_DTD_Stereo_SideBySideItlvd 0xC1
54 /* Analog = 0, Digital = 1 */
55 #define EDID1_DTD_Flag_DigitalOff 4
56 #define EDID1_DTD_Flag_DigitalMask 0x1
57 /* Analog */
58 #define EDID1_DTD_BipolarAnalogComposSyncOff 3
59 #define EDID1_DTD_BipolarAnalogComposSyncMask 0x1
60 #define EDID1_DTD_WithSerrationsOff 2
61 #define EDID1_DTD_WithSerrationsMask 0x1
62 /* Digital */
63 #define EDID1_DTD_DigitalSeparateSyncOff 3
64 #define EDID1_DTD_DigitalSeparateSyncMask 0x1
65  /* when DigitalSeparateSync == 0 -> it is composite
66  and WithSerrations defined up in Analog part applies */
67 #define EDID1_DTD_VerticalSyncIsPositiveOff 2
68 #define EDID1_DTD_VerticalSyncIsPositiveMask 0x1
69 #define EDID1_DTD_HorizontalSyncIsPositiveOff 1
70 #define EDID1_DTD_HorizontalSyncIsPositiveMask 0x1
71 
72 typedef struct {
73  uint8_t PixelClock_div10000[2];
74  uint8_t HorizontalActiveLow;
75  uint8_t HorizontalBlankingLow;
76  uint8_t HorizontalBlanking_ActiveHigh;
77  uint8_t VerticalActiveLow;
78  uint8_t VerticalBlankingLow;
79  uint8_t VerticalBlanking_ActiveHigh;
80  uint8_t HorizontalSyncOffsetLow;
81  uint8_t HorizontalSyncPulseWidthLow;
82  uint8_t VerticalSyncPulseWidth_OffsetLow;
83  uint8_t Vert_Hor_SyncPulseWidth_Offset_High;
84  uint8_t HorizontalImageSizeLow;
85  uint8_t VerticalImageSizeLow;
86  uint8_t Vertical_HorizontalImageSizeHigh;
87  uint8_t HorizontalBorder;
88  uint8_t VerticalBorder;
89  uint8_t Flags;
90 } RTEMS_PACKED EDID_detailed_timing_descriptor;
91 
92 EDID_INLINE_ROUTINE uint16_t DTD_horizontal_active (
93  EDID_detailed_timing_descriptor *dtd)
94 {
95  return (dtd->HorizontalActiveLow |
96  (dtd->HorizontalBlanking_ActiveHigh & 0xF0) << 4);
97 }
98 
99 EDID_INLINE_ROUTINE uint16_t DTD_horizontal_blanking (
100  EDID_detailed_timing_descriptor *dtd)
101 {
102  return (dtd->HorizontalBlankingLow |
103  (dtd->HorizontalBlanking_ActiveHigh & 0xF) << 8);
104 }
105 
106 EDID_INLINE_ROUTINE uint16_t DTD_vertical_active (
107  EDID_detailed_timing_descriptor *dtd)
108 {
109  return (dtd->VerticalActiveLow |
110  (dtd->VerticalBlanking_ActiveHigh & 0xF0) << 4);
111 }
112 
113 EDID_INLINE_ROUTINE uint16_t DTD_vertical_blanking (
114  EDID_detailed_timing_descriptor *dtd)
115 {
116  return (dtd->VerticalBlankingLow |
117  (dtd->VerticalBlanking_ActiveHigh & 0xF) << 8);
118 }
119 
120 EDID_INLINE_ROUTINE uint16_t DTD_vertical_sync_pulse_width (
121  EDID_detailed_timing_descriptor *dtd)
122 {
123  return ((dtd->VerticalSyncPulseWidth_OffsetLow & 0xF) |
124  (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0x3) << 4);
125 }
126 
127 EDID_INLINE_ROUTINE uint16_t DTD_vertical_sync_offset (
128  EDID_detailed_timing_descriptor *dtd)
129 {
130  return ((dtd->VerticalSyncPulseWidth_OffsetLow >> 4) |
131  (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0xC) << 2);
132 }
133 
134 EDID_INLINE_ROUTINE uint16_t DTD_horizontal_sync_pulse_width (
135  EDID_detailed_timing_descriptor *dtd)
136 {
137  return (dtd->HorizontalSyncPulseWidthLow |
138  (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0x30) << 4);
139 }
140 
141 EDID_INLINE_ROUTINE uint16_t DTD_horizontal_sync_offset (
142  EDID_detailed_timing_descriptor *dtd)
143 {
144  return (dtd->HorizontalSyncOffsetLow |
145  (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0xC0) << 2);
146 }
147 
148 EDID_INLINE_ROUTINE uint16_t DTD_vertical_image_size (
149  EDID_detailed_timing_descriptor *dtd)
150 {
151  return (dtd->VerticalImageSizeLow |
152  (dtd->Vertical_HorizontalImageSizeHigh & 0xF) << 8);
153 }
154 
155 EDID_INLINE_ROUTINE uint16_t DTD_horizontal_image_size (
156  EDID_detailed_timing_descriptor *dtd)
157 {
158  return (dtd->HorizontalImageSizeLow |
159  (dtd->Vertical_HorizontalImageSizeHigh & 0xF0) << 4);
160 }
161 
162 typedef struct {
163  uint8_t ColorPointWhitePointIndexNumber;
164  uint8_t ColorPointWhiteLowBits;
165  uint8_t ColorPointWhite_x;
166  uint8_t ColorPointWhite_y;
167  uint8_t ColorPointWhiteGamma;
168 } RTEMS_PACKED EDID_color_point_data;
169 
170 /* Basic Display Parameters */
171 /* Monitor Descriptor - Data Type Tag */
172 #define EDID_DTT_MonitorSerialNumber 0xFF
173 
174 #define EDID_DTT_ASCIIString 0xFE
175 
176 #define EDID_DTT_MonitorRangeLimits 0xFD
177 typedef struct {
178  uint8_t MinVerticalRateInHz;
179  uint8_t MaxVerticalRateInHz;
180  uint8_t MinHorizontalInKHz;
181  uint8_t MaxHorizontalInKHz;
182  uint8_t MaxSupportedPixelClockIn10MHz;
183 /* see VESA, Generalized Timing Formula Standard - GTF
184  Version 1.0, December 18, 1996 */
185  uint8_t GTFStandard[8];
186 } RTEMS_PACKED EDID_monitor_range_limits;
187 
188 #define EDID_DTT_MonitorName 0xFC
189 
190 #define EDID_DTT_AdditionalColorPointData 0xFB
191 /* Standard Timing Identification */
192 #define EDID_DTT_AdditionalSTI 0xFA
193 
194 #define EDID_DTT_DisplayColorManagement 0xF9
195 
196 #define EDID_DTT_CVT3ByteTimingCodes 0xF8
197 
198 #define EDID1_CVT_AspectRatioOff 2
199 #define EDID1_CVT_AspectRatioMask 0x3
200 #define EDID1_CVT_AddressableLinesHighOff 4
201 #define EDID1_CVT_AddressableLinesHighMask 0xF
202  /* next 5 bits indicate supported vertical rates */
203 #define EDID1_CVT_VerticalRate60HzRBOff 0
204 #define EDID1_CVT_VerticalRate60HzRBMask 0x1
205 #define EDID1_CVT_VerticalRate85HzOff 1
206 #define EDID1_CVT_VerticalRate85HzMask 0x1
207 #define EDID1_CVT_VerticalRate75HzOff 2
208 #define EDID1_CVT_VerticalRate75HzMask 0x1
209 #define EDID1_CVT_VerticalRate60HzOff 3
210 #define EDID1_CVT_VerticalRate60HzMask 0x1
211 #define EDID1_CVT_VerticalRate50HzOff 4
212 #define EDID1_CVT_VerticalRate50HzMask 0x1
213 #define EDID1_CVT_PreferredVerticalRateOff 5
214 #define EDID1_CVT_PreferredVerticalRateMask 0x3
215 
216 #define EDID_CVT_AspectRatio_4_3 0
217 #define EDID_CVT_AspectRatio_16_9 1
218 #define EDID_CVT_AspectRatio_16_10 2
219 #define EDID_CVT_AspectRatio_15_9 3
220 #define EDID_CVT_PrefVertRate50Hz 0
221 #define EDID_CVT_PrefVertRate60Hz 1
222 #define EDID_CVT_PrefVertRate75Hz 2
223 #define EDID_CVT_PrefVertRate85Hz 3
224 typedef struct {
225  uint8_t AddressableLinesLow;
226  uint8_t AspectRatio_AddressableLinesHigh;
227  uint8_t VerticalRate_PreferredVerticalRate;
228 } RTEMS_PACKED EDID_CVT_3_byte_code_descriptor;
229 typedef struct {
230  uint8_t VersionNumber;
231  EDID_CVT_3_byte_code_descriptor cvt[4];
232 } RTEMS_PACKED EDID_CVT_timing_codes_3B;
233 
234 EDID_INLINE_ROUTINE uint16_t edid1_CVT_addressable_lines_high (
235  EDID_CVT_3_byte_code_descriptor *cvt)
236 {
237  return (cvt->AddressableLinesLow |
238  (cvt->VerticalRate_PreferredVerticalRate &
239  (EDID1_CVT_AddressableLinesHighMask<<EDID1_CVT_AddressableLinesHighOff)
240  ) << (8-EDID1_CVT_AddressableLinesHighOff) );
241 }
242 
243 EDID_INLINE_ROUTINE uint8_t edid1_CVT_aspect_ratio (
244  EDID_CVT_3_byte_code_descriptor *cvt)
245 {
246  return (cvt->AspectRatio_AddressableLinesHigh >> EDID1_CVT_AspectRatioOff) &
247  EDID1_CVT_AspectRatioMask;
248 }
249 
250 #define EDID_DTT_EstablishedTimingsIII 0xF7
251 typedef struct {
252  uint8_t RevisionNumber;
253  uint8_t EST_III[12];
254 } RTEMS_PACKED EDID_established_timings_III;
255 enum EST_III {
256  EST_1152x864_75Hz = 0,
257  EST_1024x768_85Hz = 1,
258  EST_800x600_85Hz = 2,
259  EST_848x480_60Hz = 3,
260  EST_640x480_85Hz = 4,
261  EST_720x400_85Hz = 5,
262  EST_640x400_85Hz = 6,
263  EST_640x350_85Hz = 7,
264 
265  EST_1280x1024_85Hz = 8,
266  EST_1280x1024_60Hz = 9,
267  EST_1280x960_85Hz = 10,
268  EST_1280x960_60Hz = 11,
269  EST_1280x768_85Hz = 12,
270  EST_1280x768_75Hz = 13,
271  EST_1280x768_60Hz = 14,
272  EST_1280x768_60HzRB = 15,
273 
274  EST_1400x1050_75Hz = 16,
275  EST_1400x1050_60Hz = 17,
276  EST_1400x1050_60HzRB= 18,
277  EST_1400x900_85Hz = 19,
278  EST_1400x900_75Hz = 20,
279  EST_1400x900_60Hz = 21,
280  EST_1400x900_60HzRB = 22,
281  EST_1360x768_60Hz = 23,
282 
283  EST_1600x1200_70Hz = 24,
284  EST_1600x1200_65Hz = 25,
285  EST_1600x1200_60Hz = 26,
286  EST_1680x1050_85Hz = 27,
287  EST_1680x1050_75Hz = 28,
288  EST_1680x1050_60Hz = 29,
289  EST_1680x1050_60HzRB= 30,
290  EST_1400x1050_85Hz = 31,
291 
292  EST_1920x1200_60Hz = 32,
293  EST_1920x1200_60HzRB= 33,
294  EST_1856x1392_75Hz = 34,
295  EST_1856x1392_60Hz = 35,
296  EST_1792x1344_75Hz = 36,
297  EST_1792x1344_60Hz = 37,
298  EST_1600x1200_85Hz = 38,
299  EST_1600x1200_75Hz = 39,
300 
301  EST_1920x1440_75Hz = 44,
302  EST_1920x1440_60Hz = 45,
303  EST_1920x1200_85Hz = 46,
304  EST_1920x1200_75Hz = 47,
305 };
306 
307 #define EDID_DTT_DescriptorSpaceUnused 0x10
308 /* DTT 0x0 - 0xF are manufacturer specific */
309 
310 typedef struct {
311  uint8_t Flag0[2];
312  uint8_t Flag1;
313  uint8_t DataTypeTag;
314  uint8_t Flag2;
315  uint8_t DescriptorData[13];
316 } RTEMS_PACKED EDID_monitor_descriptor;
317 
318 union EDID_DTD_MD {
319  EDID_detailed_timing_descriptor dtd;
320  EDID_monitor_descriptor md;
321 } RTEMS_PACKED;
322 
323 #define EDID1_STI_ImageAspectRatioOff 0
324 #define EDID1_STI_ImageAspectRatioMask 0x3
325 #define EDID1_STI_RefreshRateOff 2
326 #define EDID1_STI_RefreshRateMask 0x3F
327 
328 #define EDID_STI_DescriptorUnused 0x0101
329 #define EDID_STI_AspectRatio_16_10 0
330 #define EDID_STI_AspectRatio_4_3 1
331 #define EDID_STI_AspectRatio_5_4 2
332 #define EDID_STI_AspectRatio_16_9 3
333 typedef struct {
334  uint8_t HorizontalActivePixels;
335  uint8_t ImageAspectRatio_RefreshRate;
336 } RTEMS_PACKED EDID_standard_timing_identification;
337 
338 /* Video Input Definition */
339 /* Analog = 0, Digital = 1 */
340 #define EDID1_VID_DigitalSignalLevelOff 7
341 #define EDID1_VID_DigitalSignalLevelMask 0x1
342 /* for EDID1_VID_DigitalSignalLevelOff = 1 (Digital) */
343 #define EDID1_VID_ColorBitDepthOff 4
344 #define EDID1_VID_ColorBitDepthMask 0x7 /* see CBD */
345 #define EDID1_VID_DigitalVideoStandardSuppOff 0
346 #define EDID1_VID_DigitalVideoStandardSuppMask 0xF /* see DVS */
347 /* for EDID1_VID_DigitalSignalLevelOff = 0 (Analog) */
348 #define EDID1_VID_SignalLevelStandardOff 5
349 #define EDID1_VID_SignalLevelStandardMask 0x3
350 #define EDID1_VID_VideoSetupBlankOff 4
351 #define EDID1_VID_VideoSetupBlankMask 0x1
352 #define EDID1_VID_SeparateSyncHandVSignalsOff 3
353 #define EDID1_VID_SeparateSyncHandVSignalsMask 0x1
354 #define EDID1_VID_SyncSignalOnHorizontalOff 2
355 #define EDID1_VID_SyncSignalOnHorizontalMask 0x1
356 #define EDID1_VID_SyncSignalOnGreenOff 1
357 #define EDID1_VID_SyncSignalOnGreenMask 0x1
358 #define EDID1_VID_SerationOnVerticalSyncOff 0
359 #define EDID1_VID_SerationOnVerticalSyncMask 0x1
360 /* Analog Interface Data Format - Signal Level Standard */
361 #define EDID_SLS_0700_0300_1000Vpp 0x0
362 #define EDID_SLS_0714_0286_1000Vpp 0x1
363 #define EDID_SLS_1000_0400_1400Vpp 0x2
364 #define EDID_SLS_0700_0000_0700Vpp 0x3
365 
366 /* Color Bit Depths */
367 #define CBD_undef 0x0
368 #define CBD_6bPerPrimaryColor 0x1
369 #define CBD_8bPerPrimaryColor 0x2
370 #define CBD_10bPerPrimaryColor 0x3
371 #define CBD_12bPerPrimaryColor 0x4
372 #define CBD_14bPerPrimaryColor 0x5
373 #define CBD_16bPerPrimaryColor 0x6
374 #define CBD_reserved 0x7
375 
376 /* Digital Video Standard Supported */
377 #define DVS_undef 0x0
378 #define DVS_DVI 0x1
379 #define DVS_HDMI_a 0x2
380 #define DVS_HDMI_b 0x3
381 #define DVS_MDDI 0x4
382 #define DVS_DiplayPort 0x5
383 
384 /* Feature Support */
385 #define EDID1_Feature_GTFSupported_mask 0x1
386 #define EDID1_Feature_GTFSupported_off 0
387 #define EDID1_Feature_PreferredTimingMode_mask 0x1
388 #define EDID1_Feature_PreferredTimingMode_off 1
389 #define EDID1_Feature_StandardDefaultColorSpace_mask 0x1
390 #define EDID1_Feature_StandardDefaultColorSpace_off 2
391 #define EDID1_Feature_DisplayType_mask 0x2
392 #define EDID1_Feature_DisplayType_off 3
393  /* Refer to VESA DPMS Specification */
394 #define EDID1_Feature_ActiveOff_mask 0x1
395 #define EDID1_Feature_ActiveOff_off 5
396 #define EDID1_Feature_Suspend_mask 0x1
397 #define EDID1_Feature_Suspend_off 6
398 #define EDID1_Feature_StandBy_mask 0x1
399 #define EDID1_Feature_StandBy_off 7
400  /* analog - Display Color Type */
401 #define EDID_DisplayType_Monochrome 0
402 #define EDID_DisplayType_RGBcolor 1
403 #define EDID_DisplayType_nonRGBcolor 2
404 #define EDID_DisplayType_undef 3
405  /* digital - Supported Color Encoding Formats */
406 #define EDID_DisplayType_RGB444 0
407 #define EDID_DisplayType_RGB444YCrCb444 1
408 #define EDID_DisplayType_RGB444YCrCb422 2
409 #define EDID_DisplayType_RGB444YCrCb444YCrCb422 3
410 
411 typedef struct {
412  uint8_t Header[8];
413 /* Vendor Product Identification */
414  uint8_t IDManufacturerName[2];
415  uint8_t IDProductCode[2];
416  uint8_t IDSerialNumber[4];
417  uint8_t WeekofManufacture;
418  uint8_t YearofManufacture;
419 /* EDID Structure Version Revision Level */
420  uint8_t Version;
421  uint8_t Revision;
422 /* Basic Display Parameters Features */
423  /* Video Input Definition */
424  uint8_t VideoInputDefinition;
425  uint8_t MaxHorizontalImageSize;
426  uint8_t MaxVerticalImageSize;
427  uint8_t DisplayTransferCharacteristic;
428  /* Feature Support */
429  uint8_t Features;
430 /* Color Characteristics */
431  uint8_t GreenRedLow;
432  uint8_t WhiteBlueLow;
433  uint8_t RedXHigh;
434  uint8_t RedYHigh;
435  uint8_t GreenXHigh;
436  uint8_t GreenYHigh;
437  uint8_t BlueXHigh;
438  uint8_t BlueYHigh;
439  uint8_t WhiteXHigh;
440  uint8_t WhiteYHigh;
441 /* Established Timings I, II, Manufacturer's */
442  uint8_t EST_I_II_Man[3];
443 /* Standard Timing Identification */
444  EDID_standard_timing_identification STI[8];
445 /* Detailed Timing Descriptions / Monitor Descriptions */
446  union EDID_DTD_MD dtd_md[4];
447  uint8_t ExtensionFlag;
448  uint8_t Checksum;
449 } RTEMS_PACKED EDID_edid1;
450 
451 EDID_INLINE_ROUTINE uint16_t edid1_RedX (EDID_edid1 *edid) {
452  return (edid->RedXHigh<<2) | (edid->GreenRedLow>>6);
453 }
454 EDID_INLINE_ROUTINE uint16_t edid1_RedY (EDID_edid1 *edid) {
455  return (edid->RedYHigh<<2) | (edid->GreenRedLow>>4)&&0x3;
456 }
457 EDID_INLINE_ROUTINE uint16_t edid1_GreenX (EDID_edid1 *edid) {
458  return (edid->GreenXHigh<<2) | (edid->GreenRedLow>>2)&&0x3;
459 }
460 EDID_INLINE_ROUTINE uint16_t edid1_GreenY (EDID_edid1 *edid) {
461  return (edid->GreenYHigh<<2) | (edid->GreenRedLow&0x3);
462 }
463 EDID_INLINE_ROUTINE uint16_t edid1_BlueX (EDID_edid1 *edid) {
464  return (edid->BlueXHigh<<2) | (edid->WhiteBlueLow>>6);
465 }
466 EDID_INLINE_ROUTINE uint16_t edid1_BlueY (EDID_edid1 *edid) {
467  return (edid->BlueYHigh<<2) | (edid->WhiteBlueLow>>4)&&0x3;
468 }
469 EDID_INLINE_ROUTINE uint16_t edid1_WhiteX (EDID_edid1 *edid) {
470  return (edid->WhiteXHigh<<2) | (edid->WhiteBlueLow>>2)&&0x3;
471 }
472 EDID_INLINE_ROUTINE uint16_t edid1_WhiteY (EDID_edid1 *edid) {
473  return (edid->WhiteYHigh<<2) | (edid->WhiteBlueLow&0x3);
474 }
475 
476 EDID_INLINE_ROUTINE int edid1_STI_is_unused (
477  const EDID_standard_timing_identification *edid_sti) {
478  return (edid_sti->HorizontalActivePixels ==
479  (uint8_t)EDID_STI_DescriptorUnused) &&
480  (edid_sti->ImageAspectRatio_RefreshRate ==
481  (uint8_t)(EDID_STI_DescriptorUnused >> 8));
482 }
483 
484 enum edid1_established_timings {
485 /* Established Timings I */
486  EST_800x600_60Hz = 0,
487  EST_800x600_56Hz = 1,
488  EST_640x480_75Hz = 2,
489  EST_640x480_72Hz = 3,
490  EST_640x480_67Hz = 4,
491  EST_640x480_60Hz = 5,
492  EST_720x400_88Hz = 6,
493  EST_720x400_70Hz = 7,
494 /* Established Timings II */
495  EST_1280x1024_75Hz = 8,
496  EST_1024x768_75Hz = 9,
497  EST_1024x768_70Hz = 10,
498  EST_1024x768_60Hz = 11,
499  EST_1024x768_87Hz = 12,
500  EST_832x624_75Hz = 13,
501  EST_800x600_75Hz = 14,
502  EST_800x600_72Hz = 15,
503 /* Manufacturer's Timings */
504  EST_1152x870_75Hz = 23,
505 };
506 
507 EDID_INLINE_ROUTINE uint8_t edid1_established_tim (
508  EDID_edid1 *edid,
509  enum edid1_established_timings est)
510 {
511  return (uint8_t)(edid->EST_I_II_Man[est/8] & (est%8));
512 }
513 
514 #ifdef __cplusplus
515 }
516 #endif /* __cplusplus */
517 
518 #endif /* ASM */
519 
520 #endif /* _VBE_H */
Definition: edid.h:318
#define RTEMS_PACKED
Definition: basedefs.h:175
Used for passing and retrieving registers content to/from real mode interrupt call.
Definition: realmode_int.h:43
Basic Definitions.