RTEMS
5.0.0
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ARM Assembler Support API. More...
Go to the source code of this file.
Macros | |
#define | ASM |
#define | __USER_LABEL_PREFIX__ _ |
#define | __REGISTER_PREFIX__ |
#define | SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) |
#define | REG(x) CONCAT1 (__REGISTER_PREFIX__, x) |
#define | r0 REG(r0) |
#define | r1 REG(r1) |
#define | r2 REG(r2) |
#define | r3 REG(r3) |
#define | r4 REG(r4) |
#define | r5 REG(r5) |
#define | r6 REG(r6) |
#define | r7 REG(r7) |
#define | r8 REG(r8) |
#define | r9 REG(r9) |
#define | r10 REG(r10) |
#define | r11 REG(r11) |
#define | r12 REG(r12) |
#define | r13 REG(r13) |
#define | r14 REG(r14) |
#define | r15 REG(r15) |
#define | CPSR REG(CPSR) |
#define | SPSR REG(SPSR) |
#define | NUM_IRQ_VECTOR 6 |
#define | NUM_FIQ_VECTOR 7 |
#define | CPSR_IRQ_DISABLE 0x80 |
#define | CPSR_FIQ_DISABLE 0x40 |
#define | CPSR_THUMB_ENABLE 0x20 |
#define | CPSR_FIQ_MODE 0x11 |
#define | CPSR_IRQ_MODE 0x12 |
#define | CPSR_SUPERVISOR_MODE 0x13 |
#define | CPSR_UNDEF_MODE 0x1B |
#define | CPSR_MODE_BITS 0x1F |
#define | BEGIN_CODE_DCL .text |
#define | END_CODE_DCL |
#define | BEGIN_DATA_DCL .data |
#define | END_DATA_DCL |
#define | BEGIN_CODE .text |
#define | END_CODE |
#define | BEGIN_DATA |
#define | END_DATA |
#define | BEGIN_BSS |
#define | END_BSS |
#define | END |
#define | PUBLIC(sym) .globl SYM (sym) |
#define | EXTERN(sym) .globl SYM (sym) |
#define | FUNCTION_THUMB_ENTRY(name) |
#define | FUNCTION_ENTRY(name) |
#define | FUNCTION_END(name) .size name, . - name |
#define | DEFINE_FUNCTION_ARM(name) .globl name ; name: ; .globl name ## _arm ; name ## _arm: |
ARM Assembler Support API.
This include file attempts to address the problems caused by incompatible flavors of assemblers and toolsets. It primarily addresses variations in the use of leading underscores on symbols and the requirement that register names be preceded by a %.
NOTE: The spacing in the use of these macros is critical to them working as advertised.