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#define | BBB_I2C_CON_EN (1 << 15) /* I2C module enable */ |
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#define | BBB_I2C_CON_BE (1 << 14) /* Big endian mode */ |
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#define | BBB_I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ |
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#define | BBB_I2C_CON_MST (1 << 10) /* Master/slave mode */ |
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#define | BBB_I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ |
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#define | BBB_I2C_CON_XA (1 << 8) /* Expand address */ |
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#define | BBB_I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ |
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#define | BBB_I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ |
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#define | BBB_I2C_CON_CLR 0x0 /* Clear configuration register */ |
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#define | BBB_I2C_STAT_SBD (1 << 15) /* Single byte data */ |
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#define | BBB_I2C_STAT_BB (1 << 12) /* Bus busy */ |
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#define | BBB_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ |
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#define | BBB_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ |
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#define | BBB_I2C_STAT_AAS (1 << 9) /* Address as slave */ |
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#define | BBB_I2C_STAT_GC (1 << 5) |
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#define | BBB_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ |
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#define | BBB_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ |
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#define | BBB_I2C_STAT_ARDY (1 << 2) /* Register access ready */ |
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#define | BBB_I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ |
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#define | BBB_I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ |
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#define | BBB_I2C_IE_GC_IE (1 << 5) |
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#define | BBB_I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ |
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#define | BBB_I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ |
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#define | BBB_I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ |
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#define | BBB_I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ |
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#define | BBB_I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ |
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#define | BBB_I2C_SYSC_SRST (1 << 1) |
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#define | BBB_I2C_TIMEOUT 1000 |
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#define | BBB_I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */ |
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#define | BBB_CONFIG_SYS_I2C_SPEED 100000 |
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#define | BBB_CONFIG_SYS_I2C_SLAVE 1 |
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#define | BBB_I2C_ALL_FLAGS 0x7FFF |
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#define | BBB_I2C_ALL_IRQ_FLAGS 0xFFFF |
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#define | BBB_I2C_SYSCLK 48000000 |
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#define | BBB_I2C_INTERNAL_CLK 12000000 |
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#define | BBB_I2C_SPEED_CLK 100000 |
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#define | BBB_I2C_IRQ_ERROR |
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#define | BBB_I2C_IRQ_USED |
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#define | BBB_I2C_0_BUS_PATH "/dev/i2c-0" |
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#define | BBB_I2C_1_BUS_PATH "/dev/i2c-1" |
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#define | BBB_I2C_2_BUS_PATH "/dev/i2c-2" |
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#define | BBB_I2C0_IRQ 70 |
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#define | BBB_I2C1_IRQ 71 |
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#define | BBB_I2C2_IRQ 30 |
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#define | BBB_MODE2 2 |
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#define | BBB_MODE3 3 |
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