RTEMS  5.0.0
at91rm9200.h
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1 
9 /*
10  * Atmel AT91RM9200 Register definitions, used in KIT637_V6 (CSB637)
11  *
12  * Copyright (c) 2003 by Cogent Computer Systems
13  * Written by Mike Kelly <mike@cogcomp.com>
14  *
15  * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br>
16  * from NCB - Sistemas Embarcados Ltda. (Brazil)
17  *
18  * The license and distribution terms for this file may be
19  * found in the file LICENSE in this distribution or at
20  * http://www.rtems.org/license/LICENSE.
21 */
22 
23 
24 #ifndef __AT91RM9200_H__
25 #define __AT91RM9200_H__
26 
27 #include "bits.h"
28 
29 typedef volatile unsigned long vulong;
30 
31 /* Source Mode Register - 32 of them */
32 #define AIC_SMR_BASE 0xFFFFF000
33 #define AIC_SMR_REG(_x_) *(vulong *)(AIC_SMR_BASE + (_x_ & 0x7c))
34 
35 /* Source Vector Register - 32 of them */
36 #define AIC_SVR_BASE 0xFFFFF080
37 #define AIC_SVR_REG(_x_) *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c))
38 
39 /* Control Register - 32 of them */
40 #define AIC_CTL_BASE 0xFFFFF100
41 #define AIC_CTL_REG(_x_) *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f))
42 
43 /* Register Offsets */
44 /* offsets from AIC_SMR_BASE and AIC_SVR_BASE */
45 #define AIC_SMR_FIQ 0x00 /* Advanced Interrupt Controller FIQ */
46 #define AIC_SMR_SYSIRQ 0x04 /* Advanced Interrupt Controller SYSIRQ */
47 #define AIC_SMR_PIOA 0x08 /* Parallel I/O Controller A */
48 #define AIC_SMR_PIOB 0x0c /* Parallel I/O Controller B */
49 #define AIC_SMR_PIOC 0x10 /* Parallel I/O Controller C */
50 #define AIC_SMR_PIOD 0x14 /* Parallel I/O Controller D */
51 #define AIC_SMR_US0 0x18 /* USART 0 */
52 #define AIC_SMR_US1 0x1c /* USART 1 */
53 #define AIC_SMR_US2 0x20 /* USART 2 */
54 #define AIC_SMR_US3 0x24 /* USART 3 */
55 #define AIC_SMR_MCI 0x28 /* Multimedia Card Interface */
56 #define AIC_SMR_UDP 0x2c /* USB Device Port */
57 #define AIC_SMR_TWI 0x30 /* Two-wire Interface */
58 #define AIC_SMR_SPI 0x34 /* Serial Peripheral Interface */
59 #define AIC_SMR_SSC0 0x38 /* Synchronous Serial Controller 0 */
60 #define AIC_SMR_SSC1 0x3c /* Synchronous Serial Controller 1 */
61 #define AIC_SMR_SSC2 0x40 /* Synchronous Serial Controller 2 */
62 #define AIC_SMR_TC0 0x44 /* Timer/Counter 0 */
63 #define AIC_SMR_TC1 0x48 /* Timer/Counter 1 */
64 #define AIC_SMR_TC2 0x4c /* Timer/Counter 2 */
65 #define AIC_SMR_TC3 0x50 /* Timer/Counter 3 */
66 #define AIC_SMR_TC4 0x54 /* Timer/Counter 4 */
67 #define AIC_SMR_TC5 0x58 /* Timer/Counter 5 */
68 #define AIC_SMR_UHP 0x5c /* USB Host Port */
69 #define AIC_SMR_EMAC 0x60 /* Ethernet MAC */
70 #define AIC_SMR_IRQ0 0x64 /* Advanced Interrupt Controller IRQ0 */
71 #define AIC_SMR_IRQ1 0x68 /* Advanced Interrupt Controller IRQ1 */
72 #define AIC_SMR_IRQ2 0x6c /* Advanced Interrupt Controller IRQ2 */
73 #define AIC_SMR_IRQ3 0x70 /* Advanced Interrupt Controller IRQ3 */
74 #define AIC_SMR_IRQ4 0x74 /* Advanced Interrupt Controller IRQ4 */
75 #define AIC_SMR_IRQ5 0x78 /* Advanced Interrupt Controller IRQ5 */
76 #define AIC_SMR_IRQ6 0x7c /* Advanced Interrupt Controller IRQ6 */
77 
78 /* from AIC_CTL_BASE */
79 #define AIC_IVR 0x00 /* IRQ Vector Register */
80 #define AIC_FVR 0x04 /* FIQ Vector Register */
81 #define AIC_ISR 0x08 /* Interrupt Status Register */
82 #define AIC_IPR 0x0C /* Interrupt Pending Register */
83 #define AIC_IMR 0x10 /* Interrupt Mask Register */
84 #define AIC_CISR 0x14 /* Core Interrupt Status Register */
85 #define AIC_IECR 0x20 /* Interrupt Enable Command Register */
86 #define AIC_IDCR 0x24 /* Interrupt Disable Command Register */
87 #define AIC_ICCR 0x28 /* Interrupt Clear Command Register */
88 #define AIC_ISCR 0x2C /* Interrupt Set Command Register */
89 #define AIC_EOICR 0x30 /* End of Interrupt Command Register */
90 #define AIC_SPU 0x34 /* Spurious Vector Register */
91 #define AIC_DCR 0x38 /* Debug Control Register (Protect) */
92 #define AIC_FFER 0x40 /* Fast Forcing Enable Register */
93 #define AIC_FFDR 0x44 /* Fast Forcing Disable Register */
94 #define AIC_FFSR 0x48 /* Fast Forcing Status Register */
95 
96 /* Bit Defines */
97 /* AIC_ISR - Interrupt Status Register */
98 #define AIC_ISR_IRQID_MASK 0x1f /* current interrupt ID */
99 
100 /* AIC_CISR - Core Interrupt Status Register */
101 #define AIC_CISR_IRQ BIT1 /* 1 = Core IRQ is active */
102 #define AIC_CISR_FIQ BIT0 /* 1 = Core FIQ is active */
103 
104 /* AIC_DCR - Debug Control Register (Protect) */
105 #define AIC_DCR_GMSK BIT1 /* 0 = AIC controls IRQ and FIQ */
106 #define AIC_DCR_PROT BIT0 /* 1 = enable protection mode */
107 
108 /* AIC_SMR */
109 #define AIC_SMR_PRIOR(_x_) ((_x_ & 0x07) << 0)
110 #define AIC_SMR_SRC_LVL_LOW (0 << 5) /* Are these right? docs don't say which is high/low */
111 #define AIC_SMR_SRC_EDGE_LOW (1 << 5)
112 #define AIC_SMR_SRC_LVL_HI (2 << 5)
113 #define AIC_SMR_SRC_EDGE_HI (3 << 5)
114 
115 /**************************************************************************/
116 /* Debug Unit */
117 /**************************************************************************/
118 #define DBGU_BASE 0xFFFFF200
119 #define DBGU_REG(_x_) *(vulong *)(DBGU_BASE + _x_)
120 
121 /* Register Offsets */
122 #define DBGU_CR 0x00 /* Control Register */
123 #define DBGU_MR 0x04 /* Mode Register */
124 #define DBGU_IER 0x08 /* Interrupt Enable Register */
125 #define DBGU_IDR 0x0C /* Interrupt Disable Register */
126 #define DBGU_IMR 0x10 /* Interrupt Mask Register */
127 #define DBGU_CSR 0x14 /* Channel Status Register */
128 #define DBGU_RHR 0x18 /* Receiver Holding Register */
129 #define DBGU_THR 0x1C /* Transmitter Holding Register */
130 #define DBGU_BRGR 0x20 /* Baud Rate Generator Register */
131 #define DBGU_C1R 0x40 /* Chip ID1 Register */
132 #define DBGU_C2R 0x44 /* Chip ID2 Register */
133 #define DBGU_FNTR 0x48 /* Force NTRST Register */
134 
135 /**************************************************************************/
136 /* USART 0-3 */
137 /**************************************************************************/
138 #define USART0_BASE 0xFFFC0000
139 #define USART1_BASE 0xFFFC4000
140 #define USART2_BASE 0xFFFC8000
141 #define USART3_BASE 0xFFFCC000
142 /*
143  * WARNING: The USART3_BASE at the AT91RM9200 Manual is wrong!!!
144  * Manual revision: Rev. 1768H-ATARM–16-Jun-09
145  * USART3_BASE is NOT 0xFFECC000
146  */
147 
148 /****************/
149 /* System Timer */
150 /****************/
151 #define ST_BASE 0xFFFFFD00
152 #define ST_REG(_x_) *(vulong *)(ST_BASE + _x_)
153 
154 /* Register Offsets */
155 #define ST_CR 0x00 /* Control Register */
156 #define ST_PIMR 0x04 /* Period Interval Mode Register */
157 #define ST_WDMR 0x08 /* Watchdog Mode Register */
158 #define ST_RTMR 0x0C /* Real-time Mode Register */
159 #define ST_SR 0x10 /* Status Register */
160 #define ST_IER 0x14 /* Interrupt Enable Register */
161 #define ST_IDR 0x18 /* Interrupt Disable Register */
162 #define ST_IMR 0x1C /* Interrupt Mask Register */
163 #define ST_RTAR 0x20 /* Real-time Alarm Register */
164 #define ST_CRTR 0x24 /* Current Real-time Register */
165 
166 /* Bit Defines */
167 /* ST_CR - Control Register */
168 #define ST_CR_WDRST BIT0 /* write 1 to reload WD counter */
169 
170 /* ST_PIMR - Period Interval Mode Register */
171 #define ST_PIMR_PIV_MASK 0x0000ffff
172 
173 /* ST_WDMR - Watchdog Mode Register */
174 #define ST_WDMR_EXTEN BIT17 /* WDOVF is not implemented on AT91RM9200 */
175 #define ST_WDMR_RSTEN BIT16 /* 1 = reset the AT91RM9200 when WD overflows */
176 #define ST_WDMR_WDV_MASK 0x0000ffff /* WD counter is in the lower 16-bits */
177 
178 /* ST_RTMR - Real-time Mode Register */
179 #define ST_RTMR_RTPRES_MASK 0x0000ffff /* Real-Time Prescaler */
180 
181 /* ST_SR - Status Register - Read Only */
182 /* ST_IER - Interrupt Enable Register - Write Only */
183 /* ST_IDR - Interrupt Disable Register - Write Only */
184 /* ST_IMR - Interrupt Mask Register - Read Only */
185 #define ST_SR_ALMS BIT3
186 #define ST_SR_RTTINC BIT2
187 #define ST_SR_WDOVF BIT1
188 #define ST_SR_PITS BIT0
189 
190 /* ST_RTAR - Real-time Alarm Register */
191 #define ST_RTAR_ALMV_MASK 0x000fffff
192 
193 /* ST_CRTR - Current Real-time Register */
194 #define ST_CRTR_CRTV_MASK 0x000fffff
195 
196 
197 /**************************************************************************
198  * Peripheral Data Control (DMA)
199  * Note that each of the following peripherals has it's own
200  * set of these registers starting at offset 0x100 from it's
201  * base address: DBGU, SPI, USART and SSC
202  * To access the DMA for a peripheral, use the macro for that
203  * peripheral but with these register offsets
204  **************************************************************************/
205 /* Register Offsets */
206 #define PDC_RPR 0x100 /* Receive Pointer Register */
207 #define PDC_RCR 0x104 /* Receive Counter Register */
208 #define PDC_TPR 0x108 /* Transmit Pointer Register */
209 #define PDC_TCR 0x10c /* Transmit Counter Register */
210 #define PDC_RNPR 0x110 /* Receive Next Pointer Register */
211 #define PDC_RNCR 0x114 /* Receive Next Counter Register */
212 #define PDC_TNPR 0x118 /* Transmit Next Pointer Register */
213 #define PDC_TNCR 0x11c /* Transmit Next Counter Register */
214 #define PDC_PTCR 0x120 /* PDC Transfer Control Register */
215 #define PDC_PTSR 0x124 /* PDC Transfer Status Register */
216 
217 /**************************************************************************
218  * Parallel I/O Unit
219  * There are four PIO blocks - A, B, C and D. They all have the
220  * same register set, but different base addresses
221  **************************************************************************/
222 /* Port A */
223 #define PIOA_BASE 0xFFFFF400
224 #define PIOA_REG(_x_) *(vulong *)(PIOA_BASE + _x_)
225 
226 /* Port B */
227 #define PIOB_BASE 0xFFFFF600
228 #define PIOB_REG(_x_) *(vulong *)(PIOB_BASE + _x_)
229 
230 /* Port C */
231 #define PIOC_BASE 0xFFFFF800
232 #define PIOC_REG(_x_) *(vulong *)(PIOC_BASE + _x_)
233 
234 /* Port D */
235 #define PIOD_BASE 0xFFFFFA00
236 #define PIOD_REG(_x_) *(vulong *)(PIOD_BASE + _x_)
237 
238 /**************************************************************************
239  * Power Management and Clock Control
240  *************************************************************************/
241 #define PMC_BASE 0xFFFFFC00
242 #define PMC_REG(_x_) *(vulong *)(PMC_BASE + _x_)
243 
244 /**************************************************************************
245  * MAC Unit
246  *************************************************************************/
247 #define EMAC_BASE 0xFFFBC000
248 #define EMAC_REG(_x_) *(vulong *)(EMAC_BASE + _x_)
249 
250 /**************************************************************************
251  * Timer/Counter Unit
252  **************************************************************************/
253 #define TC_BASE 0xFFFA0000
254 #define TC_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_)
255 #define TC_TC0_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_)
256 #define TC_TC1_REG(_x_) *(vulong *)(TC_BASE + 0x40 + _x_)
257 #define TC_TC2_REG(_x_) *(vulong *)(TC_BASE + 0x80 + _x_)
258 
259 /* Offsets from TC_TC?_REG */
260 #define TC_CCR 0x00 /* Channel Control Register */
261 #define TC_CMR 0x04 /* Channel Mode Register */
262 #define TC_CV 0x10 /* Counter Value */
263 #define TC_RA 0x14 /* Register A */
264 #define TC_RB 0x18 /* Register B */
265 #define TC_RC 0x1C /* Register C */
266 #define TC_SR 0x20 /* Status Register */
267 #define TC_IER 0x24 /* Interrupt Enable Register */
268 #define TC_IDR 0x28 /* Interrupt Disable Register */
269 #define TC_IMR 0x2C /* Interrupt Mask Register */
270 
271 /* Offsets from TC_BASE */
272 #define TC_BCR 0xc0 /* Channel Control Register */
273 #define TC_BMR 0xc4 /* Channel Control Register */
274 
275 /* Block control register */
276 #define TC_BCR_SYNC BIT1 /* Set to syncronize channels */
277 
278 /* Block mode register */
279 #define TC_BMR_TC0(_x_) ((_x_ & 0x3) << 0) /* TC0 clock source */
280 #define TC_BMR_TC1(_x_) ((_x_ & 0x3) << 2) /* TC1 clock source */
281 #define TC_BMR_TC2(_x_) ((_x_ & 0x3) << 4) /* TC2 clock source */
282 
283 /* Channel Control register */
284 #define TC_CCR_CLKEN BIT0 /* Enable clock */
285 #define TC_CCR_CLKDIS BIT1 /* Disable clock */
286 #define TC_CCR_SWTRG BIT2 /* Software trigger command */
287 
288 /* Channel mode register */
289 #define TC_CMR_TCCLKS(_x_) ((_x_ & 0x7) << 0) /* Clock source */
290 #define TC_CMR_CLKI BIT3 /* Clock invert */
291 #define TC_BURST(_x_) ((_x_ & 0x3 << 4) /* Burst signal selection */
292 #define TC_WAVE BIT15 /* 0 for catpure, 1 for wave */
293 
294 /* Channel mode register - capture mode (TC_WAVE = 0) */
295 #define TC_CMR_LDBSTOP BIT6 /* Set to stop clock when RB loads */
296 #define TC_CMR_LDBDIS BIT7 /* Set to disable clock when RB loads */
297 #define TC_CMR_ETRGEDG(_x_) ((_x_ & 0x3) << 8) /* Select edge triggering mode */
298 #define TC_CMR_ABETRG BIT10 /* Select ext trigger source */
299 #define TC_CMR_CPCTRG BIT14 /* RC Compare trigger enable */
300 #define TC_CMR_LDRA(_x_) ((_x_ & 0x3) << 16) /* RA loading selection */
301 #define TC_CMR_LDRB(_x_) ((_x_ & 0x3) << 18) /* RB loading selection */
302 
303 /* Channel mode register - wave mode (TC_WAVE = 1) */
304 #define TC_CMR_CPCSTOP BIT6 /* Clock stopped w/ RC compare */
305 #define TC_CMR_CPCDIS BIT7 /* Clock disabled w/ RC compare */
306 #define TC_CMR_EEVTEDG(_x_) ((_x_ & 0x3) << 8) /* Ext event edge selection */
307 #define TC_CMR_EEVT(_x_) ((_x_ & 0x3) << 10) /* Ext event selection */
308 #define TC_CMR_ENETRG BIT12 /* Ext event trigger enable */
309 #define TC_CMR_WAVESEL(_x_) ((_x_ & 0x3) << 13) /* Waveform selection */
310 #define TC_CMR_ACPA(_x_) ((_x_ & 0x3) << 16) /* RA compare effect on TIOA */
311 #define TC_CMR_ACPC(_x_) ((_x_ & 0x3) << 18) /* RC compare effect on TIOA */
312 #define TC_CMR_AEEVT(_x_) ((_x_ & 0x3) << 20) /* Ext event effect on TIOA */
313 #define TC_CMR_ASWTRG(_x_) ((_x_ & 0x3) << 22) /* SW trigger effect on TIOA */
314 #define TC_CMR_BCPB(_x_) ((_x_ & 0x3) << 24) /* RB compare effect on TIOB */
315 #define TC_CMR_BCPC(_x_) ((_x_ & 0x3) << 26) /* RC compare effect on TIOB */
316 #define TC_CMR_BEEVT(_x_) ((_x_ & 0x3) << 28) /* Ext event effect on TIOB */
317 #define TC_CMR_BSWTRG(_x_) ((_x_ & 0x3) << 30) /* SW trigger effect on TIOB */
318 
319 /* Counter value */
320 #define TC_CV_MASK 0xffff /* Timer counter mask */
321 
322 /* Status, Interrupt enable, Interrupt disable, and Interrupt mask registers */
323 #define TC_SR_COVFS BIT0 /* Counter overflow status */
324 #define TC_SR_LOVRS BIT1 /* Load overrun status */
325 #define TC_SR_CPAS BIT2 /* RA compare status */
326 #define TC_SR_CPBS BIT3 /* RB compare status */
327 #define TC_SR_CPCS BIT4 /* RC compare status */
328 #define TC_SR_LDRAS BIT5 /* RA loading status */
329 #define TC_SR_LDRBS BIT6 /* RB loading status */
330 #define TC_SR_ETRGS BIT7 /* External trigger status */
331 #define TC_SR_CLKSTA BIT16 /* Clock enabling status */
332 #define TC_SR_MTIOA BIT17 /* TIOA Mirror */
333 #define TC_SR_MTIOB BIT18 /* TIOB Mirror */
334 
335 /***************************************************************************
336  * External Bus Interface Unit
337  **************************************************************************/
338 #define EBI_BASE 0xFFFFFF60
339 #define EBI_REG(_x_) *(vulong *)(EBI_BASE + _x_)
340 
341 /***************************************************************************
342  * Static Memory Interface Unit
343  ***************************************************************************/
344 #define SMC_REG(_x_) *(vulong *)(EBI_BASE + 0x10 + _x_)
345 
346 /**************************************************************************
347  * SDRAM Memory Interface Unit
348  **************************************************************************/
349 #define SDRC_REG(_x_) *(vulong *)(EBI_BASE + 0x30 + _x_)
350 
351 #endif /* __AT91RM9200_H__ */
352 
bits.h
Contains Defined Bits.
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