RTEMS  5.0.0
armv7m.h
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1 
7 /*
8  * Copyright (c) 2011-2014 Sebastian Huber. All rights reserved.
9  *
10  * embedded brains GmbH
11  * Obere Lagerstr. 30
12  * 82178 Puchheim
13  * Germany
14  * <rtems@embedded-brains.de>
15  *
16  * The license and distribution terms for this file may be
17  * found in the file LICENSE in this distribution or at
18  * http://www.rtems.org/license/LICENSE.
19  */
20 
21 #ifndef RTEMS_SCORE_ARMV7M_H
22 #define RTEMS_SCORE_ARMV7M_H
23 
24 #include <rtems/score/cpu.h>
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif /* __cplusplus */
29 
30 #ifdef ARM_MULTILIB_ARCH_V7M
31 
32 /* Coprocessor Access Control Register, CPACR */
33 #define ARMV7M_CPACR 0xe000ed88
34 
35 #ifndef ASM
36 
37 typedef struct {
38  uint32_t reserved_0;
39  uint32_t ictr;
40  uint32_t actlr;
41  uint32_t reserved_1;
42 } ARMV7M_ICTAC;
43 
44 typedef void (*ARMV7M_Exception_handler)(void);
45 
46 typedef struct {
47  uint32_t register_r0;
48  uint32_t register_r1;
49  uint32_t register_r2;
50  uint32_t register_r3;
51  uint32_t register_r12;
52  void *register_lr;
53  void *register_pc;
54  uint32_t register_xpsr;
55 #ifdef ARM_MULTILIB_VFP
56  uint32_t register_s0;
57  uint32_t register_s1;
58  uint32_t register_s2;
59  uint32_t register_s3;
60  uint32_t register_s4;
61  uint32_t register_s5;
62  uint32_t register_s6;
63  uint32_t register_s7;
64  uint32_t register_s8;
65  uint32_t register_s9;
66  uint32_t register_s10;
67  uint32_t register_s11;
68  uint32_t register_s12;
69  uint32_t register_s13;
70  uint32_t register_s14;
71  uint32_t register_s15;
72  uint32_t register_fpscr;
73  uint32_t reserved;
74 #endif
75 } ARMV7M_Exception_frame;
76 
77 typedef struct {
78  uint32_t comp;
79  uint32_t mask;
80  uint32_t function;
81  uint32_t reserved;
82 } ARMV7M_DWT_comparator;
83 
84 typedef struct {
85 #define ARMV7M_DWT_CTRL_NOCYCCNT (1U << 25)
86 #define ARMV7M_DWT_CTRL_CYCCNTENA (1U << 0)
87  uint32_t ctrl;
88  uint32_t cyccnt;
89  uint32_t cpicnt;
90  uint32_t exccnt;
91  uint32_t sleepcnt;
92  uint32_t lsucnt;
93  uint32_t foldcnt;
94  uint32_t pcsr;
95  ARMV7M_DWT_comparator comparator[249];
96 #define ARMV7M_DWT_LAR_UNLOCK_MAGIC 0xc5acce55U
97  uint32_t lar;
98  uint32_t lsr;
99 } ARMV7M_DWT;
100 
101 typedef struct {
102  uint32_t cpuid;
103 
104 #define ARMV7M_SCB_ICSR_NMIPENDSET (1U << 31)
105 #define ARMV7M_SCB_ICSR_PENDSVSET (1U << 28)
106 #define ARMV7M_SCB_ICSR_PENDSVCLR (1U << 27)
107 #define ARMV7M_SCB_ICSR_PENDSTSET (1U << 26)
108 #define ARMV7M_SCB_ICSR_PENDSTCLR (1U << 25)
109 #define ARMV7M_SCB_ICSR_ISRPREEMPT (1U << 23)
110 #define ARMV7M_SCB_ICSR_ISRPENDING (1U << 22)
111 #define ARMV7M_SCB_ICSR_VECTPENDING_GET(reg) (((reg) >> 12) & 0x1ffU)
112 #define ARMV7M_SCB_ICSR_RETTOBASE (1U << 11)
113 #define ARMV7M_SCB_ICSR_VECTACTIVE_GET(reg) ((reg) & 0x1ffU)
114  uint32_t icsr;
115 
116  ARMV7M_Exception_handler *vtor;
117 
118 #define ARMV7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
119 #define ARMV7M_SCB_AIRCR_ENDIANESS (1U << 15)
120 #define ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT 8
121 #define ARMV7M_SCB_AIRCR_PRIGROUP_MASK \
122  ((0x7U) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT)
123 #define ARMV7M_SCB_AIRCR_PRIGROUP(val) \
124  (((val) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK)
125 #define ARMV7M_SCB_AIRCR_PRIGROUP_GET(reg) \
126  (((val) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK) >> ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT)
127 #define ARMV7M_SCB_AIRCR_PRIGROUP_SET(reg, val) \
128  (((reg) & ~ARMV7M_SCB_AIRCR_PRIGROUP_MASK) | ARMV7M_SCB_AIRCR_PRIGROUP(val))
129 #define ARMV7M_SCB_AIRCR_SYSRESETREQ (1U << 2)
130 #define ARMV7M_SCB_AIRCR_VECTCLRACTIVE (1U << 1)
131 #define ARMV7M_SCB_AIRCR_VECTRESET (1U << 0)
132  uint32_t aircr;
133 
134  uint32_t scr;
135  uint32_t ccr;
136  uint8_t shpr [12];
137 
138 #define ARMV7M_SCB_SHCSR_USGFAULTENA (1U << 18)
139 #define ARMV7M_SCB_SHCSR_BUSFAULTENA (1U << 17)
140 #define ARMV7M_SCB_SHCSR_MEMFAULTENA (1U << 16)
141  uint32_t shcsr;
142 
143  uint32_t cfsr;
144  uint32_t hfsr;
145  uint32_t dfsr;
146  uint32_t mmfar;
147  uint32_t bfar;
148  uint32_t afsr;
149  uint32_t reserved_e000ed40[18];
150  uint32_t cpacr;
151  uint32_t reserved_e000ed8c[106];
152  uint32_t fpccr;
153  uint32_t fpcar;
154  uint32_t fpdscr;
155  uint32_t mvfr0;
156  uint32_t mvfr1;
157 } ARMV7M_SCB;
158 
159 typedef struct {
160 #define ARMV7M_SYSTICK_CSR_COUNTFLAG (1U << 16)
161 #define ARMV7M_SYSTICK_CSR_CLKSOURCE (1U << 2)
162 #define ARMV7M_SYSTICK_CSR_TICKINT (1U << 1)
163 #define ARMV7M_SYSTICK_CSR_ENABLE (1U << 0)
164  uint32_t csr;
165 
166  uint32_t rvr;
167  uint32_t cvr;
168 
169 #define ARMV7M_SYSTICK_CALIB_NOREF (1U << 31)
170 #define ARMV7M_SYSTICK_CALIB_SKEW (1U << 30)
171 #define ARMV7M_SYSTICK_CALIB_TENMS_GET(reg) ((reg) & 0xffffffU)
172  uint32_t calib;
173 } ARMV7M_Systick;
174 
175 typedef struct {
176  uint32_t iser [8];
177  uint32_t reserved_0 [24];
178  uint32_t icer [8];
179  uint32_t reserved_1 [24];
180  uint32_t ispr [8];
181  uint32_t reserved_2 [24];
182  uint32_t icpr [8];
183  uint32_t reserved_3 [24];
184  uint32_t iabr [8];
185  uint32_t reserved_4 [56];
186  uint8_t ipr [240];
187  uint32_t reserved_5 [644];
188  uint32_t stir;
189 } ARMV7M_NVIC;
190 
191 typedef struct {
192 #define ARMV7M_MPU_TYPE_IREGION_GET(reg) (((reg) >> 16) & 0xffU)
193 #define ARMV7M_MPU_TYPE_DREGION_GET(reg) (((reg) >> 8) & 0xffU)
194 #define ARMV7M_MPU_TYPE_SEPARATE (1U << 0)
195  uint32_t type;
196 
197 #define ARMV7M_MPU_CTRL_PRIVDEFENA (1U << 2)
198 #define ARMV7M_MPU_CTRL_HFNMIENA (1U << 1)
199 #define ARMV7M_MPU_CTRL_ENABLE (1U << 0)
200  uint32_t ctrl;
201 
202  uint32_t rnr;
203 
204 #define ARMV7M_MPU_RBAR_ADDR_SHIFT 5
205 #define ARMV7M_MPU_RBAR_ADDR_MASK \
206  ((0x7ffffffU) << ARMV7M_MPU_RBAR_ADDR_SHIFT)
207 #define ARMV7M_MPU_RBAR_ADDR(val) \
208  (((val) << ARMV7M_MPU_RBAR_ADDR_SHIFT) & ARMV7M_MPU_RBAR_ADDR_MASK)
209 #define ARMV7M_MPU_RBAR_ADDR_GET(reg) \
210  (((val) & ARMV7M_MPU_RBAR_ADDR_MASK) >> ARMV7M_MPU_RBAR_ADDR_SHIFT)
211 #define ARMV7M_MPU_RBAR_ADDR_SET(reg, val) \
212  (((reg) & ~ARMV7M_MPU_RBAR_ADDR_MASK) | ARMV7M_MPU_RBAR_ADDR(val))
213 #define ARMV7M_MPU_RBAR_VALID (1U << 4)
214 #define ARMV7M_MPU_RBAR_REGION_SHIFT 0
215 #define ARMV7M_MPU_RBAR_REGION_MASK \
216  ((0xfU) << ARMV7M_MPU_RBAR_REGION_SHIFT)
217 #define ARMV7M_MPU_RBAR_REGION(val) \
218  (((val) << ARMV7M_MPU_RBAR_REGION_SHIFT) & ARMV7M_MPU_RBAR_REGION_MASK)
219 #define ARMV7M_MPU_RBAR_REGION_GET(reg) \
220  (((val) & ARMV7M_MPU_RBAR_REGION_MASK) >> ARMV7M_MPU_RBAR_REGION_SHIFT)
221 #define ARMV7M_MPU_RBAR_REGION_SET(reg, val) \
222  (((reg) & ~ARMV7M_MPU_RBAR_REGION_MASK) | ARMV7M_MPU_RBAR_REGION(val))
223  uint32_t rbar;
224 
225 #define ARMV7M_MPU_RASR_XN (1U << 28)
226 #define ARMV7M_MPU_RASR_AP_SHIFT 24
227 #define ARMV7M_MPU_RASR_AP_MASK \
228  ((0x7U) << ARMV7M_MPU_RASR_AP_SHIFT)
229 #define ARMV7M_MPU_RASR_AP(val) \
230  (((val) << ARMV7M_MPU_RASR_AP_SHIFT) & ARMV7M_MPU_RASR_AP_MASK)
231 #define ARMV7M_MPU_RASR_AP_GET(reg) \
232  (((val) & ARMV7M_MPU_RASR_AP_MASK) >> ARMV7M_MPU_RASR_AP_SHIFT)
233 #define ARMV7M_MPU_RASR_AP_SET(reg, val) \
234  (((reg) & ~ARMV7M_MPU_RASR_AP_MASK) | ARMV7M_MPU_RASR_AP(val))
235 #define ARMV7M_MPU_RASR_TEX_SHIFT 19
236 #define ARMV7M_MPU_RASR_TEX_MASK \
237  ((0x7U) << ARMV7M_MPU_RASR_TEX_SHIFT)
238 #define ARMV7M_MPU_RASR_TEX(val) \
239  (((val) << ARMV7M_MPU_RASR_TEX_SHIFT) & ARMV7M_MPU_RASR_TEX_MASK)
240 #define ARMV7M_MPU_RASR_TEX_GET(reg) \
241  (((val) & ARMV7M_MPU_RASR_TEX_MASK) >> ARMV7M_MPU_RASR_TEX_SHIFT)
242 #define ARMV7M_MPU_RASR_TEX_SET(reg, val) \
243  (((reg) & ~ARMV7M_MPU_RASR_TEX_MASK) | ARMV7M_MPU_RASR_TEX(val))
244 #define ARMV7M_MPU_RASR_S (1U << 18)
245 #define ARMV7M_MPU_RASR_C (1U << 17)
246 #define ARMV7M_MPU_RASR_B (1U << 16)
247 #define ARMV7M_MPU_RASR_SRD_SHIFT 8
248 #define ARMV7M_MPU_RASR_SRD_MASK \
249  ((0xffU) << ARMV7M_MPU_RASR_SRD_SHIFT)
250 #define ARMV7M_MPU_RASR_SRD(val) \
251  (((val) << ARMV7M_MPU_RASR_SRD_SHIFT) & ARMV7M_MPU_RASR_SRD_MASK)
252 #define ARMV7M_MPU_RASR_SRD_GET(reg) \
253  (((val) & ARMV7M_MPU_RASR_SRD_MASK) >> ARMV7M_MPU_RASR_SRD_SHIFT)
254 #define ARMV7M_MPU_RASR_SRD_SET(reg, val) \
255  (((reg) & ~ARMV7M_MPU_RASR_SRD_MASK) | ARMV7M_MPU_RASR_SRD(val))
256 #define ARMV7M_MPU_RASR_SIZE_SHIFT 1
257 #define ARMV7M_MPU_RASR_SIZE_MASK \
258  ((0x1fU) << ARMV7M_MPU_RASR_SIZE_SHIFT)
259 #define ARMV7M_MPU_RASR_SIZE(val) \
260  (((val) << ARMV7M_MPU_RASR_SIZE_SHIFT) & ARMV7M_MPU_RASR_SIZE_MASK)
261 #define ARMV7M_MPU_RASR_SIZE_GET(reg) \
262  (((val) & ARMV7M_MPU_RASR_SIZE_MASK) >> ARMV7M_MPU_RASR_SIZE_SHIFT)
263 #define ARMV7M_MPU_RASR_SIZE_SET(reg, val) \
264  (((reg) & ~ARMV7M_MPU_RASR_SIZE_MASK) | ARMV7M_MPU_RASR_SIZE(val))
265 #define ARMV7M_MPU_RASR_ENABLE (1U << 0)
266  uint32_t rasr;
267 
268  uint32_t rbar_a1;
269  uint32_t rasr_a1;
270  uint32_t rbar_a2;
271  uint32_t rasr_a2;
272  uint32_t rbar_a3;
273  uint32_t rasr_a3;
274 } ARMV7M_MPU;
275 
276 typedef enum {
277  ARMV7M_MPU_AP_PRIV_NO_USER_NO,
278  ARMV7M_MPU_AP_PRIV_RW_USER_NO,
279  ARMV7M_MPU_AP_PRIV_RW_USER_RO,
280  ARMV7M_MPU_AP_PRIV_RW_USER_RW,
281  ARMV7M_MPU_AP_PRIV_RO_USER_NO = 0x5,
282  ARMV7M_MPU_AP_PRIV_RO_USER_RO,
283 } ARMV7M_MPU_Access_permissions;
284 
285 typedef enum {
286  ARMV7M_MPU_ATTR_R = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO)
287  | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN,
288  ARMV7M_MPU_ATTR_RW = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
289  | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN | ARMV7M_MPU_RASR_B,
290  ARMV7M_MPU_ATTR_RWX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
291  | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B,
292  ARMV7M_MPU_ATTR_X = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_NO_USER_NO)
293  | ARMV7M_MPU_RASR_C,
294  ARMV7M_MPU_ATTR_RX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO)
295  | ARMV7M_MPU_RASR_C,
296  ARMV7M_MPU_ATTR_IO = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
297  | ARMV7M_MPU_RASR_XN,
298 } ARMV7M_MPU_Attributes;
299 
300 typedef enum {
301  ARMV7M_MPU_SIZE_32_B = 0x4,
302  ARMV7M_MPU_SIZE_64_B,
303  ARMV7M_MPU_SIZE_128_B,
304  ARMV7M_MPU_SIZE_256_B,
305  ARMV7M_MPU_SIZE_512_B,
306  ARMV7M_MPU_SIZE_1_KB,
307  ARMV7M_MPU_SIZE_2_KB,
308  ARMV7M_MPU_SIZE_4_KB,
309  ARMV7M_MPU_SIZE_8_KB,
310  ARMV7M_MPU_SIZE_16_KB,
311  ARMV7M_MPU_SIZE_32_KB,
312  ARMV7M_MPU_SIZE_64_KB,
313  ARMV7M_MPU_SIZE_128_KB,
314  ARMV7M_MPU_SIZE_256_KB,
315  ARMV7M_MPU_SIZE_512_KB,
316  ARMV7M_MPU_SIZE_1_MB,
317  ARMV7M_MPU_SIZE_2_MB,
318  ARMV7M_MPU_SIZE_4_MB,
319  ARMV7M_MPU_SIZE_8_MB,
320  ARMV7M_MPU_SIZE_16_MB,
321  ARMV7M_MPU_SIZE_32_MB,
322  ARMV7M_MPU_SIZE_64_MB,
323  ARMV7M_MPU_SIZE_128_MB,
324  ARMV7M_MPU_SIZE_256_MB,
325  ARMV7M_MPU_SIZE_512_MB,
326  ARMV7M_MPU_SIZE_1_GB,
327  ARMV7M_MPU_SIZE_2_GB,
328  ARMV7M_MPU_SIZE_4_GB
329 } ARMV7M_MPU_Size;
330 
331 typedef struct {
332  uint32_t rbar;
333  uint32_t rasr;
334 } ARMV7M_MPU_Region;
335 
336 #define ARMV7M_MPU_REGION_INITIALIZER(idx, addr, size, attr) \
337  { \
338  ((addr) & ARMV7M_MPU_RBAR_ADDR_MASK) \
339  | ARMV7M_MPU_RBAR_VALID \
340  | ARMV7M_MPU_RBAR_REGION(idx), \
341  ARMV7M_MPU_RASR_SIZE(size) | (attr) | ARMV7M_MPU_RASR_ENABLE \
342  }
343 
344 #define ARMV7M_MPU_REGION_DISABLED_INITIALIZER(idx) \
345  { \
346  ARMV7M_MPU_RBAR_VALID | ARMV7M_MPU_RBAR_REGION(idx), \
347  0 \
348  }
349 
350 typedef struct {
351  uint32_t dhcsr;
352  uint32_t dcrsr;
353  uint32_t dcrdr;
354 #define ARMV7M_DEBUG_DEMCR_VC_CORERESET (1U << 0)
355 #define ARMV7M_DEBUG_DEMCR_VC_MMERR (1U << 4)
356 #define ARMV7M_DEBUG_DEMCR_VC_NOCPERR (1U << 5)
357 #define ARMV7M_DEBUG_DEMCR_VC_CHKERR (1U << 6)
358 #define ARMV7M_DEBUG_DEMCR_VC_STATERR (1U << 7)
359 #define ARMV7M_DEBUG_DEMCR_VC_BUSERR (1U << 8)
360 #define ARMV7M_DEBUG_DEMCR_VC_INTERR (1U << 9)
361 #define ARMV7M_DEBUG_DEMCR_VC_HARDERR (1U << 10)
362 #define ARMV7M_DEBUG_DEMCR_MON_EN (1U << 16)
363 #define ARMV7M_DEBUG_DEMCR_MON_PEND (1U << 17)
364 #define ARMV7M_DEBUG_DEMCR_MON_STEP (1U << 18)
365 #define ARMV7M_DEBUG_DEMCR_MON_REQ (1U << 19)
366 #define ARMV7M_DEBUG_DEMCR_TRCENA (1U << 24)
367  uint32_t demcr;
368 } ARMV7M_DEBUG;
369 
370 #define ARMV7M_DWT_BASE 0xe0001000
371 #define ARMV7M_SCS_BASE 0xe000e000
372 #define ARMV7M_ICTAC_BASE (ARMV7M_SCS_BASE + 0x0)
373 #define ARMV7M_SYSTICK_BASE (ARMV7M_SCS_BASE + 0x10)
374 #define ARMV7M_NVIC_BASE (ARMV7M_SCS_BASE + 0x100)
375 #define ARMV7M_SCB_BASE (ARMV7M_SCS_BASE + 0xd00)
376 #define ARMV7M_MPU_BASE (ARMV7M_SCS_BASE + 0xd90)
377 #define ARMV7M_DEBUG_BASE (ARMV7M_SCS_BASE + 0xdf0)
378 
379 #define _ARMV7M_DWT \
380  ((volatile ARMV7M_DWT *) ARMV7M_DWT_BASE)
381 #define _ARMV7M_ICTAC \
382  ((volatile ARMV7M_ICTAC *) ARMV7M_ICTAC_BASE)
383 #define _ARMV7M_SCB \
384  ((volatile ARMV7M_SCB *) ARMV7M_SCB_BASE)
385 #define _ARMV7M_Systick \
386  ((volatile ARMV7M_Systick *) ARMV7M_SYSTICK_BASE)
387 #define _ARMV7M_NVIC \
388  ((volatile ARMV7M_NVIC *) ARMV7M_NVIC_BASE)
389 #define _ARMV7M_MPU \
390  ((volatile ARMV7M_MPU *) ARMV7M_MPU_BASE)
391 #define _ARMV7M_DEBUG \
392  ((volatile ARMV7M_DEBUG *) ARMV7M_DEBUG_BASE)
393 
394 #define ARMV7M_VECTOR_MSP 0
395 #define ARMV7M_VECTOR_RESET 1
396 #define ARMV7M_VECTOR_NMI 2
397 #define ARMV7M_VECTOR_HARD_FAULT 3
398 #define ARMV7M_VECTOR_MEM_MANAGE 4
399 #define ARMV7M_VECTOR_BUS_FAULT 5
400 #define ARMV7M_VECTOR_USAGE_FAULT 6
401 #define ARMV7M_VECTOR_SVC 11
402 #define ARMV7M_VECTOR_DEBUG_MONITOR 12
403 #define ARMV7M_VECTOR_PENDSV 14
404 #define ARMV7M_VECTOR_SYSTICK 15
405 #define ARMV7M_VECTOR_IRQ(n) ((n) + 16)
406 #define ARMV7M_IRQ_OF_VECTOR(n) ((n) - 16)
407 
408 #define ARMV7M_EXCEPTION_PRIORITY_LOWEST 255
409 
410 static inline bool _ARMV7M_Is_vector_an_irq( int vector )
411 {
412  /* External (i.e. non-system) IRQs start after the SysTick vector. */
413  return vector > ARMV7M_VECTOR_SYSTICK;
414 }
415 
416 static inline uint32_t _ARMV7M_Get_basepri(void)
417 {
418  uint32_t val;
419  __asm__ volatile ("mrs %[val], basepri\n" : [val] "=&r" (val));
420  return val;
421 }
422 
423 static inline void _ARMV7M_Set_basepri(uint32_t val)
424 {
425  __asm__ volatile ("msr basepri, %[val]\n" : : [val] "r" (val));
426 }
427 
428 static inline uint32_t _ARMV7M_Get_primask(void)
429 {
430  uint32_t val;
431  __asm__ volatile ("mrs %[val], primask\n" : [val] "=&r" (val));
432  return val;
433 }
434 
435 static inline void _ARMV7M_Set_primask(uint32_t val)
436 {
437  __asm__ volatile ("msr primask, %[val]\n" : : [val] "r" (val));
438 }
439 
440 static inline uint32_t _ARMV7M_Get_faultmask(void)
441 {
442  uint32_t val;
443  __asm__ volatile ("mrs %[val], faultmask\n" : [val] "=&r" (val));
444  return val;
445 }
446 
447 static inline void _ARMV7M_Set_faultmask(uint32_t val)
448 {
449  __asm__ volatile ("msr faultmask, %[val]\n" : : [val] "r" (val));
450 }
451 
452 static inline uint32_t _ARMV7M_Get_control(void)
453 {
454  uint32_t val;
455  __asm__ volatile ("mrs %[val], control\n" : [val] "=&r" (val));
456  return val;
457 }
458 
459 static inline void _ARMV7M_Set_control(uint32_t val)
460 {
461  __asm__ volatile ("msr control, %[val]\n" : : [val] "r" (val));
462 }
463 
464 static inline uint32_t _ARMV7M_Get_MSP(void)
465 {
466  uint32_t val;
467  __asm__ volatile ("mrs %[val], msp\n" : [val] "=&r" (val));
468  return val;
469 }
470 
471 static inline void _ARMV7M_Set_MSP(uint32_t val)
472 {
473  __asm__ volatile ("msr msp, %[val]\n" : : [val] "r" (val));
474 }
475 
476 static inline uint32_t _ARMV7M_Get_PSP(void)
477 {
478  uint32_t val;
479  __asm__ volatile ("mrs %[val], psp\n" : [val] "=&r" (val));
480  return val;
481 }
482 
483 static inline void _ARMV7M_Set_PSP(uint32_t val)
484 {
485  __asm__ volatile ("msr psp, %[val]\n" : : [val] "r" (val));
486 }
487 
488 static inline uint32_t _ARMV7M_Get_XPSR(void)
489 {
490  uint32_t val;
491  __asm__ volatile ("mrs %[val], xpsr\n" : [val] "=&r" (val));
492  return val;
493 }
494 
495 static inline bool _ARMV7M_NVIC_Is_enabled( int irq )
496 {
497  int index = irq >> 5;
498  uint32_t bit = 1U << (irq & 0x1f);
499 
500  return (_ARMV7M_NVIC->iser [index] & bit) != 0;
501 }
502 
503 static inline void _ARMV7M_NVIC_Set_enable( int irq )
504 {
505  int index = irq >> 5;
506  uint32_t bit = 1U << (irq & 0x1f);
507 
508  _ARMV7M_NVIC->iser [index] = bit;
509 }
510 
511 static inline void _ARMV7M_NVIC_Clear_enable( int irq )
512 {
513  int index = irq >> 5;
514  uint32_t bit = 1U << (irq & 0x1f);
515 
516  _ARMV7M_NVIC->icer [index] = bit;
517 }
518 
519 static inline bool _ARMV7M_NVIC_Is_pending( int irq )
520 {
521  int index = irq >> 5;
522  uint32_t bit = 1U << (irq & 0x1f);
523 
524  return (_ARMV7M_NVIC->ispr [index] & bit) != 0;
525 }
526 
527 static inline void _ARMV7M_NVIC_Set_pending( int irq )
528 {
529  int index = irq >> 5;
530  uint32_t bit = 1U << (irq & 0x1f);
531 
532  _ARMV7M_NVIC->ispr [index] = bit;
533 }
534 
535 static inline void _ARMV7M_NVIC_Clear_pending( int irq )
536 {
537  int index = irq >> 5;
538  uint32_t bit = 1U << (irq & 0x1f);
539 
540  _ARMV7M_NVIC->icpr [index] = bit;
541 }
542 
543 static inline bool _ARMV7M_NVIC_Is_active( int irq )
544 {
545  int index = irq >> 5;
546  uint32_t bit = 1U << (irq & 0x1f);
547 
548  return (_ARMV7M_NVIC->iabr [index] & bit) != 0;
549 }
550 
551 static inline void _ARMV7M_NVIC_Set_priority( int irq, int priority )
552 {
553  _ARMV7M_NVIC->ipr [irq] = (uint8_t) priority;
554 }
555 
556 static inline int _ARMV7M_NVIC_Get_priority( int irq )
557 {
558  return _ARMV7M_NVIC->ipr [irq];
559 }
560 
561 static inline bool _ARMV7M_DWT_Enable_CYCCNT( void )
562 {
563  uint32_t demcr;
564  uint32_t dwt_ctrl;
565 
566  demcr = _ARMV7M_DEBUG->demcr;
567  _ARMV7M_DEBUG->demcr = demcr | ARMV7M_DEBUG_DEMCR_TRCENA;
568  _ARM_Data_synchronization_barrier();
569 
570  dwt_ctrl = _ARMV7M_DWT->ctrl;
571  if ((dwt_ctrl & ARMV7M_DWT_CTRL_NOCYCCNT) == 0) {
572  _ARMV7M_DWT->lar = ARMV7M_DWT_LAR_UNLOCK_MAGIC;
573  _ARM_Data_synchronization_barrier();
574  _ARMV7M_DWT->ctrl = dwt_ctrl | ARMV7M_DWT_CTRL_CYCCNTENA;
575  return true;
576  } else {
577  _ARMV7M_DEBUG->demcr = demcr;
578  return false;
579  }
580 }
581 
582 int _ARMV7M_Get_exception_priority( int vector );
583 
584 void _ARMV7M_Set_exception_priority( int vector, int priority );
585 
586 ARMV7M_Exception_handler _ARMV7M_Get_exception_handler( int index );
587 
588 void _ARMV7M_Set_exception_handler(
589  int index,
590  ARMV7M_Exception_handler handler
591 );
592 
596 void _ARMV7M_Set_exception_priority_and_handler(
597  int index,
598  int priority,
599  ARMV7M_Exception_handler handler
600 );
601 
602 void _ARMV7M_Exception_default( void );
603 
604 void _ARMV7M_Interrupt_service_enter( void );
605 
606 void _ARMV7M_Interrupt_service_leave( void );
607 
608 void _ARMV7M_Pendable_service_call( void );
609 
610 void _ARMV7M_Supervisor_call( void );
611 
612 #endif /* ASM */
613 
614 #endif /* ARM_MULTILIB_ARCH_V7M */
615 
616 #ifdef __cplusplus
617 }
618 #endif /* __cplusplus */
619 
620 #endif /* RTEMS_SCORE_ARMV7M_H */
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.