RTEMS  5.0.0
uart.h
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1 
9 /*
10  * This software is Copyright (C) 1998 by T.sqware - all rights limited
11  * It is provided in to the public domain "as is", can be freely modified
12  * as far as this copyight notice is kept unchanged, but does not imply
13  * an endorsement by T.sqware of the product in which it is included.
14  *
15  * Copyright (c) Canon Research France SA.]
16  * Emmanuel Raguet, mailto:raguet@crf.canon.fr
17  *
18  * The license and distribution terms for this file may be
19  * found in the file LICENSE in this distribution or at
20  * http://www.rtems.org/license/LICENSE.
21  */
22 
23 #ifndef _BSPUART_H
24 #define _BSPUART_H
25 
26 #include <rtems/bspIo.h>
27 
28 void BSP_uart_init(int uart, int baud, int hwFlow);
29 void BSP_uart_set_baud(int aurt, int baud);
30 void BSP_uart_intr_ctrl(int uart, int cmd);
31 void BSP_uart_throttle(int uart);
32 void BSP_uart_unthrottle(int uart);
33 int BSP_uart_polled_status(int uart);
34 void BSP_uart_polled_write(int uart, int val);
35 int BSP_uart_polled_read(int uart);
36 void BSP_uart_termios_set(int uart, void *ttyp);
37 int BSP_uart_termios_write_com1(int minor, const char *buf, int len);
38 int BSP_uart_termios_write_com2(int minor, const char *buf, int len);
39 void BSP_uart_termios_isr_com1(void);
40 void BSP_uart_termios_isr_com2(void);
41 void BSP_uart_dbgisr_com1(void);
42 void BSP_uart_dbgisr_com2(void);
43 extern unsigned BSP_poll_char_via_serial(void);
44 extern void BSP_output_char_via_serial(int val);
45 extern int BSPConsolePort;
46 extern int BSPBaseBaud;
47 /*
48  * Command values for BSP_uart_intr_ctrl(),
49  * values are strange in order to catch errors
50  * with assert
51  */
52 #define BSP_UART_INTR_CTRL_DISABLE (0)
53 #define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */
54 #define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */
55 #define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */
56 
57 /* Return values for uart_polled_status() */
58 #define BSP_UART_STATUS_ERROR (-1) /* No character */
59 #define BSP_UART_STATUS_NOCHAR (0) /* No character */
60 #define BSP_UART_STATUS_CHAR (1) /* Character present */
61 #define BSP_UART_STATUS_BREAK (2) /* Break point is detected */
62 
63 /* PC UART definitions */
64 #define BSP_UART_COM1 (0)
65 #define BSP_UART_COM2 (1)
66 
67 /*
68  * Base IO for UART
69  */
70 
71 #define COM1_BASE_IO 0x3F8
72 #define COM2_BASE_IO 0x2F8
73 
74 /*
75  * Offsets from base
76  */
77 
78 /* DLAB 0 */
79 #define RBR RSRBR /* Rx Buffer Register (read) */
80 #define THR RSTHR /* Tx Buffer Register (write) */
81 #define IER RSIER /* Interrupt Enable Register */
82 
83 /* DLAB X */
84 #define IIR RSIIR /* Interrupt Ident Register (read) */
85 #define FCR RSFCR /* FIFO Control Register (write) */
86 #define LCR RSLCR /* Line Control Register */
87 #define LSR RSLSR /* Line Status Register */
88 
89 /* DLAB 1 */
90 #define DLL RSDLL /* Divisor Latch, LSB */
91 #define DLM RSDLH /* Divisor Latch, MSB */
92 
93 /* Uart control */
94 #define CNT RSCNT /* General Control register */
95 
96 /*
97  * define bit for CNT
98  */
99 #define UART_ENABLE 1
100 #define PAD_ENABLE 2
101 
102 /*
103  * Interrupt source definition via IIR
104  */
105 #define NO_MORE_INTR 1
106 #define TRANSMITTER_HODING_REGISTER_EMPTY 2
107 #define RECEIVER_DATA_AVAIL 4
108 #define RECEIVER_ERROR 6
109 #define CHARACTER_TIMEOUT_INDICATION 12
110 
111 /*
112  * Bits definition of IER
113  */
114 #define RECEIVE_ENABLE 0x1
115 #define TRANSMIT_ENABLE 0x2
116 #define RECEIVER_LINE_ST_ENABLE 0x4
117 #define INTERRUPT_DISABLE 0x0
118 
119 /*
120  * Bits definition of the Line Status Register (LSR)
121  */
122 #define DR 0x01 /* Data Ready */
123 #define OE 0x02 /* Overrun Error */
124 #define PE 0x04 /* Parity Error */
125 #define FE 0x08 /* Framing Error */
126 #define BI 0x10 /* Break Interrupt */
127 #define THRE 0x20 /* Transmitter Holding Register Empty */
128 #define TEMT 0x40 /* Transmitter Empty */
129 #define ERFIFO 0x80 /* Error receive Fifo */
130 
131 /*
132  * Bits definition of the Line Control Register (LCR)
133  */
134 #define CHR_5_BITS 0
135 #define CHR_6_BITS 1
136 #define CHR_7_BITS 2
137 #define CHR_8_BITS 3
138 
139 #define WL 0x03 /* Word length mask */
140 #define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */
141 #define PEN 0x08 /* Parity Enabled */
142 #define EPS 0x10 /* Even Parity Select, otherwise Odd */
143 #define SP 0x20 /* Stick Parity */
144 #define BCB 0x40 /* Break Control Bit */
145 #define DLAB 0x80 /* Enable Divisor Latch Access */
146 
147 /*
148  * Bits definition of the FIFO Control Register : WD16C552 or NS16550
149  */
150 
151 #define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */
152 #define FIFO_EN 0x01 /* Enable the FIFO */
153 #define XMIT_RESET 0x04 /* Transmit FIFO Reset */
154 #define RCV_RESET 0x02 /* Receive FIFO Reset */
155 #define FCR3 0x08 /* do not understand manual! */
156 
157 #define RECEIVE_FIFO_TRIGGER1 0x0 /* trigger recieve interrupt after 1 byte */
158 #define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger recieve interrupt after 4 byte */
159 #define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger recieve interrupt after 8 byte */
160 #define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger recieve interrupt after 14 byte */
161 #define TRIG_LEVEL 0xc0 /* Mask for the trigger level */
162 
163 #endif /* _BSPUART_H */
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