RTEMS  5.0.0
cpuimpl.h
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1 
7 /*
8  * Copyright (c) 2013, 2016 embedded brains GmbH
9  *
10  * The license and distribution terms for this file may be
11  * found in the file LICENSE in this distribution or at
12  * http://www.rtems.org/license/LICENSE.
13  */
14 
15 #ifndef _RTEMS_SCORE_CPUIMPL_H
16 #define _RTEMS_SCORE_CPUIMPL_H
17 
18 #include <rtems/score/cpu.h>
19 
30 #define CPU_PER_CPU_CONTROL_SIZE 0
31 
32 #ifdef ARM_MULTILIB_ARCH_V4
33 
34 #if defined(ARM_MULTILIB_VFP_D32)
35 #define CPU_INTERRUPT_FRAME_SIZE 240
36 #elif defined(ARM_MULTILIB_VFP)
37 #define CPU_INTERRUPT_FRAME_SIZE 112
38 #else
39 #define CPU_INTERRUPT_FRAME_SIZE 40
40 #endif
41 
42 #endif /* ARM_MULTILIB_ARCH_V4 */
43 
44 #ifndef ASM
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49 
50 #ifdef ARM_MULTILIB_ARCH_V4
51 
52 typedef struct {
53 #ifdef ARM_MULTILIB_VFP
54  uint32_t fpscr;
55 #ifdef ARM_MULTILIB_VFP_D32
56  double d16;
57  double d17;
58  double d18;
59  double d19;
60  double d20;
61  double d21;
62  double d22;
63  double d23;
64  double d24;
65  double d25;
66  double d26;
67  double d27;
68  double d28;
69  double d29;
70  double d30;
71  double d31;
72 #endif /* ARM_MULTILIB_VFP_D32 */
73  double d0;
74  double d1;
75  double d2;
76  double d3;
77  double d4;
78  double d5;
79  double d6;
80  double d7;
81 #endif /* ARM_MULTILIB_VFP */
82  uint32_t r9;
83  uint32_t lr;
84  uint32_t r0;
85  uint32_t r1;
86  uint32_t r2;
87  uint32_t r3;
88  uint32_t return_pc;
89  uint32_t return_cpsr;
90  uint32_t r7;
91  uint32_t r12;
93 
94 #ifdef RTEMS_SMP
95 
96 static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control( void )
97 {
98  struct Per_CPU_Control *cpu_self;
99 
100  /* Use PL1 only Thread ID Register (TPIDRPRW) */
101  __asm__ volatile (
102  "mrc p15, 0, %0, c13, c0, 4"
103  : "=r" ( cpu_self )
104  );
105 
106  return cpu_self;
107 }
108 
109 #define _CPU_Get_current_per_CPU_control() _ARM_Get_current_per_CPU_control()
110 
111 #endif /* RTEMS_SMP */
112 
113 #endif /* ARM_MULTILIB_ARCH_V4 */
114 
115 void _CPU_Context_volatile_clobber( uintptr_t pattern );
116 
117 void _CPU_Context_validate( uintptr_t pattern );
118 
120 {
121  __asm__ volatile ( "udf" );
122 }
123 
125 {
126  __asm__ volatile ( "nop" );
127 }
128 
129 #ifdef __cplusplus
130 }
131 #endif
132 
133 #endif /* ASM */
134 
137 #endif /* _RTEMS_SCORE_CPUIMPL_H */
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
Interrupt stack frame (ISF).
Definition: cpu.h:306
Per CPU Core Structure.
Definition: percpu.h:290
RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation(void)
Emits a no operation instruction (nop).
Definition: cpuimpl.h:132
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal(void)
Emits an illegal instruction.
Definition: cpuimpl.h:122