RTEMS  5.0.0
bsp.h
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1 
7 /*
8  * Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved.
9  *
10  * embedded brains GmbH
11  * Dornierstr. 4
12  * 82178 Puchheim
13  * Germany
14  * <info@embedded-brains.de>
15  *
16  * The license and distribution terms for this file may be
17  * found in the file LICENSE in this distribution or at
18  * http://www.rtems.org/license/LICENSE.
19  */
20 
21 #ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H
22 #define LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H
23 
34 #include <bspopts.h>
35 
36 #define BSP_FEATURE_IRQ_EXTENSION
37 
38 #ifndef ASM
39 
40 #include <rtems.h>
41 
43 
44 #ifdef __cplusplus
45 extern "C" {
46 #endif /* __cplusplus */
47 
48 #define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000
49 
50 #define BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
51 
52 #define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 )
53 
54 #define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 )
55 
56 #define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
57 
58 #ifndef BSP_ARM_A9MPCORE_PERIPHCLK
59 extern uint32_t altera_cyclone_v_a9mpcore_periphclk;
60 #define BSP_ARM_A9MPCORE_PERIPHCLK altera_cyclone_v_a9mpcore_periphclk
61 #define ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK
62 #endif
63 
64 #define BSP_ARM_L2C_310_BASE 0xfffef000
65 
66 #define BSP_ARM_L2C_310_ID 0x410000c9
67 
68 #ifdef __cplusplus
69 }
70 #endif /* __cplusplus */
71 
72 #endif /* ASM */
73 
74 /* @} */
75 
76 #endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H */
DEFAULT_INITIAL_EXTENSION Support.