23 #ifndef LIBBSP_ARM_SHARED_ARM_GIC_H 24 #define LIBBSP_ARM_SHARED_ARM_GIC_H 42 #define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5) 43 #define GIC_ID_TO_ONE_BIT_REG_BIT(id) (1U << ((id) & 0x1fU)) 45 #define GIC_ID_TO_TWO_BITS_REG_INDEX(id) ((id) >> 4) 46 #define GIC_ID_TO_TWO_BITS_REG_OFFSET(id) (((id) & 0xfU) << 1) 48 static inline bool gic_id_is_enabled(
volatile gic_dist *dist, uint32_t
id)
50 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
51 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
53 return (dist->icdiser[i] & bit) != 0;
56 static inline void gic_id_enable(
volatile gic_dist *dist, uint32_t
id)
58 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
59 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
61 dist->icdiser[i] = bit;
64 static inline void gic_id_disable(
volatile gic_dist *dist, uint32_t
id)
66 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
67 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
69 dist->icdicer[i] = bit;
72 static inline bool gic_id_is_pending(
volatile gic_dist *dist, uint32_t
id)
74 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
75 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
77 return (dist->icdispr[i] & bit) != 0;
80 static inline void gic_id_set_pending(
volatile gic_dist *dist, uint32_t
id)
82 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
83 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
85 dist->icdispr[i] = bit;
88 static inline void gic_id_clear_pending(
volatile gic_dist *dist, uint32_t
id)
90 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
91 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
93 dist->icdicpr[i] = bit;
96 static inline bool gic_id_is_active(
volatile gic_dist *dist, uint32_t
id)
98 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
99 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
101 return (dist->icdabr[i] & bit) != 0;
109 static inline gic_group gic_id_get_group(
114 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
115 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
117 return (dist->icdigr[i] & bit) != 0 ? GIC_GROUP_1 : GIC_GROUP_0;
120 static inline void gic_id_set_group(
126 uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(
id);
127 uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(
id);
128 uint32_t icdigr = dist->icdigr[i];
132 if (group == GIC_GROUP_1) {
136 dist->icdigr[i] = icdigr;
139 static inline void gic_id_set_priority(
145 dist->icdipr[id] = priority;
148 static inline uint8_t gic_id_get_priority(
volatile gic_dist *dist, uint32_t
id)
150 return dist->icdipr[id];
153 static inline void gic_id_set_targets(
159 dist->icdiptr[id] = targets;
162 static inline uint8_t gic_id_get_targets(
volatile gic_dist *dist, uint32_t
id)
164 return dist->icdiptr[id];
172 static inline gic_trigger_mode gic_id_get_trigger_mode(
177 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
178 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id) + 1;
179 uint32_t bit = 1U << o;
181 return (dist->icdicfr[i] & bit) != 0 ?
182 GIC_EDGE_TRIGGERED : GIC_LEVEL_SENSITIVE;
185 static inline void gic_id_set_trigger_mode(
188 gic_trigger_mode mode
191 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
192 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id) + 1;
193 uint32_t bit = mode << o;
194 uint32_t mask = 1U << o;
195 uint32_t icdicfr = dist->icdicfr[i];
200 dist->icdicfr[i] = icdicfr;
206 } gic_handling_model;
208 static inline gic_handling_model gic_id_get_handling_model(
213 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
214 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id);
215 uint32_t bit = 1U << o;
217 return (dist->icdicfr[i] & bit) != 0 ? GIC_1_TO_N : GIC_N_TO_N;
220 static inline void gic_id_set_handling_model(
223 gic_handling_model model
226 uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(
id);
227 uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(
id);
228 uint32_t bit = model << o;
229 uint32_t mask = 1U << o;
230 uint32_t icdicfr = dist->icdicfr[i];
235 dist->icdicfr[i] = icdicfr;
Definition: arm-gic-regs.h:88
ARM GIC Register definitions.