RTEMS  5.0.0
arm-a9mpcore-regs.h
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1 
9 /*
10  * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
11  *
12  * embedded brains GmbH
13  * Dornierstr. 4
14  * 82178 Puchheim
15  * Germany
16  * <info@embedded-brains.de>
17  *
18  * The license and distribution terms for this file may be
19  * found in the file LICENSE in this distribution or at
20  * http://www.rtems.org/license/LICENSE.
21  */
22 
23 #ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
24 #define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
25 
26 #include <bsp/utility.h>
27 
28 typedef struct {
29  uint32_t ctrl;
30 #define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0)
31 #define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1)
32 #define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2)
33 #define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3)
34 #define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4)
35 #define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5)
36 #define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6)
37  uint32_t cfg;
38 #define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1)
39 #define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1)
40 #define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
41 #define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7)
42 #define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7)
43 #define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
44 #define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15)
45 #define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15)
46 #define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
47  uint32_t pwrst;
48  uint32_t invss;
49 #define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3)
50 #define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */
51 #define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
52 #define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7)
53 #define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */
54 #define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
55 #define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11)
56 #define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */
57 #define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
58 #define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15)
59 #define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */
60 #define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
61  uint32_t reserved_09[8];
62  uint32_t diagn_ctrl;
63 #define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0)
64  uint32_t reserved_10[3];
65  uint32_t fltstart;
66  uint32_t fltend;
67  uint32_t reserved_48[2];
68  uint32_t sac;
69  uint32_t snsac;
70 } a9mpcore_scu;
71 
72 typedef struct {
73 } a9mpcore_gic;
74 
75 typedef struct {
76  uint32_t cntrlower;
77  uint32_t cntrupper;
78 #define A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
79 #define A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
80 #define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
81 #define A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3)
82 #define A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2)
83 #define A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1)
84 #define A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0)
85  uint32_t ctrl;
86 #define A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0)
87  uint32_t irqst;
88  uint32_t cmpvallower;
89  uint32_t cmpvalupper;
90  uint32_t autoinc;
91 } a9mpcore_gt;
92 
93 typedef struct {
94  uint32_t load;
95  uint32_t cntr;
96  uint32_t ctrl;
97 #define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
98 #define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
99 #define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
100 #define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2)
101 #define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1)
102 #define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0)
103  uint32_t irqst;
104 #define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0)
105 } a9mpcore_pt;
106 
107 typedef struct {
108  uint32_t load;
109  uint32_t cntr;
110  uint32_t ctrl;
111  uint32_t irqst;
112  uint32_t rstst;
113  uint32_t dis;
114 } a9mpcore_pw;
115 
116 typedef struct {
118 
119 typedef struct {
120  a9mpcore_scu scu;
121  uint32_t reserved_58[42];
122  a9mpcore_gic gic;
123  uint32_t reserved_100[64];
124  a9mpcore_gt gt;
125  uint32_t reserved_21c[249];
126  a9mpcore_pt pt;
127  uint32_t reserved_610[4];
128  a9mpcore_pw pw;
129  uint32_t reserved_638[626];
130  a9mpcore_idist idist;
131 } a9mpcore;
132 
133 #endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H */
Definition: arm-a9mpcore-regs.h:75
Definition: arm-a9mpcore-regs.h:107
Definition: arm-a9mpcore-regs.h:93
Definition: arm-a9mpcore-regs.h:28
Definition: arm-a9mpcore-regs.h:119
Utility macros.
Definition: arm-a9mpcore-regs.h:72
Definition: arm-a9mpcore-regs.h:116