RTEMS  5.0.0
alt_sdr.h
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1 
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36 
37 /* Altera - ALT_SDR */
38 
39 #ifndef __ALTERA_ALT_SDR_H__
40 #define __ALTERA_ALT_SDR_H__
41 
42 #ifdef __cplusplus
43 extern "C"
44 {
45 #endif /* __cplusplus */
46 
47 /*
48  * Component : SDRAM Controller - ALT_SDR
49  * SDRAM Controller
50  *
51  * Address map for the SDRAM Interface registers
52  *
53  */
54 /*
55  * Register Group : SDRAM Controller Module - ALT_SDR_CTL
56  * SDRAM Controller Module
57  *
58  * Address map for the SDRAM controller and multi-port front-end.
59  *
60  * All registers in this group reset to zero.
61  *
62  */
63 /*
64  * Register : Controller Configuration Register - ctrlcfg
65  *
66  * The Controller Configuration Register determines the behavior of the controller.
67  *
68  * Register Layout
69  *
70  * Bits | Access | Reset | Description
71  * :--------|:-------|:--------|:---------------------------
72  * [2:0] | RW | Unknown | DRAM Memory Type
73  * [7:3] | RW | Unknown | DRAM Memory Burst Length
74  * [9:8] | RW | Unknown | Address Interleaving Order
75  * [10] | RW | Unknown | ECC Enable
76  * [11] | RW | Unknown | ECC Auto-Correction Enable
77  * [12] | RW | Unknown | TBD
78  * [13] | RW | Unknown | Generate Single Bit Errors
79  * [14] | RW | Unknown | Generate Double Bit Errors
80  * [15] | RW | Unknown | Command Reorder Enable
81  * [21:16] | RW | Unknown | Starvation Limit
82  * [22] | RW | Unknown | DQS Tracking Enable
83  * [23] | RW | Unknown | No DM Pins Present
84  * [24] | RW | Unknown | Burst Interrupt Enable
85  * [25] | RW | Unknown | Burst Terminate Enable
86  * [31:26] | ??? | Unknown | *UNDEFINED*
87  *
88  */
89 /*
90  * Field : DRAM Memory Type - memtype
91  *
92  * Selects memory type. Program this field with one of the following binary values,
93  * "001" for DDR2 SDRAM, "010" for DDR3 SDRAM, "011"
94  * for LPDDR1 SDRAM or "100" for LPDDR2 SDRAM.
95  *
96  * Field Access Macros:
97  *
98  */
99 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */
100 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB 0
101 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */
102 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB 2
103 /* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */
104 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH 3
105 /* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */
106 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK 0x00000007
107 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */
108 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK 0xfffffff8
109 /* The reset value of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field is UNKNOWN. */
110 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET 0x0
111 /* Extracts the ALT_SDR_CTL_CTLCFG_MEMTYPE field value from a register. */
112 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_GET(value) (((value) & 0x00000007) >> 0)
113 /* Produces a ALT_SDR_CTL_CTLCFG_MEMTYPE register field value suitable for setting the register. */
114 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET(value) (((value) << 0) & 0x00000007)
115 
116 /*
117  * Field : DRAM Memory Burst Length - membl
118  *
119  * Configures burst length as a static decimal value. Legal values are valid for
120  * JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, this
121  * should be programmed with 8 (binary &quot;01000&quot;), for DDR2 it can be
122  * either 4 or 8 depending on the exact DRAM chip. LPDDR2 can be programmed with
123  * 4, 8, or 16 and LPDDR can be programmed with 2, 4, or 8. You must also program
124  * the membl field in the staticcfg register.
125  *
126  * Field Access Macros:
127  *
128  */
129 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */
130 #define ALT_SDR_CTL_CTLCFG_MEMBL_LSB 3
131 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */
132 #define ALT_SDR_CTL_CTLCFG_MEMBL_MSB 7
133 /* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */
134 #define ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH 5
135 /* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */
136 #define ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK 0x000000f8
137 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */
138 #define ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK 0xffffff07
139 /* The reset value of the ALT_SDR_CTL_CTLCFG_MEMBL register field is UNKNOWN. */
140 #define ALT_SDR_CTL_CTLCFG_MEMBL_RESET 0x0
141 /* Extracts the ALT_SDR_CTL_CTLCFG_MEMBL field value from a register. */
142 #define ALT_SDR_CTL_CTLCFG_MEMBL_GET(value) (((value) & 0x000000f8) >> 3)
143 /* Produces a ALT_SDR_CTL_CTLCFG_MEMBL register field value suitable for setting the register. */
144 #define ALT_SDR_CTL_CTLCFG_MEMBL_SET(value) (((value) << 3) & 0x000000f8)
145 
146 /*
147  * Field : Address Interleaving Order - addrorder
148  *
149  * Selects the order for address interleaving. Programming this field with
150  * different values gives different mappings between the AXI or Avalon-MM address
151  * and the SDRAM address. Program this field with the following binary values to
152  * select the ordering. &quot;00&quot; - chip, row, bank, column, &quot;01&quot; -
153  * chip, bank, row, column, &quot;10&quot;-row, chip, bank, column
154  *
155  * Field Access Macros:
156  *
157  */
158 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */
159 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB 8
160 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */
161 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB 9
162 /* The width in bits of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */
163 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH 2
164 /* The mask used to set the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */
165 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK 0x00000300
166 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */
167 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK 0xfffffcff
168 /* The reset value of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field is UNKNOWN. */
169 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET 0x0
170 /* Extracts the ALT_SDR_CTL_CTLCFG_ADDRORDER field value from a register. */
171 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_GET(value) (((value) & 0x00000300) >> 8)
172 /* Produces a ALT_SDR_CTL_CTLCFG_ADDRORDER register field value suitable for setting the register. */
173 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET(value) (((value) << 8) & 0x00000300)
174 
175 /*
176  * Field : ECC Enable - eccen
177  *
178  * Enable the generation and checking of ECC. This bit must only be set if the
179  * memory connected to the SDRAM interface is 24 or 40 bits wide. If you set this,
180  * you must clear the useeccasdata field in the staticcfg register.
181  *
182  * Field Access Macros:
183  *
184  */
185 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */
186 #define ALT_SDR_CTL_CTLCFG_ECCEN_LSB 10
187 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */
188 #define ALT_SDR_CTL_CTLCFG_ECCEN_MSB 10
189 /* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */
190 #define ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH 1
191 /* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */
192 #define ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK 0x00000400
193 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */
194 #define ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK 0xfffffbff
195 /* The reset value of the ALT_SDR_CTL_CTLCFG_ECCEN register field is UNKNOWN. */
196 #define ALT_SDR_CTL_CTLCFG_ECCEN_RESET 0x0
197 /* Extracts the ALT_SDR_CTL_CTLCFG_ECCEN field value from a register. */
198 #define ALT_SDR_CTL_CTLCFG_ECCEN_GET(value) (((value) & 0x00000400) >> 10)
199 /* Produces a ALT_SDR_CTL_CTLCFG_ECCEN register field value suitable for setting the register. */
200 #define ALT_SDR_CTL_CTLCFG_ECCEN_SET(value) (((value) << 10) & 0x00000400)
201 
202 /*
203  * Field : ECC Auto-Correction Enable - ecccorren
204  *
205  * Enable auto correction of the read data returned when single bit error is
206  * detected.
207  *
208  * Field Access Macros:
209  *
210  */
211 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */
212 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB 11
213 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */
214 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB 11
215 /* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */
216 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH 1
217 /* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */
218 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK 0x00000800
219 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */
220 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK 0xfffff7ff
221 /* The reset value of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field is UNKNOWN. */
222 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET 0x0
223 /* Extracts the ALT_SDR_CTL_CTLCFG_ECCCORREN field value from a register. */
224 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_GET(value) (((value) & 0x00000800) >> 11)
225 /* Produces a ALT_SDR_CTL_CTLCFG_ECCCORREN register field value suitable for setting the register. */
226 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET(value) (((value) << 11) & 0x00000800)
227 
228 /*
229  * Field : TBD - cfg_enable_ecc_code_overwrites
230  *
231  * Set to a one to enable ECC overwrites. ECC overwrites occur when a correctable
232  * ECC error is seen and cause a new read/modify/write to be scheduled for that
233  * location to clear the ECC error.
234  *
235  * Field Access Macros:
236  *
237  */
238 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */
239 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB 12
240 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */
241 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB 12
242 /* The width in bits of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */
243 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH 1
244 /* The mask used to set the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */
245 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK 0x00001000
246 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */
247 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK 0xffffefff
248 /* The reset value of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field is UNKNOWN. */
249 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET 0x0
250 /* Extracts the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS field value from a register. */
251 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET(value) (((value) & 0x00001000) >> 12)
252 /* Produces a ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value suitable for setting the register. */
253 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET(value) (((value) << 12) & 0x00001000)
254 
255 /*
256  * Field : Generate Single Bit Errors - gensbe
257  *
258  * Enable the deliberate insertion of single bit errors in data written to memory.
259  * This should only be used for testing purposes.
260  *
261  * Field Access Macros:
262  *
263  */
264 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */
265 #define ALT_SDR_CTL_CTLCFG_GENSBE_LSB 13
266 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */
267 #define ALT_SDR_CTL_CTLCFG_GENSBE_MSB 13
268 /* The width in bits of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */
269 #define ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH 1
270 /* The mask used to set the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */
271 #define ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK 0x00002000
272 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */
273 #define ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK 0xffffdfff
274 /* The reset value of the ALT_SDR_CTL_CTLCFG_GENSBE register field is UNKNOWN. */
275 #define ALT_SDR_CTL_CTLCFG_GENSBE_RESET 0x0
276 /* Extracts the ALT_SDR_CTL_CTLCFG_GENSBE field value from a register. */
277 #define ALT_SDR_CTL_CTLCFG_GENSBE_GET(value) (((value) & 0x00002000) >> 13)
278 /* Produces a ALT_SDR_CTL_CTLCFG_GENSBE register field value suitable for setting the register. */
279 #define ALT_SDR_CTL_CTLCFG_GENSBE_SET(value) (((value) << 13) & 0x00002000)
280 
281 /*
282  * Field : Generate Double Bit Errors - gendbe
283  *
284  * Enable the deliberate insertion of double bit errors in data written to memory.
285  * This should only be used for testing purposes.
286  *
287  * Field Access Macros:
288  *
289  */
290 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */
291 #define ALT_SDR_CTL_CTLCFG_GENDBE_LSB 14
292 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */
293 #define ALT_SDR_CTL_CTLCFG_GENDBE_MSB 14
294 /* The width in bits of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */
295 #define ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH 1
296 /* The mask used to set the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */
297 #define ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK 0x00004000
298 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */
299 #define ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK 0xffffbfff
300 /* The reset value of the ALT_SDR_CTL_CTLCFG_GENDBE register field is UNKNOWN. */
301 #define ALT_SDR_CTL_CTLCFG_GENDBE_RESET 0x0
302 /* Extracts the ALT_SDR_CTL_CTLCFG_GENDBE field value from a register. */
303 #define ALT_SDR_CTL_CTLCFG_GENDBE_GET(value) (((value) & 0x00004000) >> 14)
304 /* Produces a ALT_SDR_CTL_CTLCFG_GENDBE register field value suitable for setting the register. */
305 #define ALT_SDR_CTL_CTLCFG_GENDBE_SET(value) (((value) << 14) & 0x00004000)
306 
307 /*
308  * Field : Command Reorder Enable - reorderen
309  *
310  * This bit controls whether the controller can re-order operations to optimize
311  * SDRAM bandwidth. It should generally be set to a one.
312  *
313  * Field Access Macros:
314  *
315  */
316 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */
317 #define ALT_SDR_CTL_CTLCFG_REORDEREN_LSB 15
318 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */
319 #define ALT_SDR_CTL_CTLCFG_REORDEREN_MSB 15
320 /* The width in bits of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */
321 #define ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH 1
322 /* The mask used to set the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */
323 #define ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK 0x00008000
324 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */
325 #define ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK 0xffff7fff
326 /* The reset value of the ALT_SDR_CTL_CTLCFG_REORDEREN register field is UNKNOWN. */
327 #define ALT_SDR_CTL_CTLCFG_REORDEREN_RESET 0x0
328 /* Extracts the ALT_SDR_CTL_CTLCFG_REORDEREN field value from a register. */
329 #define ALT_SDR_CTL_CTLCFG_REORDEREN_GET(value) (((value) & 0x00008000) >> 15)
330 /* Produces a ALT_SDR_CTL_CTLCFG_REORDEREN register field value suitable for setting the register. */
331 #define ALT_SDR_CTL_CTLCFG_REORDEREN_SET(value) (((value) << 15) & 0x00008000)
332 
333 /*
334  * Field : Starvation Limit - starvelimit
335  *
336  * Specifies the number of DRAM burst transactions an individual transaction will
337  * allow to reorder ahead of it before its priority is raised in the memory
338  * controller.
339  *
340  * Field Access Macros:
341  *
342  */
343 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */
344 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB 16
345 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */
346 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB 21
347 /* The width in bits of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */
348 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH 6
349 /* The mask used to set the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */
350 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK 0x003f0000
351 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */
352 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK 0xffc0ffff
353 /* The reset value of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field is UNKNOWN. */
354 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET 0x0
355 /* Extracts the ALT_SDR_CTL_CTLCFG_STARVELIMIT field value from a register. */
356 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET(value) (((value) & 0x003f0000) >> 16)
357 /* Produces a ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value suitable for setting the register. */
358 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET(value) (((value) << 16) & 0x003f0000)
359 
360 /*
361  * Field : DQS Tracking Enable - dqstrken
362  *
363  * Enables DQS tracking in the PHY.
364  *
365  * Field Access Macros:
366  *
367  */
368 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */
369 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB 22
370 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */
371 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB 22
372 /* The width in bits of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */
373 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH 1
374 /* The mask used to set the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */
375 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK 0x00400000
376 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */
377 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK 0xffbfffff
378 /* The reset value of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field is UNKNOWN. */
379 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET 0x0
380 /* Extracts the ALT_SDR_CTL_CTLCFG_DQSTRKEN field value from a register. */
381 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET(value) (((value) & 0x00400000) >> 22)
382 /* Produces a ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value suitable for setting the register. */
383 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET(value) (((value) << 22) & 0x00400000)
384 
385 /*
386  * Field : No DM Pins Present - nodmpins
387  *
388  * Set to a one to enable DRAM operation if no DM pins are connected.
389  *
390  * Field Access Macros:
391  *
392  */
393 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */
394 #define ALT_SDR_CTL_CTLCFG_NODMPINS_LSB 23
395 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */
396 #define ALT_SDR_CTL_CTLCFG_NODMPINS_MSB 23
397 /* The width in bits of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */
398 #define ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH 1
399 /* The mask used to set the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */
400 #define ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK 0x00800000
401 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */
402 #define ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK 0xff7fffff
403 /* The reset value of the ALT_SDR_CTL_CTLCFG_NODMPINS register field is UNKNOWN. */
404 #define ALT_SDR_CTL_CTLCFG_NODMPINS_RESET 0x0
405 /* Extracts the ALT_SDR_CTL_CTLCFG_NODMPINS field value from a register. */
406 #define ALT_SDR_CTL_CTLCFG_NODMPINS_GET(value) (((value) & 0x00800000) >> 23)
407 /* Produces a ALT_SDR_CTL_CTLCFG_NODMPINS register field value suitable for setting the register. */
408 #define ALT_SDR_CTL_CTLCFG_NODMPINS_SET(value) (((value) << 23) & 0x00800000)
409 
410 /*
411  * Field : Burst Interrupt Enable - burstintren
412  *
413  * Set to a one to enable the controller to issue burst interrupt commands. This
414  * must only be set when the DRAM memory type is LPDDR2.
415  *
416  * Field Access Macros:
417  *
418  */
419 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */
420 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB 24
421 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */
422 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB 24
423 /* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */
424 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH 1
425 /* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */
426 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK 0x01000000
427 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */
428 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK 0xfeffffff
429 /* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field is UNKNOWN. */
430 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET 0x0
431 /* Extracts the ALT_SDR_CTL_CTLCFG_BURSTINTREN field value from a register. */
432 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET(value) (((value) & 0x01000000) >> 24)
433 /* Produces a ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value suitable for setting the register. */
434 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET(value) (((value) << 24) & 0x01000000)
435 
436 /*
437  * Field : Burst Terminate Enable - bursttermen
438  *
439  * Set to a one to enable the controller to issue burst terminate commands. This
440  * must only be set when the DRAM memory type is LPDDR2.
441  *
442  * Field Access Macros:
443  *
444  */
445 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */
446 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB 25
447 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */
448 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB 25
449 /* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */
450 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH 1
451 /* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */
452 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK 0x02000000
453 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */
454 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK 0xfdffffff
455 /* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field is UNKNOWN. */
456 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET 0x0
457 /* Extracts the ALT_SDR_CTL_CTLCFG_BURSTTERMEN field value from a register. */
458 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET(value) (((value) & 0x02000000) >> 25)
459 /* Produces a ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value suitable for setting the register. */
460 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET(value) (((value) << 25) & 0x02000000)
461 
462 #ifndef __ASSEMBLY__
463 /*
464  * WARNING: The C register and register group struct declarations are provided for
465  * convenience and illustrative purposes. They should, however, be used with
466  * caution as the C language standard provides no guarantees about the alignment or
467  * atomicity of device memory accesses. The recommended practice for writing
468  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
469  * alt_write_word() functions.
470  *
471  * The struct declaration for register ALT_SDR_CTL_CTLCFG.
472  */
473 struct ALT_SDR_CTL_CTLCFG_s
474 {
475  uint32_t memtype : 3; /* DRAM Memory Type */
476  uint32_t membl : 5; /* DRAM Memory Burst Length */
477  uint32_t addrorder : 2; /* Address Interleaving Order */
478  uint32_t eccen : 1; /* ECC Enable */
479  uint32_t ecccorren : 1; /* ECC Auto-Correction Enable */
480  uint32_t cfg_enable_ecc_code_overwrites : 1; /* TBD */
481  uint32_t gensbe : 1; /* Generate Single Bit Errors */
482  uint32_t gendbe : 1; /* Generate Double Bit Errors */
483  uint32_t reorderen : 1; /* Command Reorder Enable */
484  uint32_t starvelimit : 6; /* Starvation Limit */
485  uint32_t dqstrken : 1; /* DQS Tracking Enable */
486  uint32_t nodmpins : 1; /* No DM Pins Present */
487  uint32_t burstintren : 1; /* Burst Interrupt Enable */
488  uint32_t bursttermen : 1; /* Burst Terminate Enable */
489  uint32_t : 6; /* *UNDEFINED* */
490 };
491 
492 /* The typedef declaration for register ALT_SDR_CTL_CTLCFG. */
493 typedef volatile struct ALT_SDR_CTL_CTLCFG_s ALT_SDR_CTL_CTLCFG_t;
494 #endif /* __ASSEMBLY__ */
495 
496 /* The byte offset of the ALT_SDR_CTL_CTLCFG register from the beginning of the component. */
497 #define ALT_SDR_CTL_CTLCFG_OFST 0x0
498 
499 /*
500  * Register : DRAM Timings 1 Register - dramtiming1
501  *
502  * This register implements JEDEC standardized timing parameters. It should be
503  * programmed in clock cycles, for the value specified by the memory vendor.
504  *
505  * Register Layout
506  *
507  * Bits | Access | Reset | Description
508  * :--------|:-------|:--------|:---------------------------
509  * [3:0] | RW | Unknown | CAS Write Latency
510  * [8:4] | RW | Unknown | Additive Latency
511  * [13:9] | RW | Unknown | CAS Read Latency
512  * [17:14] | RW | Unknown | Activate to Activate Delay
513  * [23:18] | RW | Unknown | Four Activate Window Time
514  * [31:24] | RW | Unknown | Refresh Cycle Time
515  *
516  */
517 /*
518  * Field : CAS Write Latency - tcwl
519  *
520  * Memory write latency.
521  *
522  * Field Access Macros:
523  *
524  */
525 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */
526 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB 0
527 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */
528 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB 3
529 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */
530 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH 4
531 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */
532 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK 0x0000000f
533 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */
534 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK 0xfffffff0
535 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field is UNKNOWN. */
536 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET 0x0
537 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCWL field value from a register. */
538 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_GET(value) (((value) & 0x0000000f) >> 0)
539 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TCWL register field value suitable for setting the register. */
540 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET(value) (((value) << 0) & 0x0000000f)
541 
542 /*
543  * Field : Additive Latency - tal
544  *
545  * Memory additive latency.
546  *
547  * Field Access Macros:
548  *
549  */
550 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */
551 #define ALT_SDR_CTL_DRAMTIMING1_TAL_LSB 4
552 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */
553 #define ALT_SDR_CTL_DRAMTIMING1_TAL_MSB 8
554 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */
555 #define ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH 5
556 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */
557 #define ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK 0x000001f0
558 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */
559 #define ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK 0xfffffe0f
560 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TAL register field is UNKNOWN. */
561 #define ALT_SDR_CTL_DRAMTIMING1_TAL_RESET 0x0
562 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TAL field value from a register. */
563 #define ALT_SDR_CTL_DRAMTIMING1_TAL_GET(value) (((value) & 0x000001f0) >> 4)
564 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TAL register field value suitable for setting the register. */
565 #define ALT_SDR_CTL_DRAMTIMING1_TAL_SET(value) (((value) << 4) & 0x000001f0)
566 
567 /*
568  * Field : CAS Read Latency - tcl
569  *
570  * Memory read latency.
571  *
572  * Field Access Macros:
573  *
574  */
575 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */
576 #define ALT_SDR_CTL_DRAMTIMING1_TCL_LSB 9
577 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */
578 #define ALT_SDR_CTL_DRAMTIMING1_TCL_MSB 13
579 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */
580 #define ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH 5
581 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */
582 #define ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK 0x00003e00
583 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */
584 #define ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK 0xffffc1ff
585 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCL register field is UNKNOWN. */
586 #define ALT_SDR_CTL_DRAMTIMING1_TCL_RESET 0x0
587 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCL field value from a register. */
588 #define ALT_SDR_CTL_DRAMTIMING1_TCL_GET(value) (((value) & 0x00003e00) >> 9)
589 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TCL register field value suitable for setting the register. */
590 #define ALT_SDR_CTL_DRAMTIMING1_TCL_SET(value) (((value) << 9) & 0x00003e00)
591 
592 /*
593  * Field : Activate to Activate Delay - trrd
594  *
595  * The activate to activate, different banks timing parameter.
596  *
597  * Field Access Macros:
598  *
599  */
600 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */
601 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB 14
602 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */
603 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB 17
604 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */
605 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH 4
606 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */
607 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK 0x0003c000
608 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */
609 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK 0xfffc3fff
610 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field is UNKNOWN. */
611 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET 0x0
612 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRRD field value from a register. */
613 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_GET(value) (((value) & 0x0003c000) >> 14)
614 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TRRD register field value suitable for setting the register. */
615 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET(value) (((value) << 14) & 0x0003c000)
616 
617 /*
618  * Field : Four Activate Window Time - tfaw
619  *
620  * The four-activate window timing parameter.
621  *
622  * Field Access Macros:
623  *
624  */
625 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */
626 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB 18
627 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */
628 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB 23
629 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */
630 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH 6
631 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */
632 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK 0x00fc0000
633 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */
634 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK 0xff03ffff
635 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field is UNKNOWN. */
636 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET 0x0
637 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TFAW field value from a register. */
638 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_GET(value) (((value) & 0x00fc0000) >> 18)
639 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TFAW register field value suitable for setting the register. */
640 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET(value) (((value) << 18) & 0x00fc0000)
641 
642 /*
643  * Field : Refresh Cycle Time - trfc
644  *
645  * The refresh cycle timing parameter.
646  *
647  * Field Access Macros:
648  *
649  */
650 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */
651 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB 24
652 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */
653 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB 31
654 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */
655 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH 8
656 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */
657 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK 0xff000000
658 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */
659 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK 0x00ffffff
660 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field is UNKNOWN. */
661 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET 0x0
662 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRFC field value from a register. */
663 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_GET(value) (((value) & 0xff000000) >> 24)
664 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TRFC register field value suitable for setting the register. */
665 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET(value) (((value) << 24) & 0xff000000)
666 
667 #ifndef __ASSEMBLY__
668 /*
669  * WARNING: The C register and register group struct declarations are provided for
670  * convenience and illustrative purposes. They should, however, be used with
671  * caution as the C language standard provides no guarantees about the alignment or
672  * atomicity of device memory accesses. The recommended practice for writing
673  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
674  * alt_write_word() functions.
675  *
676  * The struct declaration for register ALT_SDR_CTL_DRAMTIMING1.
677  */
678 struct ALT_SDR_CTL_DRAMTIMING1_s
679 {
680  uint32_t tcwl : 4; /* CAS Write Latency */
681  uint32_t tal : 5; /* Additive Latency */
682  uint32_t tcl : 5; /* CAS Read Latency */
683  uint32_t trrd : 4; /* Activate to Activate Delay */
684  uint32_t tfaw : 6; /* Four Activate Window Time */
685  uint32_t trfc : 8; /* Refresh Cycle Time */
686 };
687 
688 /* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING1. */
689 typedef volatile struct ALT_SDR_CTL_DRAMTIMING1_s ALT_SDR_CTL_DRAMTIMING1_t;
690 #endif /* __ASSEMBLY__ */
691 
692 /* The byte offset of the ALT_SDR_CTL_DRAMTIMING1 register from the beginning of the component. */
693 #define ALT_SDR_CTL_DRAMTIMING1_OFST 0x4
694 
695 /*
696  * Register : DRAM Timings 2 Register - dramtiming2
697  *
698  * This register implements JEDEC standardized timing parameters. It should be
699  * programmed in clock cycles, for the value specified by the memory vendor.
700  *
701  * Register Layout
702  *
703  * Bits | Access | Reset | Description
704  * :--------|:-------|:--------|:--------------------------------
705  * [12:0] | RW | Unknown | Refresh Interval
706  * [16:13] | RW | Unknown | Activate to Read or Write Delay
707  * [20:17] | RW | Unknown | Row Precharge Time
708  * [24:21] | RW | Unknown | Write Recovery Time
709  * [28:25] | RW | Unknown | Write to Read Time
710  * [31:29] | ??? | 0x0 | *UNDEFINED*
711  *
712  */
713 /*
714  * Field : Refresh Interval - trefi
715  *
716  * The refresh interval timing parameter.
717  *
718  * Field Access Macros:
719  *
720  */
721 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */
722 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB 0
723 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */
724 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB 12
725 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */
726 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH 13
727 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */
728 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK 0x00001fff
729 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */
730 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK 0xffffe000
731 /* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field is UNKNOWN. */
732 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET 0x0
733 /* Extracts the ALT_SDR_CTL_DRAMTIMING2_TREFI field value from a register. */
734 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_GET(value) (((value) & 0x00001fff) >> 0)
735 /* Produces a ALT_SDR_CTL_DRAMTIMING2_TREFI register field value suitable for setting the register. */
736 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET(value) (((value) << 0) & 0x00001fff)
737 
738 /*
739  * Field : Activate to Read or Write Delay - trcd
740  *
741  * The activate to read/write timing parameter.
742  *
743  * Field Access Macros:
744  *
745  */
746 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */
747 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB 13
748 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */
749 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB 16
750 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */
751 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH 4
752 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */
753 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK 0x0001e000
754 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */
755 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK 0xfffe1fff
756 /* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field is UNKNOWN. */
757 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET 0x0
758 /* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRCD field value from a register. */
759 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_GET(value) (((value) & 0x0001e000) >> 13)
760 /* Produces a ALT_SDR_CTL_DRAMTIMING2_TRCD register field value suitable for setting the register. */
761 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET(value) (((value) << 13) & 0x0001e000)
762 
763 /*
764  * Field : Row Precharge Time - trp
765  *
766  * The precharge to activate timing parameter.
767  *
768  * Field Access Macros:
769  *
770  */
771 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */
772 #define ALT_SDR_CTL_DRAMTIMING2_TRP_LSB 17
773 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */
774 #define ALT_SDR_CTL_DRAMTIMING2_TRP_MSB 20
775 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */
776 #define ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH 4
777 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */
778 #define ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK 0x001e0000
779 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */
780 #define ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK 0xffe1ffff
781 /* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRP register field is UNKNOWN. */
782 #define ALT_SDR_CTL_DRAMTIMING2_TRP_RESET 0x0
783 /* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRP field value from a register. */
784 #define ALT_SDR_CTL_DRAMTIMING2_TRP_GET(value) (((value) & 0x001e0000) >> 17)
785 /* Produces a ALT_SDR_CTL_DRAMTIMING2_TRP register field value suitable for setting the register. */
786 #define ALT_SDR_CTL_DRAMTIMING2_TRP_SET(value) (((value) << 17) & 0x001e0000)
787 
788 /*
789  * Field : Write Recovery Time - twr
790  *
791  * The write recovery timing.
792  *
793  * Field Access Macros:
794  *
795  */
796 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */
797 #define ALT_SDR_CTL_DRAMTIMING2_TWR_LSB 21
798 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */
799 #define ALT_SDR_CTL_DRAMTIMING2_TWR_MSB 24
800 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */
801 #define ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH 4
802 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */
803 #define ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK 0x01e00000
804 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */
805 #define ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK 0xfe1fffff
806 /* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWR register field is UNKNOWN. */
807 #define ALT_SDR_CTL_DRAMTIMING2_TWR_RESET 0x0
808 /* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWR field value from a register. */
809 #define ALT_SDR_CTL_DRAMTIMING2_TWR_GET(value) (((value) & 0x01e00000) >> 21)
810 /* Produces a ALT_SDR_CTL_DRAMTIMING2_TWR register field value suitable for setting the register. */
811 #define ALT_SDR_CTL_DRAMTIMING2_TWR_SET(value) (((value) << 21) & 0x01e00000)
812 
813 /*
814  * Field : Write to Read Time - twtr
815  *
816  * The write to read timing parameter.
817  *
818  * Field Access Macros:
819  *
820  */
821 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */
822 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB 25
823 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */
824 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB 28
825 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */
826 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH 4
827 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */
828 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK 0x1e000000
829 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */
830 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK 0xe1ffffff
831 /* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field is UNKNOWN. */
832 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET 0x0
833 /* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWTR field value from a register. */
834 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_GET(value) (((value) & 0x1e000000) >> 25)
835 /* Produces a ALT_SDR_CTL_DRAMTIMING2_TWTR register field value suitable for setting the register. */
836 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET(value) (((value) << 25) & 0x1e000000)
837 
838 #ifndef __ASSEMBLY__
839 /*
840  * WARNING: The C register and register group struct declarations are provided for
841  * convenience and illustrative purposes. They should, however, be used with
842  * caution as the C language standard provides no guarantees about the alignment or
843  * atomicity of device memory accesses. The recommended practice for writing
844  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
845  * alt_write_word() functions.
846  *
847  * The struct declaration for register ALT_SDR_CTL_DRAMTIMING2.
848  */
849 struct ALT_SDR_CTL_DRAMTIMING2_s
850 {
851  uint32_t trefi : 13; /* Refresh Interval */
852  uint32_t trcd : 4; /* Activate to Read or Write Delay */
853  uint32_t trp : 4; /* Row Precharge Time */
854  uint32_t twr : 4; /* Write Recovery Time */
855  uint32_t twtr : 4; /* Write to Read Time */
856  uint32_t : 3; /* *UNDEFINED* */
857 };
858 
859 /* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING2. */
860 typedef volatile struct ALT_SDR_CTL_DRAMTIMING2_s ALT_SDR_CTL_DRAMTIMING2_t;
861 #endif /* __ASSEMBLY__ */
862 
863 /* The byte offset of the ALT_SDR_CTL_DRAMTIMING2 register from the beginning of the component. */
864 #define ALT_SDR_CTL_DRAMTIMING2_OFST 0x8
865 
866 /*
867  * Register : DRAM Timings 3 Register - dramtiming3
868  *
869  * This register implements JEDEC standardized timing parameters. It should be
870  * programmed in clock cycles, for the value specified by the memory vendor.
871  *
872  * Register Layout
873  *
874  * Bits | Access | Reset | Description
875  * :--------|:-------|:--------|:--------------------------------
876  * [3:0] | RW | Unknown | Read to Precharge Time
877  * [8:4] | RW | Unknown | Activate to Precharge Time
878  * [14:9] | RW | Unknown | Row Cycle Time
879  * [18:15] | RW | Unknown | Mode Register Programming Delay
880  * [22:19] | RW | Unknown | CAS to CAS Delay
881  * [31:23] | ??? | 0x0 | *UNDEFINED*
882  *
883  */
884 /*
885  * Field : Read to Precharge Time - trtp
886  *
887  * The read to precharge timing parameter.
888  *
889  * Field Access Macros:
890  *
891  */
892 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */
893 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB 0
894 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */
895 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB 3
896 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */
897 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH 4
898 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */
899 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK 0x0000000f
900 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */
901 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK 0xfffffff0
902 /* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field is UNKNOWN. */
903 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET 0x0
904 /* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRTP field value from a register. */
905 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_GET(value) (((value) & 0x0000000f) >> 0)
906 /* Produces a ALT_SDR_CTL_DRAMTIMING3_TRTP register field value suitable for setting the register. */
907 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET(value) (((value) << 0) & 0x0000000f)
908 
909 /*
910  * Field : Activate to Precharge Time - tras
911  *
912  * The activate to precharge timing parameter.
913  *
914  * Field Access Macros:
915  *
916  */
917 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */
918 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB 4
919 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */
920 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB 8
921 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */
922 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH 5
923 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */
924 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK 0x000001f0
925 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */
926 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK 0xfffffe0f
927 /* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field is UNKNOWN. */
928 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET 0x0
929 /* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRAS field value from a register. */
930 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_GET(value) (((value) & 0x000001f0) >> 4)
931 /* Produces a ALT_SDR_CTL_DRAMTIMING3_TRAS register field value suitable for setting the register. */
932 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET(value) (((value) << 4) & 0x000001f0)
933 
934 /*
935  * Field : Row Cycle Time - trc
936  *
937  * The activate to activate timing parameter.
938  *
939  * Field Access Macros:
940  *
941  */
942 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */
943 #define ALT_SDR_CTL_DRAMTIMING3_TRC_LSB 9
944 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */
945 #define ALT_SDR_CTL_DRAMTIMING3_TRC_MSB 14
946 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */
947 #define ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH 6
948 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */
949 #define ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK 0x00007e00
950 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */
951 #define ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK 0xffff81ff
952 /* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRC register field is UNKNOWN. */
953 #define ALT_SDR_CTL_DRAMTIMING3_TRC_RESET 0x0
954 /* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRC field value from a register. */
955 #define ALT_SDR_CTL_DRAMTIMING3_TRC_GET(value) (((value) & 0x00007e00) >> 9)
956 /* Produces a ALT_SDR_CTL_DRAMTIMING3_TRC register field value suitable for setting the register. */
957 #define ALT_SDR_CTL_DRAMTIMING3_TRC_SET(value) (((value) << 9) & 0x00007e00)
958 
959 /*
960  * Field : Mode Register Programming Delay - tmrd
961  *
962  * Mode register timing parameter.
963  *
964  * Field Access Macros:
965  *
966  */
967 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */
968 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB 15
969 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */
970 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB 18
971 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */
972 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH 4
973 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */
974 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK 0x00078000
975 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */
976 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK 0xfff87fff
977 /* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field is UNKNOWN. */
978 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET 0x0
979 /* Extracts the ALT_SDR_CTL_DRAMTIMING3_TMRD field value from a register. */
980 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_GET(value) (((value) & 0x00078000) >> 15)
981 /* Produces a ALT_SDR_CTL_DRAMTIMING3_TMRD register field value suitable for setting the register. */
982 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET(value) (((value) << 15) & 0x00078000)
983 
984 /*
985  * Field : CAS to CAS Delay - tccd
986  *
987  * The CAS to CAS delay time.
988  *
989  * Field Access Macros:
990  *
991  */
992 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */
993 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB 19
994 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */
995 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB 22
996 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */
997 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH 4
998 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */
999 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK 0x00780000
1000 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */
1001 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK 0xff87ffff
1002 /* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field is UNKNOWN. */
1003 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET 0x0
1004 /* Extracts the ALT_SDR_CTL_DRAMTIMING3_TCCD field value from a register. */
1005 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_GET(value) (((value) & 0x00780000) >> 19)
1006 /* Produces a ALT_SDR_CTL_DRAMTIMING3_TCCD register field value suitable for setting the register. */
1007 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET(value) (((value) << 19) & 0x00780000)
1008 
1009 #ifndef __ASSEMBLY__
1010 /*
1011  * WARNING: The C register and register group struct declarations are provided for
1012  * convenience and illustrative purposes. They should, however, be used with
1013  * caution as the C language standard provides no guarantees about the alignment or
1014  * atomicity of device memory accesses. The recommended practice for writing
1015  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1016  * alt_write_word() functions.
1017  *
1018  * The struct declaration for register ALT_SDR_CTL_DRAMTIMING3.
1019  */
1020 struct ALT_SDR_CTL_DRAMTIMING3_s
1021 {
1022  uint32_t trtp : 4; /* Read to Precharge Time */
1023  uint32_t tras : 5; /* Activate to Precharge Time */
1024  uint32_t trc : 6; /* Row Cycle Time */
1025  uint32_t tmrd : 4; /* Mode Register Programming Delay */
1026  uint32_t tccd : 4; /* CAS to CAS Delay */
1027  uint32_t : 9; /* *UNDEFINED* */
1028 };
1029 
1030 /* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING3. */
1031 typedef volatile struct ALT_SDR_CTL_DRAMTIMING3_s ALT_SDR_CTL_DRAMTIMING3_t;
1032 #endif /* __ASSEMBLY__ */
1033 
1034 /* The byte offset of the ALT_SDR_CTL_DRAMTIMING3 register from the beginning of the component. */
1035 #define ALT_SDR_CTL_DRAMTIMING3_OFST 0xc
1036 
1037 /*
1038  * Register : DRAM Timings 4 Register - dramtiming4
1039  *
1040  * This register implements JEDEC standardized timing parameters. It should be
1041  * programmed in clock cycles, for the value specified by the memory vendor.
1042  *
1043  * Register Layout
1044  *
1045  * Bits | Access | Reset | Description
1046  * :--------|:-------|:--------|:-------------------------------
1047  * [9:0] | RW | Unknown | Self-refresh Exit
1048  * [19:10] | RW | Unknown | Power Down Exit
1049  * [23:20] | RW | Unknown | Minimum Low Power State Cycles
1050  * [31:24] | ??? | 0x0 | *UNDEFINED*
1051  *
1052  */
1053 /*
1054  * Field : Self-refresh Exit - selfrfshexit
1055  *
1056  * The self refresh exit cycles, tXS.
1057  *
1058  * Field Access Macros:
1059  *
1060  */
1061 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */
1062 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB 0
1063 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */
1064 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB 9
1065 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */
1066 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH 10
1067 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */
1068 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK 0x000003ff
1069 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */
1070 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK 0xfffffc00
1071 /* The reset value of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field is UNKNOWN. */
1072 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET 0x0
1073 /* Extracts the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT field value from a register. */
1074 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET(value) (((value) & 0x000003ff) >> 0)
1075 /* Produces a ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value suitable for setting the register. */
1076 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET(value) (((value) << 0) & 0x000003ff)
1077 
1078 /*
1079  * Field : Power Down Exit - pwrdownexit
1080  *
1081  * The power down exit cycles, tXPDLL.
1082  *
1083  * Field Access Macros:
1084  *
1085  */
1086 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */
1087 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB 10
1088 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */
1089 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB 19
1090 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */
1091 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH 10
1092 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */
1093 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK 0x000ffc00
1094 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */
1095 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK 0xfff003ff
1096 /* The reset value of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field is UNKNOWN. */
1097 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET 0x0
1098 /* Extracts the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT field value from a register. */
1099 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET(value) (((value) & 0x000ffc00) >> 10)
1100 /* Produces a ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value suitable for setting the register. */
1101 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET(value) (((value) << 10) & 0x000ffc00)
1102 
1103 /*
1104  * Field : Minimum Low Power State Cycles - minpwrsavecycles
1105  *
1106  * The minimum number of cycles to stay in a low power state. This applies to both
1107  * power down and self-refresh and should be set to the greater of tPD and tCKESR.
1108  *
1109  * Field Access Macros:
1110  *
1111  */
1112 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */
1113 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
1114 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */
1115 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB 23
1116 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */
1117 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH 4
1118 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */
1119 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK 0x00f00000
1120 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */
1121 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK 0xff0fffff
1122 /* The reset value of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field is UNKNOWN. */
1123 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET 0x0
1124 /* Extracts the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES field value from a register. */
1125 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET(value) (((value) & 0x00f00000) >> 20)
1126 /* Produces a ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value suitable for setting the register. */
1127 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET(value) (((value) << 20) & 0x00f00000)
1128 
1129 #ifndef __ASSEMBLY__
1130 /*
1131  * WARNING: The C register and register group struct declarations are provided for
1132  * convenience and illustrative purposes. They should, however, be used with
1133  * caution as the C language standard provides no guarantees about the alignment or
1134  * atomicity of device memory accesses. The recommended practice for writing
1135  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1136  * alt_write_word() functions.
1137  *
1138  * The struct declaration for register ALT_SDR_CTL_DRAMTIMING4.
1139  */
1140 struct ALT_SDR_CTL_DRAMTIMING4_s
1141 {
1142  uint32_t selfrfshexit : 10; /* Self-refresh Exit */
1143  uint32_t pwrdownexit : 10; /* Power Down Exit */
1144  uint32_t minpwrsavecycles : 4; /* Minimum Low Power State Cycles */
1145  uint32_t : 8; /* *UNDEFINED* */
1146 };
1147 
1148 /* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING4. */
1149 typedef volatile struct ALT_SDR_CTL_DRAMTIMING4_s ALT_SDR_CTL_DRAMTIMING4_t;
1150 #endif /* __ASSEMBLY__ */
1151 
1152 /* The byte offset of the ALT_SDR_CTL_DRAMTIMING4 register from the beginning of the component. */
1153 #define ALT_SDR_CTL_DRAMTIMING4_OFST 0x10
1154 
1155 /*
1156  * Register : Lower Power Timing Register - lowpwrtiming
1157  *
1158  * This register controls the behavior of the low power logic in the controller.
1159  *
1160  * Register Layout
1161  *
1162  * Bits | Access | Reset | Description
1163  * :--------|:-------|:--------|:---------------------------
1164  * [15:0] | RW | Unknown | Auto-power Down Cycles
1165  * [19:16] | RW | Unknown | Clock Disable Delay Cycles
1166  * [31:20] | ??? | 0x0 | *UNDEFINED*
1167  *
1168  */
1169 /*
1170  * Field : Auto-power Down Cycles - autopdcycles
1171  *
1172  * The number of idle clock cycles after which the controller should place the
1173  * memory into power-down mode.
1174  *
1175  * Field Access Macros:
1176  *
1177  */
1178 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */
1179 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
1180 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */
1181 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB 15
1182 /* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */
1183 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH 16
1184 /* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */
1185 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK 0x0000ffff
1186 /* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */
1187 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK 0xffff0000
1188 /* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field is UNKNOWN. */
1189 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET 0x0
1190 /* Extracts the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES field value from a register. */
1191 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET(value) (((value) & 0x0000ffff) >> 0)
1192 /* Produces a ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value suitable for setting the register. */
1193 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET(value) (((value) << 0) & 0x0000ffff)
1194 
1195 /*
1196  * Field : Clock Disable Delay Cycles - clkdisablecycles
1197  *
1198  * Set to a the number of clocks after the execution of an self-refresh to stop the
1199  * clock. This register is generally set based on PHY design latency and should
1200  * generally not be changed.
1201  *
1202  * Field Access Macros:
1203  *
1204  */
1205 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */
1206 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB 16
1207 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */
1208 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB 19
1209 /* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */
1210 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH 4
1211 /* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */
1212 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK 0x000f0000
1213 /* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */
1214 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK 0xfff0ffff
1215 /* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field is UNKNOWN. */
1216 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET 0x0
1217 /* Extracts the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES field value from a register. */
1218 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET(value) (((value) & 0x000f0000) >> 16)
1219 /* Produces a ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value suitable for setting the register. */
1220 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET(value) (((value) << 16) & 0x000f0000)
1221 
1222 #ifndef __ASSEMBLY__
1223 /*
1224  * WARNING: The C register and register group struct declarations are provided for
1225  * convenience and illustrative purposes. They should, however, be used with
1226  * caution as the C language standard provides no guarantees about the alignment or
1227  * atomicity of device memory accesses. The recommended practice for writing
1228  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1229  * alt_write_word() functions.
1230  *
1231  * The struct declaration for register ALT_SDR_CTL_LOWPWRTIMING.
1232  */
1233 struct ALT_SDR_CTL_LOWPWRTIMING_s
1234 {
1235  uint32_t autopdcycles : 16; /* Auto-power Down Cycles */
1236  uint32_t clkdisablecycles : 4; /* Clock Disable Delay Cycles */
1237  uint32_t : 12; /* *UNDEFINED* */
1238 };
1239 
1240 /* The typedef declaration for register ALT_SDR_CTL_LOWPWRTIMING. */
1241 typedef volatile struct ALT_SDR_CTL_LOWPWRTIMING_s ALT_SDR_CTL_LOWPWRTIMING_t;
1242 #endif /* __ASSEMBLY__ */
1243 
1244 /* The byte offset of the ALT_SDR_CTL_LOWPWRTIMING register from the beginning of the component. */
1245 #define ALT_SDR_CTL_LOWPWRTIMING_OFST 0x14
1246 
1247 /*
1248  * Register : ODT Control Register - dramodt
1249  *
1250  * This register controls which ODT pin is asserted during reads or writes. Bits
1251  * [1:0] control which ODT pin is asserted during to accesses to chip select 0,
1252  * bits [3:2] which ODT pin is asserted during accesses to chip select 1. For
1253  * example, a value of &quot;1001&quot; will cause ODT[0] to be asserted for
1254  * accesses to CS[0], and ODT[1] to be asserted for access to CS[1] pin. Set this
1255  * to &quot;0001&quot; if there is only one chip select available.
1256  *
1257  * Register Layout
1258  *
1259  * Bits | Access | Reset | Description
1260  * :-------|:-------|:--------|:------------------
1261  * [3:0] | RW | Unknown | Write ODT Control
1262  * [7:4] | RW | Unknown | Read ODT Control
1263  * [31:8] | ??? | 0x0 | *UNDEFINED*
1264  *
1265  */
1266 /*
1267  * Field : Write ODT Control - cfg_write_odt_chip
1268  *
1269  * This register controls which ODT pin is asserted during writes.
1270  *
1271  * Field Access Macros:
1272  *
1273  */
1274 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */
1275 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB 0
1276 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */
1277 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB 3
1278 /* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */
1279 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH 4
1280 /* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */
1281 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK 0x0000000f
1282 /* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */
1283 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK 0xfffffff0
1284 /* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field is UNKNOWN. */
1285 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET 0x0
1286 /* Extracts the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP field value from a register. */
1287 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000000f) >> 0)
1288 /* Produces a ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value suitable for setting the register. */
1289 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000000f)
1290 
1291 /*
1292  * Field : Read ODT Control - cfg_read_odt_chip
1293  *
1294  * This register controls which ODT pin is asserted during reads.
1295  *
1296  * Field Access Macros:
1297  *
1298  */
1299 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */
1300 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB 4
1301 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */
1302 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB 7
1303 /* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */
1304 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH 4
1305 /* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */
1306 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK 0x000000f0
1307 /* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */
1308 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK 0xffffff0f
1309 /* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field is UNKNOWN. */
1310 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET 0x0
1311 /* Extracts the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP field value from a register. */
1312 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET(value) (((value) & 0x000000f0) >> 4)
1313 /* Produces a ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value suitable for setting the register. */
1314 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET(value) (((value) << 4) & 0x000000f0)
1315 
1316 #ifndef __ASSEMBLY__
1317 /*
1318  * WARNING: The C register and register group struct declarations are provided for
1319  * convenience and illustrative purposes. They should, however, be used with
1320  * caution as the C language standard provides no guarantees about the alignment or
1321  * atomicity of device memory accesses. The recommended practice for writing
1322  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1323  * alt_write_word() functions.
1324  *
1325  * The struct declaration for register ALT_SDR_CTL_DRAMODT.
1326  */
1327 struct ALT_SDR_CTL_DRAMODT_s
1328 {
1329  uint32_t cfg_write_odt_chip : 4; /* Write ODT Control */
1330  uint32_t cfg_read_odt_chip : 4; /* Read ODT Control */
1331  uint32_t : 24; /* *UNDEFINED* */
1332 };
1333 
1334 /* The typedef declaration for register ALT_SDR_CTL_DRAMODT. */
1335 typedef volatile struct ALT_SDR_CTL_DRAMODT_s ALT_SDR_CTL_DRAMODT_t;
1336 #endif /* __ASSEMBLY__ */
1337 
1338 /* The byte offset of the ALT_SDR_CTL_DRAMODT register from the beginning of the component. */
1339 #define ALT_SDR_CTL_DRAMODT_OFST 0x18
1340 
1341 /*
1342  * Register : DRAM Address Widths Register - dramaddrw
1343  *
1344  * This register configures the width of the various address fields of the DRAM.
1345  * The values specified in this register must match the memory devices being used.
1346  *
1347  * Register Layout
1348  *
1349  * Bits | Access | Reset | Description
1350  * :--------|:-------|:--------|:-------------------------
1351  * [4:0] | RW | Unknown | DRAM Column Address Bits
1352  * [9:5] | RW | Unknown | DRAM Row Address Bits
1353  * [12:10] | RW | Unknown | DRAM Bank Address Bits
1354  * [15:13] | RW | Unknown | DRAM Chip Address Bits
1355  * [31:16] | ??? | 0x0 | *UNDEFINED*
1356  *
1357  */
1358 /*
1359  * Field : DRAM Column Address Bits - colbits
1360  *
1361  * The number of column address bits for the memory devices in your memory
1362  * interface.
1363  *
1364  * Field Access Macros:
1365  *
1366  */
1367 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */
1368 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_LSB 0
1369 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */
1370 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_MSB 4
1371 /* The width in bits of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */
1372 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_WIDTH 5
1373 /* The mask used to set the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */
1374 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET_MSK 0x0000001f
1375 /* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */
1376 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_CLR_MSK 0xffffffe0
1377 /* The reset value of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field is UNKNOWN. */
1378 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_RESET 0x0
1379 /* Extracts the ALT_SDR_CTL_DRAMADDRW_COLBITS field value from a register. */
1380 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_GET(value) (((value) & 0x0000001f) >> 0)
1381 /* Produces a ALT_SDR_CTL_DRAMADDRW_COLBITS register field value suitable for setting the register. */
1382 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET(value) (((value) << 0) & 0x0000001f)
1383 
1384 /*
1385  * Field : DRAM Row Address Bits - rowbits
1386  *
1387  * The number of row address bits for the memory devices in your memory interface.
1388  *
1389  * Field Access Macros:
1390  *
1391  */
1392 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */
1393 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_LSB 5
1394 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */
1395 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_MSB 9
1396 /* The width in bits of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */
1397 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_WIDTH 5
1398 /* The mask used to set the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */
1399 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET_MSK 0x000003e0
1400 /* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */
1401 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_CLR_MSK 0xfffffc1f
1402 /* The reset value of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field is UNKNOWN. */
1403 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_RESET 0x0
1404 /* Extracts the ALT_SDR_CTL_DRAMADDRW_ROWBITS field value from a register. */
1405 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_GET(value) (((value) & 0x000003e0) >> 5)
1406 /* Produces a ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value suitable for setting the register. */
1407 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET(value) (((value) << 5) & 0x000003e0)
1408 
1409 /*
1410  * Field : DRAM Bank Address Bits - bankbits
1411  *
1412  * The number of bank address bits for the memory devices in your memory interface.
1413  *
1414  * Field Access Macros:
1415  *
1416  */
1417 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */
1418 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_LSB 10
1419 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */
1420 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_MSB 12
1421 /* The width in bits of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */
1422 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_WIDTH 3
1423 /* The mask used to set the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */
1424 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET_MSK 0x00001c00
1425 /* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */
1426 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_CLR_MSK 0xffffe3ff
1427 /* The reset value of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field is UNKNOWN. */
1428 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_RESET 0x0
1429 /* Extracts the ALT_SDR_CTL_DRAMADDRW_BANKBITS field value from a register. */
1430 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_GET(value) (((value) & 0x00001c00) >> 10)
1431 /* Produces a ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value suitable for setting the register. */
1432 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET(value) (((value) << 10) & 0x00001c00)
1433 
1434 /*
1435  * Field : DRAM Chip Address Bits - csbits
1436  *
1437  * The number of chip select address bits for the memory devices in your memory
1438  * interface.
1439  *
1440  * Field Access Macros:
1441  *
1442  */
1443 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */
1444 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_LSB 13
1445 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */
1446 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_MSB 15
1447 /* The width in bits of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */
1448 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_WIDTH 3
1449 /* The mask used to set the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */
1450 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET_MSK 0x0000e000
1451 /* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */
1452 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_CLR_MSK 0xffff1fff
1453 /* The reset value of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field is UNKNOWN. */
1454 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_RESET 0x0
1455 /* Extracts the ALT_SDR_CTL_DRAMADDRW_CSBITS field value from a register. */
1456 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_GET(value) (((value) & 0x0000e000) >> 13)
1457 /* Produces a ALT_SDR_CTL_DRAMADDRW_CSBITS register field value suitable for setting the register. */
1458 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET(value) (((value) << 13) & 0x0000e000)
1459 
1460 #ifndef __ASSEMBLY__
1461 /*
1462  * WARNING: The C register and register group struct declarations are provided for
1463  * convenience and illustrative purposes. They should, however, be used with
1464  * caution as the C language standard provides no guarantees about the alignment or
1465  * atomicity of device memory accesses. The recommended practice for writing
1466  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1467  * alt_write_word() functions.
1468  *
1469  * The struct declaration for register ALT_SDR_CTL_DRAMADDRW.
1470  */
1471 struct ALT_SDR_CTL_DRAMADDRW_s
1472 {
1473  uint32_t colbits : 5; /* DRAM Column Address Bits */
1474  uint32_t rowbits : 5; /* DRAM Row Address Bits */
1475  uint32_t bankbits : 3; /* DRAM Bank Address Bits */
1476  uint32_t csbits : 3; /* DRAM Chip Address Bits */
1477  uint32_t : 16; /* *UNDEFINED* */
1478 };
1479 
1480 /* The typedef declaration for register ALT_SDR_CTL_DRAMADDRW. */
1481 typedef volatile struct ALT_SDR_CTL_DRAMADDRW_s ALT_SDR_CTL_DRAMADDRW_t;
1482 #endif /* __ASSEMBLY__ */
1483 
1484 /* The byte offset of the ALT_SDR_CTL_DRAMADDRW register from the beginning of the component. */
1485 #define ALT_SDR_CTL_DRAMADDRW_OFST 0x2c
1486 
1487 /*
1488  * Register : DRAM Interface Data Width Register - dramifwidth
1489  *
1490  *
1491  * Register Layout
1492  *
1493  * Bits | Access | Reset | Description
1494  * :-------|:-------|:--------|:--------------------------
1495  * [7:0] | RW | Unknown | DRAM Interface Data Width
1496  * [31:8] | ??? | 0x0 | *UNDEFINED*
1497  *
1498  */
1499 /*
1500  * Field : DRAM Interface Data Width - ifwidth
1501  *
1502  * This register controls the interface width of the SDRAM interface, including any
1503  * bits used for ECC. For example, for a 32-bit interface with ECC, program this
1504  * register with 0x28. You must also program the ctrlwidth register.
1505  *
1506  * Field Access Macros:
1507  *
1508  */
1509 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */
1510 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_LSB 0
1511 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */
1512 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_MSB 7
1513 /* The width in bits of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */
1514 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_WIDTH 8
1515 /* The mask used to set the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */
1516 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET_MSK 0x000000ff
1517 /* The mask used to clear the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */
1518 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_CLR_MSK 0xffffff00
1519 /* The reset value of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field is UNKNOWN. */
1520 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_RESET 0x0
1521 /* Extracts the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH field value from a register. */
1522 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_GET(value) (((value) & 0x000000ff) >> 0)
1523 /* Produces a ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value suitable for setting the register. */
1524 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET(value) (((value) << 0) & 0x000000ff)
1525 
1526 #ifndef __ASSEMBLY__
1527 /*
1528  * WARNING: The C register and register group struct declarations are provided for
1529  * convenience and illustrative purposes. They should, however, be used with
1530  * caution as the C language standard provides no guarantees about the alignment or
1531  * atomicity of device memory accesses. The recommended practice for writing
1532  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1533  * alt_write_word() functions.
1534  *
1535  * The struct declaration for register ALT_SDR_CTL_DRAMIFWIDTH.
1536  */
1537 struct ALT_SDR_CTL_DRAMIFWIDTH_s
1538 {
1539  uint32_t ifwidth : 8; /* DRAM Interface Data Width */
1540  uint32_t : 24; /* *UNDEFINED* */
1541 };
1542 
1543 /* The typedef declaration for register ALT_SDR_CTL_DRAMIFWIDTH. */
1544 typedef volatile struct ALT_SDR_CTL_DRAMIFWIDTH_s ALT_SDR_CTL_DRAMIFWIDTH_t;
1545 #endif /* __ASSEMBLY__ */
1546 
1547 /* The byte offset of the ALT_SDR_CTL_DRAMIFWIDTH register from the beginning of the component. */
1548 #define ALT_SDR_CTL_DRAMIFWIDTH_OFST 0x30
1549 
1550 /*
1551  * Register : DRAM Devices Data Width Register - dramdevwidth
1552  *
1553  *
1554  * Register Layout
1555  *
1556  * Bits | Access | Reset | Description
1557  * :-------|:-------|:--------|:------------------------
1558  * [3:0] | RW | Unknown | DRAM Devices Data Width
1559  * [31:4] | ??? | 0x0 | *UNDEFINED*
1560  *
1561  */
1562 /*
1563  * Field : DRAM Devices Data Width - devwidth
1564  *
1565  * This register specifies the width of the physical DRAM chips, for example 8 or
1566  * 16.
1567  *
1568  * Field Access Macros:
1569  *
1570  */
1571 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */
1572 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_LSB 0
1573 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */
1574 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_MSB 3
1575 /* The width in bits of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */
1576 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_WIDTH 4
1577 /* The mask used to set the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */
1578 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET_MSK 0x0000000f
1579 /* The mask used to clear the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */
1580 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_CLR_MSK 0xfffffff0
1581 /* The reset value of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field is UNKNOWN. */
1582 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_RESET 0x0
1583 /* Extracts the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH field value from a register. */
1584 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_GET(value) (((value) & 0x0000000f) >> 0)
1585 /* Produces a ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value suitable for setting the register. */
1586 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET(value) (((value) << 0) & 0x0000000f)
1587 
1588 #ifndef __ASSEMBLY__
1589 /*
1590  * WARNING: The C register and register group struct declarations are provided for
1591  * convenience and illustrative purposes. They should, however, be used with
1592  * caution as the C language standard provides no guarantees about the alignment or
1593  * atomicity of device memory accesses. The recommended practice for writing
1594  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1595  * alt_write_word() functions.
1596  *
1597  * The struct declaration for register ALT_SDR_CTL_DRAMDEVWIDTH.
1598  */
1599 struct ALT_SDR_CTL_DRAMDEVWIDTH_s
1600 {
1601  uint32_t devwidth : 4; /* DRAM Devices Data Width */
1602  uint32_t : 28; /* *UNDEFINED* */
1603 };
1604 
1605 /* The typedef declaration for register ALT_SDR_CTL_DRAMDEVWIDTH. */
1606 typedef volatile struct ALT_SDR_CTL_DRAMDEVWIDTH_s ALT_SDR_CTL_DRAMDEVWIDTH_t;
1607 #endif /* __ASSEMBLY__ */
1608 
1609 /* The byte offset of the ALT_SDR_CTL_DRAMDEVWIDTH register from the beginning of the component. */
1610 #define ALT_SDR_CTL_DRAMDEVWIDTH_OFST 0x34
1611 
1612 /*
1613  * Register : DRAM Status Register - dramsts
1614  *
1615  * This register provides the status of the calibration and ECC logic.
1616  *
1617  * Register Layout
1618  *
1619  * Bits | Access | Reset | Description
1620  * :-------|:-------|:--------|:----------------------------
1621  * [0] | RW | Unknown | PHY Calibration Successful
1622  * [1] | RW | Unknown | PHY Calibration Failed
1623  * [2] | RW | Unknown | Single Bit Error Seen
1624  * [3] | RW | Unknown | Double Bit Error Seen
1625  * [4] | RW | Unknown | ECC Auto-Correction Dropped
1626  * [31:5] | ??? | 0x0 | *UNDEFINED*
1627  *
1628  */
1629 /*
1630  * Field : PHY Calibration Successful - calsuccess
1631  *
1632  * This bit will be set to 1 if the PHY was able to successfully calibrate.
1633  *
1634  * Field Access Macros:
1635  *
1636  */
1637 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */
1638 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_LSB 0
1639 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */
1640 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_MSB 0
1641 /* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */
1642 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_WIDTH 1
1643 /* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */
1644 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET_MSK 0x00000001
1645 /* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */
1646 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_CLR_MSK 0xfffffffe
1647 /* The reset value of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field is UNKNOWN. */
1648 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_RESET 0x0
1649 /* Extracts the ALT_SDR_CTL_DRAMSTS_CALSUCCESS field value from a register. */
1650 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_GET(value) (((value) & 0x00000001) >> 0)
1651 /* Produces a ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value suitable for setting the register. */
1652 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET(value) (((value) << 0) & 0x00000001)
1653 
1654 /*
1655  * Field : PHY Calibration Failed - calfail
1656  *
1657  * This bit will be set to 1 if the PHY was unable to calibrate.
1658  *
1659  * Field Access Macros:
1660  *
1661  */
1662 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */
1663 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_LSB 1
1664 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */
1665 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_MSB 1
1666 /* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */
1667 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_WIDTH 1
1668 /* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */
1669 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET_MSK 0x00000002
1670 /* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */
1671 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_CLR_MSK 0xfffffffd
1672 /* The reset value of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field is UNKNOWN. */
1673 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_RESET 0x0
1674 /* Extracts the ALT_SDR_CTL_DRAMSTS_CALFAIL field value from a register. */
1675 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_GET(value) (((value) & 0x00000002) >> 1)
1676 /* Produces a ALT_SDR_CTL_DRAMSTS_CALFAIL register field value suitable for setting the register. */
1677 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET(value) (((value) << 1) & 0x00000002)
1678 
1679 /*
1680  * Field : Single Bit Error Seen - sbeerr
1681  *
1682  * This bit will be set to 1 if there have been any ECC single bit errors detected.
1683  *
1684  * Field Access Macros:
1685  *
1686  */
1687 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */
1688 #define ALT_SDR_CTL_DRAMSTS_SBEERR_LSB 2
1689 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */
1690 #define ALT_SDR_CTL_DRAMSTS_SBEERR_MSB 2
1691 /* The width in bits of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */
1692 #define ALT_SDR_CTL_DRAMSTS_SBEERR_WIDTH 1
1693 /* The mask used to set the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */
1694 #define ALT_SDR_CTL_DRAMSTS_SBEERR_SET_MSK 0x00000004
1695 /* The mask used to clear the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */
1696 #define ALT_SDR_CTL_DRAMSTS_SBEERR_CLR_MSK 0xfffffffb
1697 /* The reset value of the ALT_SDR_CTL_DRAMSTS_SBEERR register field is UNKNOWN. */
1698 #define ALT_SDR_CTL_DRAMSTS_SBEERR_RESET 0x0
1699 /* Extracts the ALT_SDR_CTL_DRAMSTS_SBEERR field value from a register. */
1700 #define ALT_SDR_CTL_DRAMSTS_SBEERR_GET(value) (((value) & 0x00000004) >> 2)
1701 /* Produces a ALT_SDR_CTL_DRAMSTS_SBEERR register field value suitable for setting the register. */
1702 #define ALT_SDR_CTL_DRAMSTS_SBEERR_SET(value) (((value) << 2) & 0x00000004)
1703 
1704 /*
1705  * Field : Double Bit Error Seen - dbeerr
1706  *
1707  * This bit will be set to 1 if there have been any ECC double bit errors detected.
1708  *
1709  * Field Access Macros:
1710  *
1711  */
1712 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */
1713 #define ALT_SDR_CTL_DRAMSTS_DBEERR_LSB 3
1714 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */
1715 #define ALT_SDR_CTL_DRAMSTS_DBEERR_MSB 3
1716 /* The width in bits of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */
1717 #define ALT_SDR_CTL_DRAMSTS_DBEERR_WIDTH 1
1718 /* The mask used to set the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */
1719 #define ALT_SDR_CTL_DRAMSTS_DBEERR_SET_MSK 0x00000008
1720 /* The mask used to clear the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */
1721 #define ALT_SDR_CTL_DRAMSTS_DBEERR_CLR_MSK 0xfffffff7
1722 /* The reset value of the ALT_SDR_CTL_DRAMSTS_DBEERR register field is UNKNOWN. */
1723 #define ALT_SDR_CTL_DRAMSTS_DBEERR_RESET 0x0
1724 /* Extracts the ALT_SDR_CTL_DRAMSTS_DBEERR field value from a register. */
1725 #define ALT_SDR_CTL_DRAMSTS_DBEERR_GET(value) (((value) & 0x00000008) >> 3)
1726 /* Produces a ALT_SDR_CTL_DRAMSTS_DBEERR register field value suitable for setting the register. */
1727 #define ALT_SDR_CTL_DRAMSTS_DBEERR_SET(value) (((value) << 3) & 0x00000008)
1728 
1729 /*
1730  * Field : ECC Auto-Correction Dropped - corrdrop
1731  *
1732  * This bit will be set to 1 if there any auto-corrections have been dropped.
1733  *
1734  * Field Access Macros:
1735  *
1736  */
1737 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */
1738 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_LSB 4
1739 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */
1740 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_MSB 4
1741 /* The width in bits of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */
1742 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_WIDTH 1
1743 /* The mask used to set the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */
1744 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET_MSK 0x00000010
1745 /* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */
1746 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_CLR_MSK 0xffffffef
1747 /* The reset value of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field is UNKNOWN. */
1748 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_RESET 0x0
1749 /* Extracts the ALT_SDR_CTL_DRAMSTS_CORRDROP field value from a register. */
1750 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_GET(value) (((value) & 0x00000010) >> 4)
1751 /* Produces a ALT_SDR_CTL_DRAMSTS_CORRDROP register field value suitable for setting the register. */
1752 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET(value) (((value) << 4) & 0x00000010)
1753 
1754 #ifndef __ASSEMBLY__
1755 /*
1756  * WARNING: The C register and register group struct declarations are provided for
1757  * convenience and illustrative purposes. They should, however, be used with
1758  * caution as the C language standard provides no guarantees about the alignment or
1759  * atomicity of device memory accesses. The recommended practice for writing
1760  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1761  * alt_write_word() functions.
1762  *
1763  * The struct declaration for register ALT_SDR_CTL_DRAMSTS.
1764  */
1765 struct ALT_SDR_CTL_DRAMSTS_s
1766 {
1767  uint32_t calsuccess : 1; /* PHY Calibration Successful */
1768  uint32_t calfail : 1; /* PHY Calibration Failed */
1769  uint32_t sbeerr : 1; /* Single Bit Error Seen */
1770  uint32_t dbeerr : 1; /* Double Bit Error Seen */
1771  uint32_t corrdrop : 1; /* ECC Auto-Correction Dropped */
1772  uint32_t : 27; /* *UNDEFINED* */
1773 };
1774 
1775 /* The typedef declaration for register ALT_SDR_CTL_DRAMSTS. */
1776 typedef volatile struct ALT_SDR_CTL_DRAMSTS_s ALT_SDR_CTL_DRAMSTS_t;
1777 #endif /* __ASSEMBLY__ */
1778 
1779 /* The byte offset of the ALT_SDR_CTL_DRAMSTS register from the beginning of the component. */
1780 #define ALT_SDR_CTL_DRAMSTS_OFST 0x38
1781 
1782 /*
1783  * Register : ECC Interrupt Register - dramintr
1784  *
1785  *
1786  * Register Layout
1787  *
1788  * Bits | Access | Reset | Description
1789  * :-------|:-------|:--------|:---------------------------------------
1790  * [0] | RW | Unknown | Interrupt Enable
1791  * [1] | RW | Unknown | Mask Single Bit Error Interrupt
1792  * [2] | RW | Unknown | Mask Double Bit Error Interrupt
1793  * [3] | RW | Unknown | Mask Dropped Auto-correction Interrupt
1794  * [4] | RW | Unknown | Clear Interrupt Signal
1795  * [31:5] | ??? | 0x0 | *UNDEFINED*
1796  *
1797  */
1798 /*
1799  * Field : Interrupt Enable - intren
1800  *
1801  * Enable the interrupt output.
1802  *
1803  * Field Access Macros:
1804  *
1805  */
1806 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */
1807 #define ALT_SDR_CTL_DRAMINTR_INTREN_LSB 0
1808 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */
1809 #define ALT_SDR_CTL_DRAMINTR_INTREN_MSB 0
1810 /* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */
1811 #define ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH 1
1812 /* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */
1813 #define ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK 0x00000001
1814 /* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */
1815 #define ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK 0xfffffffe
1816 /* The reset value of the ALT_SDR_CTL_DRAMINTR_INTREN register field is UNKNOWN. */
1817 #define ALT_SDR_CTL_DRAMINTR_INTREN_RESET 0x0
1818 /* Extracts the ALT_SDR_CTL_DRAMINTR_INTREN field value from a register. */
1819 #define ALT_SDR_CTL_DRAMINTR_INTREN_GET(value) (((value) & 0x00000001) >> 0)
1820 /* Produces a ALT_SDR_CTL_DRAMINTR_INTREN register field value suitable for setting the register. */
1821 #define ALT_SDR_CTL_DRAMINTR_INTREN_SET(value) (((value) << 0) & 0x00000001)
1822 
1823 /*
1824  * Field : Mask Single Bit Error Interrupt - sbemask
1825  *
1826  * Mask the single bit error interrupt.
1827  *
1828  * Field Access Macros:
1829  *
1830  */
1831 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */
1832 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB 1
1833 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */
1834 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB 1
1835 /* The width in bits of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */
1836 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH 1
1837 /* The mask used to set the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */
1838 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK 0x00000002
1839 /* The mask used to clear the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */
1840 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK 0xfffffffd
1841 /* The reset value of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field is UNKNOWN. */
1842 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET 0x0
1843 /* Extracts the ALT_SDR_CTL_DRAMINTR_SBEMSK field value from a register. */
1844 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_GET(value) (((value) & 0x00000002) >> 1)
1845 /* Produces a ALT_SDR_CTL_DRAMINTR_SBEMSK register field value suitable for setting the register. */
1846 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET(value) (((value) << 1) & 0x00000002)
1847 
1848 /*
1849  * Field : Mask Double Bit Error Interrupt - dbemask
1850  *
1851  * Mask the double bit error interrupt.
1852  *
1853  * Field Access Macros:
1854  *
1855  */
1856 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */
1857 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB 2
1858 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */
1859 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB 2
1860 /* The width in bits of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */
1861 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH 1
1862 /* The mask used to set the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */
1863 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK 0x00000004
1864 /* The mask used to clear the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */
1865 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK 0xfffffffb
1866 /* The reset value of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field is UNKNOWN. */
1867 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET 0x0
1868 /* Extracts the ALT_SDR_CTL_DRAMINTR_DBEMSK field value from a register. */
1869 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_GET(value) (((value) & 0x00000004) >> 2)
1870 /* Produces a ALT_SDR_CTL_DRAMINTR_DBEMSK register field value suitable for setting the register. */
1871 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET(value) (((value) << 2) & 0x00000004)
1872 
1873 /*
1874  * Field : Mask Dropped Auto-correction Interrupt - corrdropmask
1875  *
1876  * Set this bit to a one to mask interrupts for an ECC correction write back
1877  * needing to be dropped. This indicates a burst of memory errors in a short
1878  * period of time.
1879  *
1880  * Field Access Macros:
1881  *
1882  */
1883 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */
1884 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB 3
1885 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */
1886 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB 3
1887 /* The width in bits of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */
1888 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH 1
1889 /* The mask used to set the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */
1890 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK 0x00000008
1891 /* The mask used to clear the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */
1892 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK 0xfffffff7
1893 /* The reset value of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field is UNKNOWN. */
1894 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET 0x0
1895 /* Extracts the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK field value from a register. */
1896 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET(value) (((value) & 0x00000008) >> 3)
1897 /* Produces a ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value suitable for setting the register. */
1898 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET(value) (((value) << 3) & 0x00000008)
1899 
1900 /*
1901  * Field : Clear Interrupt Signal - intrclr
1902  *
1903  * Writing to this self-clearing bit clears the interrupt signal. Writing to this
1904  * bit also clears the error count and error address registers.
1905  *
1906  * Field Access Macros:
1907  *
1908  */
1909 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */
1910 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB 4
1911 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */
1912 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB 4
1913 /* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */
1914 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH 1
1915 /* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */
1916 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK 0x00000010
1917 /* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */
1918 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK 0xffffffef
1919 /* The reset value of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field is UNKNOWN. */
1920 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET 0x0
1921 /* Extracts the ALT_SDR_CTL_DRAMINTR_INTRCLR field value from a register. */
1922 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_GET(value) (((value) & 0x00000010) >> 4)
1923 /* Produces a ALT_SDR_CTL_DRAMINTR_INTRCLR register field value suitable for setting the register. */
1924 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET(value) (((value) << 4) & 0x00000010)
1925 
1926 #ifndef __ASSEMBLY__
1927 /*
1928  * WARNING: The C register and register group struct declarations are provided for
1929  * convenience and illustrative purposes. They should, however, be used with
1930  * caution as the C language standard provides no guarantees about the alignment or
1931  * atomicity of device memory accesses. The recommended practice for writing
1932  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1933  * alt_write_word() functions.
1934  *
1935  * The struct declaration for register ALT_SDR_CTL_DRAMINTR.
1936  */
1937 struct ALT_SDR_CTL_DRAMINTR_s
1938 {
1939  uint32_t intren : 1; /* Interrupt Enable */
1940  uint32_t sbemask : 1; /* Mask Single Bit Error Interrupt */
1941  uint32_t dbemask : 1; /* Mask Double Bit Error Interrupt */
1942  uint32_t corrdropmask : 1; /* Mask Dropped Auto-correction Interrupt */
1943  uint32_t intrclr : 1; /* Clear Interrupt Signal */
1944  uint32_t : 27; /* *UNDEFINED* */
1945 };
1946 
1947 /* The typedef declaration for register ALT_SDR_CTL_DRAMINTR. */
1948 typedef volatile struct ALT_SDR_CTL_DRAMINTR_s ALT_SDR_CTL_DRAMINTR_t;
1949 #endif /* __ASSEMBLY__ */
1950 
1951 /* The byte offset of the ALT_SDR_CTL_DRAMINTR register from the beginning of the component. */
1952 #define ALT_SDR_CTL_DRAMINTR_OFST 0x3c
1953 
1954 /*
1955  * Register : ECC Single Bit Error Count Register - sbecount
1956  *
1957  *
1958  * Register Layout
1959  *
1960  * Bits | Access | Reset | Description
1961  * :-------|:-------|:--------|:-----------------------
1962  * [7:0] | RW | Unknown | Single Bit Error Count
1963  * [31:8] | ??? | 0x0 | *UNDEFINED*
1964  *
1965  */
1966 /*
1967  * Field : Single Bit Error Count - count
1968  *
1969  * Reports the number of single bit errors that have occurred since the status
1970  * register counters were last cleared.
1971  *
1972  * Field Access Macros:
1973  *
1974  */
1975 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */
1976 #define ALT_SDR_CTL_SBECOUNT_COUNT_LSB 0
1977 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */
1978 #define ALT_SDR_CTL_SBECOUNT_COUNT_MSB 7
1979 /* The width in bits of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */
1980 #define ALT_SDR_CTL_SBECOUNT_COUNT_WIDTH 8
1981 /* The mask used to set the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */
1982 #define ALT_SDR_CTL_SBECOUNT_COUNT_SET_MSK 0x000000ff
1983 /* The mask used to clear the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */
1984 #define ALT_SDR_CTL_SBECOUNT_COUNT_CLR_MSK 0xffffff00
1985 /* The reset value of the ALT_SDR_CTL_SBECOUNT_COUNT register field is UNKNOWN. */
1986 #define ALT_SDR_CTL_SBECOUNT_COUNT_RESET 0x0
1987 /* Extracts the ALT_SDR_CTL_SBECOUNT_COUNT field value from a register. */
1988 #define ALT_SDR_CTL_SBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0)
1989 /* Produces a ALT_SDR_CTL_SBECOUNT_COUNT register field value suitable for setting the register. */
1990 #define ALT_SDR_CTL_SBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff)
1991 
1992 #ifndef __ASSEMBLY__
1993 /*
1994  * WARNING: The C register and register group struct declarations are provided for
1995  * convenience and illustrative purposes. They should, however, be used with
1996  * caution as the C language standard provides no guarantees about the alignment or
1997  * atomicity of device memory accesses. The recommended practice for writing
1998  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1999  * alt_write_word() functions.
2000  *
2001  * The struct declaration for register ALT_SDR_CTL_SBECOUNT.
2002  */
2003 struct ALT_SDR_CTL_SBECOUNT_s
2004 {
2005  uint32_t count : 8; /* Single Bit Error Count */
2006  uint32_t : 24; /* *UNDEFINED* */
2007 };
2008 
2009 /* The typedef declaration for register ALT_SDR_CTL_SBECOUNT. */
2010 typedef volatile struct ALT_SDR_CTL_SBECOUNT_s ALT_SDR_CTL_SBECOUNT_t;
2011 #endif /* __ASSEMBLY__ */
2012 
2013 /* The byte offset of the ALT_SDR_CTL_SBECOUNT register from the beginning of the component. */
2014 #define ALT_SDR_CTL_SBECOUNT_OFST 0x40
2015 
2016 /*
2017  * Register : ECC Double Bit Error Count Register - dbecount
2018  *
2019  *
2020  * Register Layout
2021  *
2022  * Bits | Access | Reset | Description
2023  * :-------|:-------|:--------|:-----------------------
2024  * [7:0] | RW | Unknown | Double Bit Error Count
2025  * [31:8] | ??? | 0x0 | *UNDEFINED*
2026  *
2027  */
2028 /*
2029  * Field : Double Bit Error Count - count
2030  *
2031  * Reports the number of double bit errors that have occurred since the status
2032  * register counters were last cleared.
2033  *
2034  * Field Access Macros:
2035  *
2036  */
2037 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */
2038 #define ALT_SDR_CTL_DBECOUNT_COUNT_LSB 0
2039 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */
2040 #define ALT_SDR_CTL_DBECOUNT_COUNT_MSB 7
2041 /* The width in bits of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */
2042 #define ALT_SDR_CTL_DBECOUNT_COUNT_WIDTH 8
2043 /* The mask used to set the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */
2044 #define ALT_SDR_CTL_DBECOUNT_COUNT_SET_MSK 0x000000ff
2045 /* The mask used to clear the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */
2046 #define ALT_SDR_CTL_DBECOUNT_COUNT_CLR_MSK 0xffffff00
2047 /* The reset value of the ALT_SDR_CTL_DBECOUNT_COUNT register field is UNKNOWN. */
2048 #define ALT_SDR_CTL_DBECOUNT_COUNT_RESET 0x0
2049 /* Extracts the ALT_SDR_CTL_DBECOUNT_COUNT field value from a register. */
2050 #define ALT_SDR_CTL_DBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0)
2051 /* Produces a ALT_SDR_CTL_DBECOUNT_COUNT register field value suitable for setting the register. */
2052 #define ALT_SDR_CTL_DBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff)
2053 
2054 #ifndef __ASSEMBLY__
2055 /*
2056  * WARNING: The C register and register group struct declarations are provided for
2057  * convenience and illustrative purposes. They should, however, be used with
2058  * caution as the C language standard provides no guarantees about the alignment or
2059  * atomicity of device memory accesses. The recommended practice for writing
2060  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2061  * alt_write_word() functions.
2062  *
2063  * The struct declaration for register ALT_SDR_CTL_DBECOUNT.
2064  */
2065 struct ALT_SDR_CTL_DBECOUNT_s
2066 {
2067  uint32_t count : 8; /* Double Bit Error Count */
2068  uint32_t : 24; /* *UNDEFINED* */
2069 };
2070 
2071 /* The typedef declaration for register ALT_SDR_CTL_DBECOUNT. */
2072 typedef volatile struct ALT_SDR_CTL_DBECOUNT_s ALT_SDR_CTL_DBECOUNT_t;
2073 #endif /* __ASSEMBLY__ */
2074 
2075 /* The byte offset of the ALT_SDR_CTL_DBECOUNT register from the beginning of the component. */
2076 #define ALT_SDR_CTL_DBECOUNT_OFST 0x44
2077 
2078 /*
2079  * Register : ECC Error Address Register - erraddr
2080  *
2081  *
2082  * Register Layout
2083  *
2084  * Bits | Access | Reset | Description
2085  * :-------|:-------|:--------|:------------------
2086  * [31:0] | RW | Unknown | ECC Error Address
2087  *
2088  */
2089 /*
2090  * Field : ECC Error Address - addr
2091  *
2092  * The address of the most recent ECC error.
2093  *
2094  * Field Access Macros:
2095  *
2096  */
2097 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */
2098 #define ALT_SDR_CTL_ERRADDR_ADDR_LSB 0
2099 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */
2100 #define ALT_SDR_CTL_ERRADDR_ADDR_MSB 31
2101 /* The width in bits of the ALT_SDR_CTL_ERRADDR_ADDR register field. */
2102 #define ALT_SDR_CTL_ERRADDR_ADDR_WIDTH 32
2103 /* The mask used to set the ALT_SDR_CTL_ERRADDR_ADDR register field value. */
2104 #define ALT_SDR_CTL_ERRADDR_ADDR_SET_MSK 0xffffffff
2105 /* The mask used to clear the ALT_SDR_CTL_ERRADDR_ADDR register field value. */
2106 #define ALT_SDR_CTL_ERRADDR_ADDR_CLR_MSK 0x00000000
2107 /* The reset value of the ALT_SDR_CTL_ERRADDR_ADDR register field is UNKNOWN. */
2108 #define ALT_SDR_CTL_ERRADDR_ADDR_RESET 0x0
2109 /* Extracts the ALT_SDR_CTL_ERRADDR_ADDR field value from a register. */
2110 #define ALT_SDR_CTL_ERRADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
2111 /* Produces a ALT_SDR_CTL_ERRADDR_ADDR register field value suitable for setting the register. */
2112 #define ALT_SDR_CTL_ERRADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
2113 
2114 #ifndef __ASSEMBLY__
2115 /*
2116  * WARNING: The C register and register group struct declarations are provided for
2117  * convenience and illustrative purposes. They should, however, be used with
2118  * caution as the C language standard provides no guarantees about the alignment or
2119  * atomicity of device memory accesses. The recommended practice for writing
2120  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2121  * alt_write_word() functions.
2122  *
2123  * The struct declaration for register ALT_SDR_CTL_ERRADDR.
2124  */
2125 struct ALT_SDR_CTL_ERRADDR_s
2126 {
2127  uint32_t addr : 32; /* ECC Error Address */
2128 };
2129 
2130 /* The typedef declaration for register ALT_SDR_CTL_ERRADDR. */
2131 typedef volatile struct ALT_SDR_CTL_ERRADDR_s ALT_SDR_CTL_ERRADDR_t;
2132 #endif /* __ASSEMBLY__ */
2133 
2134 /* The byte offset of the ALT_SDR_CTL_ERRADDR register from the beginning of the component. */
2135 #define ALT_SDR_CTL_ERRADDR_OFST 0x48
2136 
2137 /*
2138  * Register : ECC Auto-correction Dropped Count Register - dropcount
2139  *
2140  *
2141  * Register Layout
2142  *
2143  * Bits | Access | Reset | Description
2144  * :-------|:-------|:--------|:------------------------------
2145  * [7:0] | RW | Unknown | Dropped Auto-correction Count
2146  * [31:8] | ??? | 0x0 | *UNDEFINED*
2147  *
2148  */
2149 /*
2150  * Field : Dropped Auto-correction Count - corrdropcount
2151  *
2152  * This gives the count of the number of ECC write back transactions dropped due to
2153  * the internal FIFO overflowing.
2154  *
2155  * Field Access Macros:
2156  *
2157  */
2158 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */
2159 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_LSB 0
2160 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */
2161 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_MSB 7
2162 /* The width in bits of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */
2163 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_WIDTH 8
2164 /* The mask used to set the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */
2165 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET_MSK 0x000000ff
2166 /* The mask used to clear the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */
2167 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_CLR_MSK 0xffffff00
2168 /* The reset value of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field is UNKNOWN. */
2169 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_RESET 0x0
2170 /* Extracts the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT field value from a register. */
2171 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_GET(value) (((value) & 0x000000ff) >> 0)
2172 /* Produces a ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value suitable for setting the register. */
2173 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET(value) (((value) << 0) & 0x000000ff)
2174 
2175 #ifndef __ASSEMBLY__
2176 /*
2177  * WARNING: The C register and register group struct declarations are provided for
2178  * convenience and illustrative purposes. They should, however, be used with
2179  * caution as the C language standard provides no guarantees about the alignment or
2180  * atomicity of device memory accesses. The recommended practice for writing
2181  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2182  * alt_write_word() functions.
2183  *
2184  * The struct declaration for register ALT_SDR_CTL_DROPCOUNT.
2185  */
2186 struct ALT_SDR_CTL_DROPCOUNT_s
2187 {
2188  uint32_t corrdropcount : 8; /* Dropped Auto-correction Count */
2189  uint32_t : 24; /* *UNDEFINED* */
2190 };
2191 
2192 /* The typedef declaration for register ALT_SDR_CTL_DROPCOUNT. */
2193 typedef volatile struct ALT_SDR_CTL_DROPCOUNT_s ALT_SDR_CTL_DROPCOUNT_t;
2194 #endif /* __ASSEMBLY__ */
2195 
2196 /* The byte offset of the ALT_SDR_CTL_DROPCOUNT register from the beginning of the component. */
2197 #define ALT_SDR_CTL_DROPCOUNT_OFST 0x4c
2198 
2199 /*
2200  * Register : ECC Auto-correction Dropped Address Register - dropaddr
2201  *
2202  *
2203  * Register Layout
2204  *
2205  * Bits | Access | Reset | Description
2206  * :-------|:-------|:--------|:--------------------------------
2207  * [31:0] | RW | Unknown | Dropped Auto-correction Address
2208  *
2209  */
2210 /*
2211  * Field : Dropped Auto-correction Address - corrdropaddr
2212  *
2213  * This register gives the last address which was dropped.
2214  *
2215  * Field Access Macros:
2216  *
2217  */
2218 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */
2219 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_LSB 0
2220 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */
2221 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_MSB 31
2222 /* The width in bits of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */
2223 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_WIDTH 32
2224 /* The mask used to set the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */
2225 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET_MSK 0xffffffff
2226 /* The mask used to clear the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */
2227 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_CLR_MSK 0x00000000
2228 /* The reset value of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field is UNKNOWN. */
2229 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_RESET 0x0
2230 /* Extracts the ALT_SDR_CTL_DROPADDR_CORRDROPADDR field value from a register. */
2231 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_GET(value) (((value) & 0xffffffff) >> 0)
2232 /* Produces a ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value suitable for setting the register. */
2233 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET(value) (((value) << 0) & 0xffffffff)
2234 
2235 #ifndef __ASSEMBLY__
2236 /*
2237  * WARNING: The C register and register group struct declarations are provided for
2238  * convenience and illustrative purposes. They should, however, be used with
2239  * caution as the C language standard provides no guarantees about the alignment or
2240  * atomicity of device memory accesses. The recommended practice for writing
2241  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2242  * alt_write_word() functions.
2243  *
2244  * The struct declaration for register ALT_SDR_CTL_DROPADDR.
2245  */
2246 struct ALT_SDR_CTL_DROPADDR_s
2247 {
2248  uint32_t corrdropaddr : 32; /* Dropped Auto-correction Address */
2249 };
2250 
2251 /* The typedef declaration for register ALT_SDR_CTL_DROPADDR. */
2252 typedef volatile struct ALT_SDR_CTL_DROPADDR_s ALT_SDR_CTL_DROPADDR_t;
2253 #endif /* __ASSEMBLY__ */
2254 
2255 /* The byte offset of the ALT_SDR_CTL_DROPADDR register from the beginning of the component. */
2256 #define ALT_SDR_CTL_DROPADDR_OFST 0x50
2257 
2258 /*
2259  * Register : Low Power Control Register - lowpwreq
2260  *
2261  * This register instructs the controller to put the DRAM into a power down state.
2262  * Note that some commands are only valid for certain memory types.
2263  *
2264  * Register Layout
2265  *
2266  * Bits | Access | Reset | Description
2267  * :-------|:-------|:--------|:---------------------------------
2268  * [0] | RW | Unknown | Deep Power Down Request
2269  * [2:1] | RW | Unknown | Deep Power Down Chip Select Mask
2270  * [3] | RW | Unknown | Self-refresh Request
2271  * [5:4] | RW | Unknown | Self-refresh Chip Select Mask
2272  * [31:6] | ??? | 0x0 | *UNDEFINED*
2273  *
2274  */
2275 /*
2276  * Field : Deep Power Down Request - deeppwrdnreq
2277  *
2278  * Write a one to this bit to request a deep power down. This bit should only be
2279  * written with LPDDR2 DRAMs, DDR3 DRAMs do not support deep power down.
2280  *
2281  * Field Access Macros:
2282  *
2283  */
2284 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */
2285 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB 0
2286 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */
2287 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB 0
2288 /* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */
2289 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH 1
2290 /* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */
2291 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK 0x00000001
2292 /* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */
2293 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK 0xfffffffe
2294 /* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field is UNKNOWN. */
2295 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET 0x0
2296 /* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ field value from a register. */
2297 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET(value) (((value) & 0x00000001) >> 0)
2298 /* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value suitable for setting the register. */
2299 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET(value) (((value) << 0) & 0x00000001)
2300 
2301 /*
2302  * Field : Deep Power Down Chip Select Mask - deeppwrdnmask
2303  *
2304  * Write ones to this register to select which DRAM chip selects will be powered
2305  * down. Typical usage is to set both of these bits when deeppwrdnreq is set but
2306  * the controller does support putting a single chip into deep power down and
2307  * keeping the other chip running.
2308  *
2309  * Field Access Macros:
2310  *
2311  */
2312 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */
2313 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB 1
2314 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */
2315 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB 2
2316 /* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */
2317 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH 2
2318 /* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */
2319 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK 0x00000006
2320 /* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */
2321 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK 0xfffffff9
2322 /* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field is UNKNOWN. */
2323 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET 0x0
2324 /* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK field value from a register. */
2325 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET(value) (((value) & 0x00000006) >> 1)
2326 /* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value suitable for setting the register. */
2327 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET(value) (((value) << 1) & 0x00000006)
2328 
2329 /*
2330  * Field : Self-refresh Request - selfrshreq
2331  *
2332  * Write a one to this bit to request the RAM be put into a self refresh state.
2333  * This bit is treated as a static value so the RAM will remain in self-refresh as
2334  * long as this register bit is set to a one. This power down mode can be selected
2335  * for all DRAMs supported by the controller.
2336  *
2337  * Field Access Macros:
2338  *
2339  */
2340 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */
2341 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB 3
2342 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */
2343 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB 3
2344 /* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */
2345 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH 1
2346 /* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */
2347 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK 0x00000008
2348 /* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */
2349 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK 0xfffffff7
2350 /* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field is UNKNOWN. */
2351 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET 0x0
2352 /* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ field value from a register. */
2353 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET(value) (((value) & 0x00000008) >> 3)
2354 /* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value suitable for setting the register. */
2355 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET(value) (((value) << 3) & 0x00000008)
2356 
2357 /*
2358  * Field : Self-refresh Chip Select Mask - selfrfshmask
2359  *
2360  * Write a one to each bit of this field to have a self refresh request apply to
2361  * both chips.
2362  *
2363  * Field Access Macros:
2364  *
2365  */
2366 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */
2367 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB 4
2368 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */
2369 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB 5
2370 /* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */
2371 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH 2
2372 /* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */
2373 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK 0x00000030
2374 /* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */
2375 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK 0xffffffcf
2376 /* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field is UNKNOWN. */
2377 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET 0x0
2378 /* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK field value from a register. */
2379 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET(value) (((value) & 0x00000030) >> 4)
2380 /* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value suitable for setting the register. */
2381 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET(value) (((value) << 4) & 0x00000030)
2382 
2383 #ifndef __ASSEMBLY__
2384 /*
2385  * WARNING: The C register and register group struct declarations are provided for
2386  * convenience and illustrative purposes. They should, however, be used with
2387  * caution as the C language standard provides no guarantees about the alignment or
2388  * atomicity of device memory accesses. The recommended practice for writing
2389  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2390  * alt_write_word() functions.
2391  *
2392  * The struct declaration for register ALT_SDR_CTL_LOWPWREQ.
2393  */
2394 struct ALT_SDR_CTL_LOWPWREQ_s
2395 {
2396  uint32_t deeppwrdnreq : 1; /* Deep Power Down Request */
2397  uint32_t deeppwrdnmask : 2; /* Deep Power Down Chip Select Mask */
2398  uint32_t selfrshreq : 1; /* Self-refresh Request */
2399  uint32_t selfrfshmask : 2; /* Self-refresh Chip Select Mask */
2400  uint32_t : 26; /* *UNDEFINED* */
2401 };
2402 
2403 /* The typedef declaration for register ALT_SDR_CTL_LOWPWREQ. */
2404 typedef volatile struct ALT_SDR_CTL_LOWPWREQ_s ALT_SDR_CTL_LOWPWREQ_t;
2405 #endif /* __ASSEMBLY__ */
2406 
2407 /* The byte offset of the ALT_SDR_CTL_LOWPWREQ register from the beginning of the component. */
2408 #define ALT_SDR_CTL_LOWPWREQ_OFST 0x54
2409 
2410 /*
2411  * Register : Low Power Acknowledge Register - lowpwrack
2412  *
2413  * This register gives the status of the power down commands requested by the Low
2414  * Power Control register.
2415  *
2416  * Register Layout
2417  *
2418  * Bits | Access | Reset | Description
2419  * :-------|:-------|:--------|:----------------------------
2420  * [0] | RW | Unknown | Deep Power Down Acknowledge
2421  * [1] | RW | Unknown | Self-refresh Acknowledge
2422  * [31:2] | ??? | 0x0 | *UNDEFINED*
2423  *
2424  */
2425 /*
2426  * Field : Deep Power Down Acknowledge - deeppwrdnack
2427  *
2428  * This bit is set to a one after a deep power down has been executed
2429  *
2430  * Field Access Macros:
2431  *
2432  */
2433 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */
2434 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB 0
2435 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */
2436 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB 0
2437 /* The width in bits of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */
2438 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH 1
2439 /* The mask used to set the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */
2440 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK 0x00000001
2441 /* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */
2442 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK 0xfffffffe
2443 /* The reset value of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field is UNKNOWN. */
2444 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET 0x0
2445 /* Extracts the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK field value from a register. */
2446 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET(value) (((value) & 0x00000001) >> 0)
2447 /* Produces a ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value suitable for setting the register. */
2448 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET(value) (((value) << 0) & 0x00000001)
2449 
2450 /*
2451  * Field : Self-refresh Acknowledge - selfrfshack
2452  *
2453  * This bit is a one to indicate that the controller is in a self-refresh state.
2454  *
2455  * Field Access Macros:
2456  *
2457  */
2458 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */
2459 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB 1
2460 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */
2461 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB 1
2462 /* The width in bits of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */
2463 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH 1
2464 /* The mask used to set the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */
2465 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK 0x00000002
2466 /* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */
2467 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK 0xfffffffd
2468 /* The reset value of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field is UNKNOWN. */
2469 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET 0x0
2470 /* Extracts the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK field value from a register. */
2471 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET(value) (((value) & 0x00000002) >> 1)
2472 /* Produces a ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value suitable for setting the register. */
2473 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET(value) (((value) << 1) & 0x00000002)
2474 
2475 #ifndef __ASSEMBLY__
2476 /*
2477  * WARNING: The C register and register group struct declarations are provided for
2478  * convenience and illustrative purposes. They should, however, be used with
2479  * caution as the C language standard provides no guarantees about the alignment or
2480  * atomicity of device memory accesses. The recommended practice for writing
2481  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2482  * alt_write_word() functions.
2483  *
2484  * The struct declaration for register ALT_SDR_CTL_LOWPWRACK.
2485  */
2486 struct ALT_SDR_CTL_LOWPWRACK_s
2487 {
2488  uint32_t deeppwrdnack : 1; /* Deep Power Down Acknowledge */
2489  uint32_t selfrfshack : 1; /* Self-refresh Acknowledge */
2490  uint32_t : 30; /* *UNDEFINED* */
2491 };
2492 
2493 /* The typedef declaration for register ALT_SDR_CTL_LOWPWRACK. */
2494 typedef volatile struct ALT_SDR_CTL_LOWPWRACK_s ALT_SDR_CTL_LOWPWRACK_t;
2495 #endif /* __ASSEMBLY__ */
2496 
2497 /* The byte offset of the ALT_SDR_CTL_LOWPWRACK register from the beginning of the component. */
2498 #define ALT_SDR_CTL_LOWPWRACK_OFST 0x58
2499 
2500 /*
2501  * Register : Static Configuration Register - staticcfg
2502  *
2503  * This register controls configuration values which cannot be updated while
2504  * transactions are flowing.
2505  *
2506  * You should write once to this register with the membl and eccen fields set to
2507  * your desired configuration, and then write to the register again with membl and
2508  * eccen and the applycfg bit set. The applycfg bit is write only.
2509  *
2510  * Register Layout
2511  *
2512  * Bits | Access | Reset | Description
2513  * :-------|:-------|:--------|:----------------------------
2514  * [1:0] | RW | Unknown | Memory Burst Length
2515  * [2] | RW | Unknown | Use ECC Bits As Data
2516  * [3] | RW | Unknown | Apply Configuration Changes
2517  * [31:4] | ??? | 0x0 | *UNDEFINED*
2518  *
2519  */
2520 /*
2521  * Field : Memory Burst Length - membl
2522  *
2523  * This field specifies the DRAM burst length. Write the following values to set
2524  * the a burst length appropriate for the specific DRAM being used. &quot;00&quot;
2525  * for burst length 2, &quot;01&quot; for burst length 4, &quot;10&quot; for burst
2526  * length 8. If you set this, you must also set the membl field in the ctrlcfg
2527  * register.
2528  *
2529  * Field Access Macros:
2530  *
2531  */
2532 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */
2533 #define ALT_SDR_CTL_STATICCFG_MEMBL_LSB 0
2534 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */
2535 #define ALT_SDR_CTL_STATICCFG_MEMBL_MSB 1
2536 /* The width in bits of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */
2537 #define ALT_SDR_CTL_STATICCFG_MEMBL_WIDTH 2
2538 /* The mask used to set the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */
2539 #define ALT_SDR_CTL_STATICCFG_MEMBL_SET_MSK 0x00000003
2540 /* The mask used to clear the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */
2541 #define ALT_SDR_CTL_STATICCFG_MEMBL_CLR_MSK 0xfffffffc
2542 /* The reset value of the ALT_SDR_CTL_STATICCFG_MEMBL register field is UNKNOWN. */
2543 #define ALT_SDR_CTL_STATICCFG_MEMBL_RESET 0x0
2544 /* Extracts the ALT_SDR_CTL_STATICCFG_MEMBL field value from a register. */
2545 #define ALT_SDR_CTL_STATICCFG_MEMBL_GET(value) (((value) & 0x00000003) >> 0)
2546 /* Produces a ALT_SDR_CTL_STATICCFG_MEMBL register field value suitable for setting the register. */
2547 #define ALT_SDR_CTL_STATICCFG_MEMBL_SET(value) (((value) << 0) & 0x00000003)
2548 
2549 /*
2550  * Field : Use ECC Bits As Data - useeccasdata
2551  *
2552  * This field allows the FPGA ports to directly access the extra data bits that are
2553  * normally used to hold the ECC code. The interface width must be set to 24 or 40
2554  * in the dramifwidth register. If you set this, you must clear the eccen field in
2555  * the ctrlcfg register.
2556  *
2557  * Field Access Macros:
2558  *
2559  */
2560 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */
2561 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_LSB 2
2562 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */
2563 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_MSB 2
2564 /* The width in bits of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */
2565 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_WIDTH 1
2566 /* The mask used to set the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */
2567 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET_MSK 0x00000004
2568 /* The mask used to clear the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */
2569 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_CLR_MSK 0xfffffffb
2570 /* The reset value of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field is UNKNOWN. */
2571 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_RESET 0x0
2572 /* Extracts the ALT_SDR_CTL_STATICCFG_USEECCASDATA field value from a register. */
2573 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_GET(value) (((value) & 0x00000004) >> 2)
2574 /* Produces a ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value suitable for setting the register. */
2575 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET(value) (((value) << 2) & 0x00000004)
2576 
2577 /*
2578  * Field : Apply Configuration Changes - applycfg
2579  *
2580  * Write with this bit set to apply all the settings loaded in SDR registers to the
2581  * memory interface. This bit is write-only and always returns 0 if read.
2582  *
2583  * Field Access Macros:
2584  *
2585  */
2586 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */
2587 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_LSB 3
2588 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */
2589 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_MSB 3
2590 /* The width in bits of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */
2591 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_WIDTH 1
2592 /* The mask used to set the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */
2593 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET_MSK 0x00000008
2594 /* The mask used to clear the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */
2595 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_CLR_MSK 0xfffffff7
2596 /* The reset value of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field is UNKNOWN. */
2597 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_RESET 0x0
2598 /* Extracts the ALT_SDR_CTL_STATICCFG_APPLYCFG field value from a register. */
2599 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_GET(value) (((value) & 0x00000008) >> 3)
2600 /* Produces a ALT_SDR_CTL_STATICCFG_APPLYCFG register field value suitable for setting the register. */
2601 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET(value) (((value) << 3) & 0x00000008)
2602 
2603 #ifndef __ASSEMBLY__
2604 /*
2605  * WARNING: The C register and register group struct declarations are provided for
2606  * convenience and illustrative purposes. They should, however, be used with
2607  * caution as the C language standard provides no guarantees about the alignment or
2608  * atomicity of device memory accesses. The recommended practice for writing
2609  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2610  * alt_write_word() functions.
2611  *
2612  * The struct declaration for register ALT_SDR_CTL_STATICCFG.
2613  */
2614 struct ALT_SDR_CTL_STATICCFG_s
2615 {
2616  uint32_t membl : 2; /* Memory Burst Length */
2617  uint32_t useeccasdata : 1; /* Use ECC Bits As Data */
2618  uint32_t applycfg : 1; /* Apply Configuration Changes */
2619  uint32_t : 28; /* *UNDEFINED* */
2620 };
2621 
2622 /* The typedef declaration for register ALT_SDR_CTL_STATICCFG. */
2623 typedef volatile struct ALT_SDR_CTL_STATICCFG_s ALT_SDR_CTL_STATICCFG_t;
2624 #endif /* __ASSEMBLY__ */
2625 
2626 /* The byte offset of the ALT_SDR_CTL_STATICCFG register from the beginning of the component. */
2627 #define ALT_SDR_CTL_STATICCFG_OFST 0x5c
2628 
2629 /*
2630  * Register : Memory Controller Width Register - ctrlwidth
2631  *
2632  * This register controls the width of the physical DRAM interface.
2633  *
2634  * Register Layout
2635  *
2636  * Bits | Access | Reset | Description
2637  * :-------|:-------|:--------|:---------------------------
2638  * [1:0] | RW | Unknown | Controller Interface Width
2639  * [31:2] | ??? | 0x0 | *UNDEFINED*
2640  *
2641  */
2642 /*
2643  * Field : Controller Interface Width - ctrlwidth
2644  *
2645  * Specifies controller DRAM interface width, with the following encoding.
2646  * &quot;00&quot; for 8-bit, &quot;01&quot; for 16-bit (no ECC) or 24-bit (ECC
2647  * enabled), &quot;10&quot; for 32-bit (no ECC) or 40-bit (ECC enabled). You must
2648  * also program the dramifwidth register.
2649  *
2650  * Field Access Macros:
2651  *
2652  */
2653 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */
2654 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_LSB 0
2655 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */
2656 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_MSB 1
2657 /* The width in bits of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */
2658 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_WIDTH 2
2659 /* The mask used to set the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */
2660 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET_MSK 0x00000003
2661 /* The mask used to clear the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */
2662 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_CLR_MSK 0xfffffffc
2663 /* The reset value of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field is UNKNOWN. */
2664 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_RESET 0x0
2665 /* Extracts the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH field value from a register. */
2666 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_GET(value) (((value) & 0x00000003) >> 0)
2667 /* Produces a ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value suitable for setting the register. */
2668 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET(value) (((value) << 0) & 0x00000003)
2669 
2670 #ifndef __ASSEMBLY__
2671 /*
2672  * WARNING: The C register and register group struct declarations are provided for
2673  * convenience and illustrative purposes. They should, however, be used with
2674  * caution as the C language standard provides no guarantees about the alignment or
2675  * atomicity of device memory accesses. The recommended practice for writing
2676  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2677  * alt_write_word() functions.
2678  *
2679  * The struct declaration for register ALT_SDR_CTL_CTLWIDTH.
2680  */
2681 struct ALT_SDR_CTL_CTLWIDTH_s
2682 {
2683  uint32_t ctrlwidth : 2; /* Controller Interface Width */
2684  uint32_t : 30; /* *UNDEFINED* */
2685 };
2686 
2687 /* The typedef declaration for register ALT_SDR_CTL_CTLWIDTH. */
2688 typedef volatile struct ALT_SDR_CTL_CTLWIDTH_s ALT_SDR_CTL_CTLWIDTH_t;
2689 #endif /* __ASSEMBLY__ */
2690 
2691 /* The byte offset of the ALT_SDR_CTL_CTLWIDTH register from the beginning of the component. */
2692 #define ALT_SDR_CTL_CTLWIDTH_OFST 0x60
2693 
2694 /*
2695  * Register : Port Configuration Register - portcfg
2696  *
2697  * This register should be set to a zero in any bit which corresponds to a port
2698  * which does mostly sequential memory accesses. For ports with highly random
2699  * accesses, the bit should be set to a one.
2700  *
2701  * Register Layout
2702  *
2703  * Bits | Access | Reset | Description
2704  * :--------|:-------|:--------|:----------------------
2705  * [9:0] | ??? | Unknown | *UNDEFINED*
2706  * [19:10] | RW | Unknown | Auto-precharge Enable
2707  * [31:20] | ??? | 0x0 | *UNDEFINED*
2708  *
2709  */
2710 /*
2711  * Field : Auto-precharge Enable - autopchen
2712  *
2713  * One bit per control port. Set bit N to a 1 to have the controller request an
2714  * automatic precharge following bus command completion (close the row
2715  * automatically). Set to a zero to request that the controller attempt to keep a
2716  * row open. For random dominated operations this register should be set to a 1
2717  * for all active ports.
2718  *
2719  * Field Access Macros:
2720  *
2721  */
2722 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */
2723 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_LSB 10
2724 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */
2725 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_MSB 19
2726 /* The width in bits of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */
2727 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_WIDTH 10
2728 /* The mask used to set the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */
2729 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET_MSK 0x000ffc00
2730 /* The mask used to clear the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */
2731 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_CLR_MSK 0xfff003ff
2732 /* The reset value of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field is UNKNOWN. */
2733 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_RESET 0x0
2734 /* Extracts the ALT_SDR_CTL_PORTCFG_AUTOPCHEN field value from a register. */
2735 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_GET(value) (((value) & 0x000ffc00) >> 10)
2736 /* Produces a ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value suitable for setting the register. */
2737 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET(value) (((value) << 10) & 0x000ffc00)
2738 
2739 #ifndef __ASSEMBLY__
2740 /*
2741  * WARNING: The C register and register group struct declarations are provided for
2742  * convenience and illustrative purposes. They should, however, be used with
2743  * caution as the C language standard provides no guarantees about the alignment or
2744  * atomicity of device memory accesses. The recommended practice for writing
2745  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2746  * alt_write_word() functions.
2747  *
2748  * The struct declaration for register ALT_SDR_CTL_PORTCFG.
2749  */
2750 struct ALT_SDR_CTL_PORTCFG_s
2751 {
2752  uint32_t : 10; /* *UNDEFINED* */
2753  uint32_t autopchen : 10; /* Auto-precharge Enable */
2754  uint32_t : 12; /* *UNDEFINED* */
2755 };
2756 
2757 /* The typedef declaration for register ALT_SDR_CTL_PORTCFG. */
2758 typedef volatile struct ALT_SDR_CTL_PORTCFG_s ALT_SDR_CTL_PORTCFG_t;
2759 #endif /* __ASSEMBLY__ */
2760 
2761 /* The byte offset of the ALT_SDR_CTL_PORTCFG register from the beginning of the component. */
2762 #define ALT_SDR_CTL_PORTCFG_OFST 0x7c
2763 
2764 /*
2765  * Register : FPGA Ports Reset Control Register - fpgaportrst
2766  *
2767  * This register implements functionality to allow the CPU to control when the MPFE
2768  * will enable the ports to the FPGA fabric.
2769  *
2770  * Register Layout
2771  *
2772  * Bits | Access | Reset | Description
2773  * :--------|:-------|:--------|:-------------------
2774  * [13:0] | RW | Unknown | Port Reset Control
2775  * [31:14] | ??? | 0x0 | *UNDEFINED*
2776  *
2777  */
2778 /*
2779  * Field : Port Reset Control - portrstn
2780  *
2781  * This register should be written to with a 1 to enable the selected FPGA port to
2782  * exit reset. Writing a bit to a zero will stretch the port reset until the
2783  * register is written. Read data ports are connected to bits 3:0, with read data
2784  * port 0 at bit 0 to read data port 3 at bit 3. Write data ports 0 to 3 are mapped
2785  * to 4 to 7, with write data port 0 connected to bit 4 to write data port 3 at bit
2786  * 7. Command ports are connected to bits 8 to 13, with command port 0 at bit 8 to
2787  * command port 5 at bit 13. Expected usage would be to set all the bits at the
2788  * same time but setting some bits to a zero and others to a one is supported.
2789  *
2790  * Field Access Macros:
2791  *
2792  */
2793 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */
2794 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB 0
2795 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */
2796 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB 13
2797 /* The width in bits of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */
2798 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH 14
2799 /* The mask used to set the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */
2800 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK 0x00003fff
2801 /* The mask used to clear the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */
2802 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK 0xffffc000
2803 /* The reset value of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field is UNKNOWN. */
2804 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET 0x0
2805 /* Extracts the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN field value from a register. */
2806 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET(value) (((value) & 0x00003fff) >> 0)
2807 /* Produces a ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value suitable for setting the register. */
2808 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET(value) (((value) << 0) & 0x00003fff)
2809 
2810 #ifndef __ASSEMBLY__
2811 /*
2812  * WARNING: The C register and register group struct declarations are provided for
2813  * convenience and illustrative purposes. They should, however, be used with
2814  * caution as the C language standard provides no guarantees about the alignment or
2815  * atomicity of device memory accesses. The recommended practice for writing
2816  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2817  * alt_write_word() functions.
2818  *
2819  * The struct declaration for register ALT_SDR_CTL_FPGAPORTRST.
2820  */
2821 struct ALT_SDR_CTL_FPGAPORTRST_s
2822 {
2823  uint32_t portrstn : 14; /* Port Reset Control */
2824  uint32_t : 18; /* *UNDEFINED* */
2825 };
2826 
2827 /* The typedef declaration for register ALT_SDR_CTL_FPGAPORTRST. */
2828 typedef volatile struct ALT_SDR_CTL_FPGAPORTRST_s ALT_SDR_CTL_FPGAPORTRST_t;
2829 #endif /* __ASSEMBLY__ */
2830 
2831 /* The byte offset of the ALT_SDR_CTL_FPGAPORTRST register from the beginning of the component. */
2832 #define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80
2833 
2834 /*
2835  * Register : Memory Protection Port Default Register - protportdefault
2836  *
2837  * This register controls the default protection assignment for a port. Ports
2838  * which have explicit rules which define regions which are illegal to access
2839  * should set the bits to pass by default. Ports which have explicit rules which
2840  * define legal areas should set the bit to force all transactions to fail.
2841  * Leaving this register to all zeros should be used for systems which do not
2842  * desire any protection from the memory controller.
2843  *
2844  * Register Layout
2845  *
2846  * Bits | Access | Reset | Description
2847  * :--------|:-------|:--------|:--------------------
2848  * [9:0] | RW | Unknown | Port Default Action
2849  * [31:10] | ??? | 0x0 | *UNDEFINED*
2850  *
2851  */
2852 /*
2853  * Field : Port Default Action - portdefault
2854  *
2855  * Determines the default action for a transactions from a port. Set a bit to a
2856  * zero to indicate that all accesses from the port should pass by default, set a
2857  * bit to a one if the default protection is to fail the access.
2858  *
2859  * Field Access Macros:
2860  *
2861  */
2862 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */
2863 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_LSB 0
2864 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */
2865 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_MSB 9
2866 /* The width in bits of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */
2867 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_WIDTH 10
2868 /* The mask used to set the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */
2869 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET_MSK 0x000003ff
2870 /* The mask used to clear the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */
2871 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_CLR_MSK 0xfffffc00
2872 /* The reset value of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field is UNKNOWN. */
2873 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_RESET 0x0
2874 /* Extracts the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT field value from a register. */
2875 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_GET(value) (((value) & 0x000003ff) >> 0)
2876 /* Produces a ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value suitable for setting the register. */
2877 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET(value) (((value) << 0) & 0x000003ff)
2878 
2879 #ifndef __ASSEMBLY__
2880 /*
2881  * WARNING: The C register and register group struct declarations are provided for
2882  * convenience and illustrative purposes. They should, however, be used with
2883  * caution as the C language standard provides no guarantees about the alignment or
2884  * atomicity of device memory accesses. The recommended practice for writing
2885  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2886  * alt_write_word() functions.
2887  *
2888  * The struct declaration for register ALT_SDR_CTL_PROTPORTDEFAULT.
2889  */
2890 struct ALT_SDR_CTL_PROTPORTDEFAULT_s
2891 {
2892  uint32_t portdefault : 10; /* Port Default Action */
2893  uint32_t : 22; /* *UNDEFINED* */
2894 };
2895 
2896 /* The typedef declaration for register ALT_SDR_CTL_PROTPORTDEFAULT. */
2897 typedef volatile struct ALT_SDR_CTL_PROTPORTDEFAULT_s ALT_SDR_CTL_PROTPORTDEFAULT_t;
2898 #endif /* __ASSEMBLY__ */
2899 
2900 /* The byte offset of the ALT_SDR_CTL_PROTPORTDEFAULT register from the beginning of the component. */
2901 #define ALT_SDR_CTL_PROTPORTDEFAULT_OFST 0x8c
2902 
2903 /*
2904  * Register : Memory Protection Address Register - protruleaddr
2905  *
2906  * This register is used to control the memory protection for port 0 transactions.
2907  * Address ranges can either be used to allow access to memory regions or disallow
2908  * access to memory regions. If trustzone is being used, access can be enabled for
2909  * protected transactions or disabled for unprotected transactions. The default
2910  * state of this register is to allow all access. Address values used for
2911  * protection are only physical addresses.
2912  *
2913  * Register Layout
2914  *
2915  * Bits | Access | Reset | Description
2916  * :--------|:-------|:--------|:-------------
2917  * [11:0] | RW | Unknown | Low Address
2918  * [23:12] | RW | Unknown | High Address
2919  * [31:24] | ??? | 0x0 | *UNDEFINED*
2920  *
2921  */
2922 /*
2923  * Field : Low Address - lowaddr
2924  *
2925  * Lower 12 bits of the address for a check. Address is compared to be less than
2926  * or equal to the address of a transaction. Note that since AXI transactions
2927  * cannot cross a 4K byte boundary, the transaction start and transaction end
2928  * address must also fall within the same 1MByte block pointed to by this address
2929  * pointer.
2930  *
2931  * Field Access Macros:
2932  *
2933  */
2934 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */
2935 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_LSB 0
2936 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */
2937 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_MSB 11
2938 /* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */
2939 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_WIDTH 12
2940 /* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */
2941 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET_MSK 0x00000fff
2942 /* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */
2943 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_CLR_MSK 0xfffff000
2944 /* The reset value of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field is UNKNOWN. */
2945 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_RESET 0x0
2946 /* Extracts the ALT_SDR_CTL_PROTRULEADDR_LOWADDR field value from a register. */
2947 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_GET(value) (((value) & 0x00000fff) >> 0)
2948 /* Produces a ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value suitable for setting the register. */
2949 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET(value) (((value) << 0) & 0x00000fff)
2950 
2951 /*
2952  * Field : High Address - highaddr
2953  *
2954  * Upper 12 bits of the address for a check. Address is compared to be greater
2955  * than or equal to the address of a transaction. Note that since AXI transactions
2956  * cannot cross a 4K byte boundary, the transaction start and transaction end
2957  * address must also fall within the same 1MByte block pointed to by this address
2958  * pointer.
2959  *
2960  * Field Access Macros:
2961  *
2962  */
2963 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */
2964 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_LSB 12
2965 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */
2966 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_MSB 23
2967 /* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */
2968 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_WIDTH 12
2969 /* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */
2970 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET_MSK 0x00fff000
2971 /* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */
2972 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_CLR_MSK 0xff000fff
2973 /* The reset value of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field is UNKNOWN. */
2974 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_RESET 0x0
2975 /* Extracts the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR field value from a register. */
2976 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_GET(value) (((value) & 0x00fff000) >> 12)
2977 /* Produces a ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value suitable for setting the register. */
2978 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET(value) (((value) << 12) & 0x00fff000)
2979 
2980 #ifndef __ASSEMBLY__
2981 /*
2982  * WARNING: The C register and register group struct declarations are provided for
2983  * convenience and illustrative purposes. They should, however, be used with
2984  * caution as the C language standard provides no guarantees about the alignment or
2985  * atomicity of device memory accesses. The recommended practice for writing
2986  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2987  * alt_write_word() functions.
2988  *
2989  * The struct declaration for register ALT_SDR_CTL_PROTRULEADDR.
2990  */
2991 struct ALT_SDR_CTL_PROTRULEADDR_s
2992 {
2993  uint32_t lowaddr : 12; /* Low Address */
2994  uint32_t highaddr : 12; /* High Address */
2995  uint32_t : 8; /* *UNDEFINED* */
2996 };
2997 
2998 /* The typedef declaration for register ALT_SDR_CTL_PROTRULEADDR. */
2999 typedef volatile struct ALT_SDR_CTL_PROTRULEADDR_s ALT_SDR_CTL_PROTRULEADDR_t;
3000 #endif /* __ASSEMBLY__ */
3001 
3002 /* The byte offset of the ALT_SDR_CTL_PROTRULEADDR register from the beginning of the component. */
3003 #define ALT_SDR_CTL_PROTRULEADDR_OFST 0x90
3004 
3005 /*
3006  * Register : Memory Protection ID Register - protruleid
3007  *
3008  *
3009  * Register Layout
3010  *
3011  * Bits | Access | Reset | Description
3012  * :--------|:-------|:--------|:------------
3013  * [11:0] | RW | Unknown | Low ID
3014  * [23:12] | RW | Unknown | High ID
3015  * [31:24] | ??? | 0x0 | *UNDEFINED*
3016  *
3017  */
3018 /*
3019  * Field : Low ID - lowid
3020  *
3021  * AxID for the protection rule. Incoming AxID needs to be greater than or equal
3022  * to this value. For all AxIDs from a port, AxID high should be programmed to all
3023  * ones.
3024  *
3025  * Field Access Macros:
3026  *
3027  */
3028 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */
3029 #define ALT_SDR_CTL_PROTRULEID_LOWID_LSB 0
3030 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */
3031 #define ALT_SDR_CTL_PROTRULEID_LOWID_MSB 11
3032 /* The width in bits of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */
3033 #define ALT_SDR_CTL_PROTRULEID_LOWID_WIDTH 12
3034 /* The mask used to set the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */
3035 #define ALT_SDR_CTL_PROTRULEID_LOWID_SET_MSK 0x00000fff
3036 /* The mask used to clear the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */
3037 #define ALT_SDR_CTL_PROTRULEID_LOWID_CLR_MSK 0xfffff000
3038 /* The reset value of the ALT_SDR_CTL_PROTRULEID_LOWID register field is UNKNOWN. */
3039 #define ALT_SDR_CTL_PROTRULEID_LOWID_RESET 0x0
3040 /* Extracts the ALT_SDR_CTL_PROTRULEID_LOWID field value from a register. */
3041 #define ALT_SDR_CTL_PROTRULEID_LOWID_GET(value) (((value) & 0x00000fff) >> 0)
3042 /* Produces a ALT_SDR_CTL_PROTRULEID_LOWID register field value suitable for setting the register. */
3043 #define ALT_SDR_CTL_PROTRULEID_LOWID_SET(value) (((value) << 0) & 0x00000fff)
3044 
3045 /*
3046  * Field : High ID - highid
3047  *
3048  * AxID for the protection rule. Incoming AxID needs to be less than or equal to
3049  * this value. For all AxIDs from a port, AxID high should be programmed to all
3050  * ones.
3051  *
3052  * Field Access Macros:
3053  *
3054  */
3055 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */
3056 #define ALT_SDR_CTL_PROTRULEID_HIGHID_LSB 12
3057 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */
3058 #define ALT_SDR_CTL_PROTRULEID_HIGHID_MSB 23
3059 /* The width in bits of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */
3060 #define ALT_SDR_CTL_PROTRULEID_HIGHID_WIDTH 12
3061 /* The mask used to set the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */
3062 #define ALT_SDR_CTL_PROTRULEID_HIGHID_SET_MSK 0x00fff000
3063 /* The mask used to clear the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */
3064 #define ALT_SDR_CTL_PROTRULEID_HIGHID_CLR_MSK 0xff000fff
3065 /* The reset value of the ALT_SDR_CTL_PROTRULEID_HIGHID register field is UNKNOWN. */
3066 #define ALT_SDR_CTL_PROTRULEID_HIGHID_RESET 0x0
3067 /* Extracts the ALT_SDR_CTL_PROTRULEID_HIGHID field value from a register. */
3068 #define ALT_SDR_CTL_PROTRULEID_HIGHID_GET(value) (((value) & 0x00fff000) >> 12)
3069 /* Produces a ALT_SDR_CTL_PROTRULEID_HIGHID register field value suitable for setting the register. */
3070 #define ALT_SDR_CTL_PROTRULEID_HIGHID_SET(value) (((value) << 12) & 0x00fff000)
3071 
3072 #ifndef __ASSEMBLY__
3073 /*
3074  * WARNING: The C register and register group struct declarations are provided for
3075  * convenience and illustrative purposes. They should, however, be used with
3076  * caution as the C language standard provides no guarantees about the alignment or
3077  * atomicity of device memory accesses. The recommended practice for writing
3078  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3079  * alt_write_word() functions.
3080  *
3081  * The struct declaration for register ALT_SDR_CTL_PROTRULEID.
3082  */
3083 struct ALT_SDR_CTL_PROTRULEID_s
3084 {
3085  uint32_t lowid : 12; /* Low ID */
3086  uint32_t highid : 12; /* High ID */
3087  uint32_t : 8; /* *UNDEFINED* */
3088 };
3089 
3090 /* The typedef declaration for register ALT_SDR_CTL_PROTRULEID. */
3091 typedef volatile struct ALT_SDR_CTL_PROTRULEID_s ALT_SDR_CTL_PROTRULEID_t;
3092 #endif /* __ASSEMBLY__ */
3093 
3094 /* The byte offset of the ALT_SDR_CTL_PROTRULEID register from the beginning of the component. */
3095 #define ALT_SDR_CTL_PROTRULEID_OFST 0x94
3096 
3097 /*
3098  * Register : Memory Protection Rule Data Register - protruledata
3099  *
3100  *
3101  * Register Layout
3102  *
3103  * Bits | Access | Reset | Description
3104  * :--------|:-------|:--------|:----------------------
3105  * [1:0] | RW | Unknown | Security Bit Behavior
3106  * [2] | RW | Unknown | Valid Rule
3107  * [12:3] | RW | Unknown | Port Mask
3108  * [13] | RW | Unknown | Rule Results
3109  * [31:14] | ??? | 0x0 | *UNDEFINED*
3110  *
3111  */
3112 /*
3113  * Field : Security Bit Behavior - security
3114  *
3115  * A value of 2'b00 will make the rule apply to secure transactions.
3116  *
3117  * A value of 2'b01 will make the rule apply to non-secure transactions.
3118  *
3119  * A value of 2'b10 or 2'b11 will make the rule apply to secure and non-secure
3120  * transactions.
3121  *
3122  * Field Access Macros:
3123  *
3124  */
3125 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */
3126 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_LSB 0
3127 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */
3128 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_MSB 1
3129 /* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */
3130 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_WIDTH 2
3131 /* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */
3132 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET_MSK 0x00000003
3133 /* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */
3134 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_CLR_MSK 0xfffffffc
3135 /* The reset value of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field is UNKNOWN. */
3136 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_RESET 0x0
3137 /* Extracts the ALT_SDR_CTL_PROTRULEDATA_SECURITY field value from a register. */
3138 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_GET(value) (((value) & 0x00000003) >> 0)
3139 /* Produces a ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value suitable for setting the register. */
3140 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET(value) (((value) << 0) & 0x00000003)
3141 
3142 /*
3143  * Field : Valid Rule - validrule
3144  *
3145  * Set to bit to a one to make a rule valid, set to a zero to invalidate a rule.
3146  *
3147  * Field Access Macros:
3148  *
3149  */
3150 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */
3151 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_LSB 2
3152 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */
3153 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_MSB 2
3154 /* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */
3155 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_WIDTH 1
3156 /* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */
3157 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET_MSK 0x00000004
3158 /* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */
3159 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_CLR_MSK 0xfffffffb
3160 /* The reset value of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field is UNKNOWN. */
3161 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_RESET 0x0
3162 /* Extracts the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE field value from a register. */
3163 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_GET(value) (((value) & 0x00000004) >> 2)
3164 /* Produces a ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value suitable for setting the register. */
3165 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET(value) (((value) << 2) & 0x00000004)
3166 
3167 /*
3168  * Field : Port Mask - portmask
3169  *
3170  * Set bit x to a one to have this rule apply to port x, set bit x to a zero to
3171  * have the rule not apply to a port.&#10;Note that port 0-port 5 are the FPGA
3172  * fabric ports, port 6 is L3 read, port 7 is CPU read, port 8 is L3 write, port 9
3173  * is CPU write.
3174  *
3175  * Field Access Macros:
3176  *
3177  */
3178 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */
3179 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_LSB 3
3180 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */
3181 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_MSB 12
3182 /* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */
3183 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_WIDTH 10
3184 /* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */
3185 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET_MSK 0x00001ff8
3186 /* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */
3187 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_CLR_MSK 0xffffe007
3188 /* The reset value of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field is UNKNOWN. */
3189 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_RESET 0x0
3190 /* Extracts the ALT_SDR_CTL_PROTRULEDATA_PORTMSK field value from a register. */
3191 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_GET(value) (((value) & 0x00001ff8) >> 3)
3192 /* Produces a ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value suitable for setting the register. */
3193 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET(value) (((value) << 3) & 0x00001ff8)
3194 
3195 /*
3196  * Field : Rule Results - ruleresult
3197  *
3198  * Set this bit to a one to force a protection failure, zero to allow the access
3199  * the succeed
3200  *
3201  * Field Access Macros:
3202  *
3203  */
3204 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */
3205 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_LSB 13
3206 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */
3207 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_MSB 13
3208 /* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */
3209 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_WIDTH 1
3210 /* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */
3211 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET_MSK 0x00002000
3212 /* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */
3213 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_CLR_MSK 0xffffdfff
3214 /* The reset value of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field is UNKNOWN. */
3215 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_RESET 0x0
3216 /* Extracts the ALT_SDR_CTL_PROTRULEDATA_RULERESULT field value from a register. */
3217 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_GET(value) (((value) & 0x00002000) >> 13)
3218 /* Produces a ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value suitable for setting the register. */
3219 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET(value) (((value) << 13) & 0x00002000)
3220 
3221 #ifndef __ASSEMBLY__
3222 /*
3223  * WARNING: The C register and register group struct declarations are provided for
3224  * convenience and illustrative purposes. They should, however, be used with
3225  * caution as the C language standard provides no guarantees about the alignment or
3226  * atomicity of device memory accesses. The recommended practice for writing
3227  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3228  * alt_write_word() functions.
3229  *
3230  * The struct declaration for register ALT_SDR_CTL_PROTRULEDATA.
3231  */
3232 struct ALT_SDR_CTL_PROTRULEDATA_s
3233 {
3234  uint32_t security : 2; /* Security Bit Behavior */
3235  uint32_t validrule : 1; /* Valid Rule */
3236  uint32_t portmask : 10; /* Port Mask */
3237  uint32_t ruleresult : 1; /* Rule Results */
3238  uint32_t : 18; /* *UNDEFINED* */
3239 };
3240 
3241 /* The typedef declaration for register ALT_SDR_CTL_PROTRULEDATA. */
3242 typedef volatile struct ALT_SDR_CTL_PROTRULEDATA_s ALT_SDR_CTL_PROTRULEDATA_t;
3243 #endif /* __ASSEMBLY__ */
3244 
3245 /* The byte offset of the ALT_SDR_CTL_PROTRULEDATA register from the beginning of the component. */
3246 #define ALT_SDR_CTL_PROTRULEDATA_OFST 0x98
3247 
3248 /*
3249  * Register : Memory Protection Rule Read-Write Register - protrulerdwr
3250  *
3251  * This register is used to perform read and write operations to the internal
3252  * protection table.
3253  *
3254  * Register Layout
3255  *
3256  * Bits | Access | Reset | Description
3257  * :-------|:-------|:--------|:------------
3258  * [4:0] | RW | Unknown | Rule Offset
3259  * [5] | RW | Unknown | Rule Write
3260  * [6] | RW | Unknown | Rule Read
3261  * [31:7] | ??? | 0x0 | *UNDEFINED*
3262  *
3263  */
3264 /*
3265  * Field : Rule Offset - ruleoffset
3266  *
3267  * This field defines which of the 20 rules in the protection table you want to
3268  * read or write.
3269  *
3270  * Field Access Macros:
3271  *
3272  */
3273 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */
3274 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB 0
3275 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */
3276 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB 4
3277 /* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */
3278 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH 5
3279 /* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */
3280 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK 0x0000001f
3281 /* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */
3282 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK 0xffffffe0
3283 /* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field is UNKNOWN. */
3284 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET 0x0
3285 /* Extracts the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET field value from a register. */
3286 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET(value) (((value) & 0x0000001f) >> 0)
3287 /* Produces a ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value suitable for setting the register. */
3288 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET(value) (((value) << 0) & 0x0000001f)
3289 
3290 /*
3291  * Field : Rule Write - writerule
3292  *
3293  * Write to this bit to have the memory_prot_data register to the table at the
3294  * offset specified by port_offset. Bit automatically clears after a single cycle
3295  * and the write operation is complete.
3296  *
3297  * Field Access Macros:
3298  *
3299  */
3300 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */
3301 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB 5
3302 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */
3303 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB 5
3304 /* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */
3305 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH 1
3306 /* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */
3307 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK 0x00000020
3308 /* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */
3309 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK 0xffffffdf
3310 /* The reset value of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field is UNKNOWN. */
3311 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET 0x0
3312 /* Extracts the ALT_SDR_CTL_PROTRULERDWR_WRRULE field value from a register. */
3313 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET(value) (((value) & 0x00000020) >> 5)
3314 /* Produces a ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value suitable for setting the register. */
3315 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET(value) (((value) << 5) & 0x00000020)
3316 
3317 /*
3318  * Field : Rule Read - readrule
3319  *
3320  * Write to this bit to have the memory_prot_data register loaded with the value
3321  * from the internal protection table at offset. Table value will be loaded before
3322  * a rdy is returned so read data from the register will be correct for any follow-
3323  * on reads to the memory_prot_data register.
3324  *
3325  * Field Access Macros:
3326  *
3327  */
3328 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */
3329 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB 6
3330 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */
3331 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB 6
3332 /* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */
3333 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH 1
3334 /* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */
3335 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK 0x00000040
3336 /* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */
3337 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK 0xffffffbf
3338 /* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field is UNKNOWN. */
3339 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET 0x0
3340 /* Extracts the ALT_SDR_CTL_PROTRULERDWR_RDRULE field value from a register. */
3341 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET(value) (((value) & 0x00000040) >> 6)
3342 /* Produces a ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value suitable for setting the register. */
3343 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET(value) (((value) << 6) & 0x00000040)
3344 
3345 #ifndef __ASSEMBLY__
3346 /*
3347  * WARNING: The C register and register group struct declarations are provided for
3348  * convenience and illustrative purposes. They should, however, be used with
3349  * caution as the C language standard provides no guarantees about the alignment or
3350  * atomicity of device memory accesses. The recommended practice for writing
3351  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3352  * alt_write_word() functions.
3353  *
3354  * The struct declaration for register ALT_SDR_CTL_PROTRULERDWR.
3355  */
3356 struct ALT_SDR_CTL_PROTRULERDWR_s
3357 {
3358  uint32_t ruleoffset : 5; /* Rule Offset */
3359  uint32_t writerule : 1; /* Rule Write */
3360  uint32_t readrule : 1; /* Rule Read */
3361  uint32_t : 25; /* *UNDEFINED* */
3362 };
3363 
3364 /* The typedef declaration for register ALT_SDR_CTL_PROTRULERDWR. */
3365 typedef volatile struct ALT_SDR_CTL_PROTRULERDWR_s ALT_SDR_CTL_PROTRULERDWR_t;
3366 #endif /* __ASSEMBLY__ */
3367 
3368 /* The byte offset of the ALT_SDR_CTL_PROTRULERDWR register from the beginning of the component. */
3369 #define ALT_SDR_CTL_PROTRULERDWR_OFST 0x9c
3370 
3371 /*
3372  * Register : QOS Control Register - qoslowpri
3373  *
3374  * This register controls the mapping of AXI4 QOS received from the FPGA fabric to
3375  * the internal priority used for traffic prioritization.
3376  *
3377  * Register Layout
3378  *
3379  * Bits | Access | Reset | Description
3380  * :--------|:-------|:--------|:-----------------------
3381  * [19:0] | RW | Unknown | Low Priority QoS Value
3382  * [31:20] | ??? | 0x0 | *UNDEFINED*
3383  *
3384  */
3385 /*
3386  * Field : Low Priority QoS Value - lowpriorityval
3387  *
3388  * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for
3389  * each port in this register controls the priority used for a port
3390  *
3391  * Field Access Macros:
3392  *
3393  */
3394 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */
3395 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_LSB 0
3396 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */
3397 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_MSB 19
3398 /* The width in bits of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */
3399 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_WIDTH 20
3400 /* The mask used to set the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */
3401 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET_MSK 0x000fffff
3402 /* The mask used to clear the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */
3403 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_CLR_MSK 0xfff00000
3404 /* The reset value of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field is UNKNOWN. */
3405 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_RESET 0x0
3406 /* Extracts the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL field value from a register. */
3407 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0)
3408 /* Produces a ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value suitable for setting the register. */
3409 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff)
3410 
3411 #ifndef __ASSEMBLY__
3412 /*
3413  * WARNING: The C register and register group struct declarations are provided for
3414  * convenience and illustrative purposes. They should, however, be used with
3415  * caution as the C language standard provides no guarantees about the alignment or
3416  * atomicity of device memory accesses. The recommended practice for writing
3417  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3418  * alt_write_word() functions.
3419  *
3420  * The struct declaration for register ALT_SDR_CTL_QOSLOWPRI.
3421  */
3422 struct ALT_SDR_CTL_QOSLOWPRI_s
3423 {
3424  uint32_t lowpriorityval : 20; /* Low Priority QoS Value */
3425  uint32_t : 12; /* *UNDEFINED* */
3426 };
3427 
3428 /* The typedef declaration for register ALT_SDR_CTL_QOSLOWPRI. */
3429 typedef volatile struct ALT_SDR_CTL_QOSLOWPRI_s ALT_SDR_CTL_QOSLOWPRI_t;
3430 #endif /* __ASSEMBLY__ */
3431 
3432 /* The byte offset of the ALT_SDR_CTL_QOSLOWPRI register from the beginning of the component. */
3433 #define ALT_SDR_CTL_QOSLOWPRI_OFST 0xa0
3434 
3435 /*
3436  * Register : qoshighpri Register - qoshighpri
3437  *
3438  *
3439  * Register Layout
3440  *
3441  * Bits | Access | Reset | Description
3442  * :--------|:-------|:--------|:------------------------
3443  * [19:0] | RW | Unknown | High Priority QoS Value
3444  * [31:20] | ??? | 0x0 | *UNDEFINED*
3445  *
3446  */
3447 /*
3448  * Field : High Priority QoS Value - highpriorityval
3449  *
3450  * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for
3451  * each port in this register controls the priority used for a port
3452  *
3453  * Field Access Macros:
3454  *
3455  */
3456 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */
3457 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_LSB 0
3458 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */
3459 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_MSB 19
3460 /* The width in bits of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */
3461 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_WIDTH 20
3462 /* The mask used to set the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */
3463 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET_MSK 0x000fffff
3464 /* The mask used to clear the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */
3465 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_CLR_MSK 0xfff00000
3466 /* The reset value of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field is UNKNOWN. */
3467 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_RESET 0x0
3468 /* Extracts the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL field value from a register. */
3469 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0)
3470 /* Produces a ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value suitable for setting the register. */
3471 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff)
3472 
3473 #ifndef __ASSEMBLY__
3474 /*
3475  * WARNING: The C register and register group struct declarations are provided for
3476  * convenience and illustrative purposes. They should, however, be used with
3477  * caution as the C language standard provides no guarantees about the alignment or
3478  * atomicity of device memory accesses. The recommended practice for writing
3479  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3480  * alt_write_word() functions.
3481  *
3482  * The struct declaration for register ALT_SDR_CTL_QOSHIGHPRI.
3483  */
3484 struct ALT_SDR_CTL_QOSHIGHPRI_s
3485 {
3486  uint32_t highpriorityval : 20; /* High Priority QoS Value */
3487  uint32_t : 12; /* *UNDEFINED* */
3488 };
3489 
3490 /* The typedef declaration for register ALT_SDR_CTL_QOSHIGHPRI. */
3491 typedef volatile struct ALT_SDR_CTL_QOSHIGHPRI_s ALT_SDR_CTL_QOSHIGHPRI_t;
3492 #endif /* __ASSEMBLY__ */
3493 
3494 /* The byte offset of the ALT_SDR_CTL_QOSHIGHPRI register from the beginning of the component. */
3495 #define ALT_SDR_CTL_QOSHIGHPRI_OFST 0xa4
3496 
3497 /*
3498  * Register : qospriorityen Register - qospriorityen
3499  *
3500  *
3501  * Register Layout
3502  *
3503  * Bits | Access | Reset | Description
3504  * :--------|:-------|:--------|:--------------------
3505  * [9:0] | RW | Unknown | Per-Port QoS Enable
3506  * [31:10] | ??? | 0x0 | *UNDEFINED*
3507  *
3508  */
3509 /*
3510  * Field : Per-Port QoS Enable - priorityen
3511  *
3512  * This 10 bit field is set to a one to enable QOS usage for a port.
3513  *
3514  * Field Access Macros:
3515  *
3516  */
3517 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */
3518 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_LSB 0
3519 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */
3520 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_MSB 9
3521 /* The width in bits of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */
3522 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_WIDTH 10
3523 /* The mask used to set the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */
3524 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET_MSK 0x000003ff
3525 /* The mask used to clear the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */
3526 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_CLR_MSK 0xfffffc00
3527 /* The reset value of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field is UNKNOWN. */
3528 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_RESET 0x0
3529 /* Extracts the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN field value from a register. */
3530 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_GET(value) (((value) & 0x000003ff) >> 0)
3531 /* Produces a ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value suitable for setting the register. */
3532 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET(value) (((value) << 0) & 0x000003ff)
3533 
3534 #ifndef __ASSEMBLY__
3535 /*
3536  * WARNING: The C register and register group struct declarations are provided for
3537  * convenience and illustrative purposes. They should, however, be used with
3538  * caution as the C language standard provides no guarantees about the alignment or
3539  * atomicity of device memory accesses. The recommended practice for writing
3540  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3541  * alt_write_word() functions.
3542  *
3543  * The struct declaration for register ALT_SDR_CTL_QOSPRIORITYEN.
3544  */
3545 struct ALT_SDR_CTL_QOSPRIORITYEN_s
3546 {
3547  uint32_t priorityen : 10; /* Per-Port QoS Enable */
3548  uint32_t : 22; /* *UNDEFINED* */
3549 };
3550 
3551 /* The typedef declaration for register ALT_SDR_CTL_QOSPRIORITYEN. */
3552 typedef volatile struct ALT_SDR_CTL_QOSPRIORITYEN_s ALT_SDR_CTL_QOSPRIORITYEN_t;
3553 #endif /* __ASSEMBLY__ */
3554 
3555 /* The byte offset of the ALT_SDR_CTL_QOSPRIORITYEN register from the beginning of the component. */
3556 #define ALT_SDR_CTL_QOSPRIORITYEN_OFST 0xa8
3557 
3558 /*
3559  * Register : Scheduler priority Register - mppriority
3560  *
3561  * This register is used to configure the DRAM burst operation scheduling.
3562  *
3563  * Register Layout
3564  *
3565  * Bits | Access | Reset | Description
3566  * :--------|:-------|:--------|:---------------------
3567  * [29:0] | RW | Unknown | Port User Priorities
3568  * [31:30] | ??? | 0x0 | *UNDEFINED*
3569  *
3570  */
3571 /*
3572  * Field : Port User Priorities - userpriority
3573  *
3574  * Set absolute user priority of the port. Each port is represented by a 3 bit
3575  * value, 000=lowest priority, 111=highest priority. Port 0 is bits 2:0. Port
3576  * number offset corresponds to the control port assignment.
3577  *
3578  * Field Access Macros:
3579  *
3580  */
3581 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */
3582 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_LSB 0
3583 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */
3584 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_MSB 29
3585 /* The width in bits of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */
3586 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_WIDTH 30
3587 /* The mask used to set the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */
3588 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET_MSK 0x3fffffff
3589 /* The mask used to clear the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */
3590 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_CLR_MSK 0xc0000000
3591 /* The reset value of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field is UNKNOWN. */
3592 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_RESET 0x0
3593 /* Extracts the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY field value from a register. */
3594 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_GET(value) (((value) & 0x3fffffff) >> 0)
3595 /* Produces a ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value suitable for setting the register. */
3596 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET(value) (((value) << 0) & 0x3fffffff)
3597 
3598 #ifndef __ASSEMBLY__
3599 /*
3600  * WARNING: The C register and register group struct declarations are provided for
3601  * convenience and illustrative purposes. They should, however, be used with
3602  * caution as the C language standard provides no guarantees about the alignment or
3603  * atomicity of device memory accesses. The recommended practice for writing
3604  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3605  * alt_write_word() functions.
3606  *
3607  * The struct declaration for register ALT_SDR_CTL_MPPRIORITY.
3608  */
3609 struct ALT_SDR_CTL_MPPRIORITY_s
3610 {
3611  uint32_t userpriority : 30; /* Port User Priorities */
3612  uint32_t : 2; /* *UNDEFINED* */
3613 };
3614 
3615 /* The typedef declaration for register ALT_SDR_CTL_MPPRIORITY. */
3616 typedef volatile struct ALT_SDR_CTL_MPPRIORITY_s ALT_SDR_CTL_MPPRIORITY_t;
3617 #endif /* __ASSEMBLY__ */
3618 
3619 /* The byte offset of the ALT_SDR_CTL_MPPRIORITY register from the beginning of the component. */
3620 #define ALT_SDR_CTL_MPPRIORITY_OFST 0xac
3621 
3622 /*
3623  * Register : Controller Command Pool Priority Remap Register - remappriority
3624  *
3625  * This register controls the priority for transactions in the controller command
3626  * pool.
3627  *
3628  * Register Layout
3629  *
3630  * Bits | Access | Reset | Description
3631  * :-------|:-------|:--------|:---------------
3632  * [7:0] | RW | Unknown | Priority Remap
3633  * [31:8] | ??? | 0x0 | *UNDEFINED*
3634  *
3635  */
3636 /*
3637  * Field : Priority Remap - priorityremap
3638  *
3639  * Set bit N of this register to the value to a one to enable the controller
3640  * command pool priority bit of a transaction from MPFE priority N
3641  *
3642  * Field Access Macros:
3643  *
3644  */
3645 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */
3646 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_LSB 0
3647 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */
3648 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_MSB 7
3649 /* The width in bits of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */
3650 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_WIDTH 8
3651 /* The mask used to set the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */
3652 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET_MSK 0x000000ff
3653 /* The mask used to clear the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */
3654 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_CLR_MSK 0xffffff00
3655 /* The reset value of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field is UNKNOWN. */
3656 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_RESET 0x0
3657 /* Extracts the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP field value from a register. */
3658 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_GET(value) (((value) & 0x000000ff) >> 0)
3659 /* Produces a ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value suitable for setting the register. */
3660 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET(value) (((value) << 0) & 0x000000ff)
3661 
3662 #ifndef __ASSEMBLY__
3663 /*
3664  * WARNING: The C register and register group struct declarations are provided for
3665  * convenience and illustrative purposes. They should, however, be used with
3666  * caution as the C language standard provides no guarantees about the alignment or
3667  * atomicity of device memory accesses. The recommended practice for writing
3668  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3669  * alt_write_word() functions.
3670  *
3671  * The struct declaration for register ALT_SDR_CTL_REMAPPRIORITY.
3672  */
3673 struct ALT_SDR_CTL_REMAPPRIORITY_s
3674 {
3675  uint32_t priorityremap : 8; /* Priority Remap */
3676  uint32_t : 24; /* *UNDEFINED* */
3677 };
3678 
3679 /* The typedef declaration for register ALT_SDR_CTL_REMAPPRIORITY. */
3680 typedef volatile struct ALT_SDR_CTL_REMAPPRIORITY_s ALT_SDR_CTL_REMAPPRIORITY_t;
3681 #endif /* __ASSEMBLY__ */
3682 
3683 /* The byte offset of the ALT_SDR_CTL_REMAPPRIORITY register from the beginning of the component. */
3684 #define ALT_SDR_CTL_REMAPPRIORITY_OFST 0xe0
3685 
3686 /*
3687  * Register Group : Port Sum of Weight Register - ALT_SDR_CTL_MPWT
3688  * Port Sum of Weight Register
3689  *
3690  * This register is used to configure the DRAM burst operation scheduling.
3691  *
3692  */
3693 /*
3694  * Register : Port Sum of Weight Register[1/4] - mpweight_0_4
3695  *
3696  * This register is used to configure the DRAM burst operation scheduling.
3697  *
3698  * Register Layout
3699  *
3700  * Bits | Access | Reset | Description
3701  * :-------|:-------|:--------|:--------------------------
3702  * [31:0] | RW | Unknown | Port Static Weights[31:0]
3703  *
3704  */
3705 /*
3706  * Field : Port Static Weights[31:0] - staticweight_31_0
3707  *
3708  * Set static weight of the port. Each port is programmed with a 5 bit value.
3709  * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45
3710  *
3711  * Field Access Macros:
3712  *
3713  */
3714 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */
3715 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_LSB 0
3716 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */
3717 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_MSB 31
3718 /* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */
3719 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_WIDTH 32
3720 /* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */
3721 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET_MSK 0xffffffff
3722 /* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */
3723 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_CLR_MSK 0x00000000
3724 /* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field is UNKNOWN. */
3725 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_RESET 0x0
3726 /* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 field value from a register. */
3727 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_GET(value) (((value) & 0xffffffff) >> 0)
3728 /* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value suitable for setting the register. */
3729 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET(value) (((value) << 0) & 0xffffffff)
3730 
3731 #ifndef __ASSEMBLY__
3732 /*
3733  * WARNING: The C register and register group struct declarations are provided for
3734  * convenience and illustrative purposes. They should, however, be used with
3735  * caution as the C language standard provides no guarantees about the alignment or
3736  * atomicity of device memory accesses. The recommended practice for writing
3737  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3738  * alt_write_word() functions.
3739  *
3740  * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4.
3741  */
3742 struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s
3743 {
3744  uint32_t staticweight_31_0 : 32; /* Port Static Weights[31:0] */
3745 };
3746 
3747 /* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4. */
3748 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t;
3749 #endif /* __ASSEMBLY__ */
3750 
3751 /* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register from the beginning of the component. */
3752 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST 0x0
3753 /* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register. */
3754 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST))
3755 
3756 /*
3757  * Register : Port Sum of Weight Register[2/4] - mpweight_1_4
3758  *
3759  * This register is used to configure the DRAM burst operation scheduling.
3760  *
3761  * Register Layout
3762  *
3763  * Bits | Access | Reset | Description
3764  * :--------|:-------|:--------|:---------------------------
3765  * [17:0] | RW | Unknown | Port Static Weights[49:32]
3766  * [31:18] | RW | Unknown | Port Sum of Weights[13:0]
3767  *
3768  */
3769 /*
3770  * Field : Port Static Weights[49:32] - staticweight_49_32
3771  *
3772  * Set static weight of the port. Each port is programmed with a 5 bit value.
3773  * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45
3774  *
3775  * Field Access Macros:
3776  *
3777  */
3778 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */
3779 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_LSB 0
3780 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */
3781 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_MSB 17
3782 /* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */
3783 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_WIDTH 18
3784 /* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */
3785 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET_MSK 0x0003ffff
3786 /* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */
3787 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_CLR_MSK 0xfffc0000
3788 /* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field is UNKNOWN. */
3789 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_RESET 0x0
3790 /* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 field value from a register. */
3791 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_GET(value) (((value) & 0x0003ffff) >> 0)
3792 /* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value suitable for setting the register. */
3793 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET(value) (((value) << 0) & 0x0003ffff)
3794 
3795 /*
3796  * Field : Port Sum of Weights[13:0] - sumofweights_13_0
3797  *
3798  * Set the sum of static weights for particular user priority. This register is
3799  * used as part of the deficit round robin implementation. It should be set to the
3800  * sum of the weights for the ports
3801  *
3802  * Field Access Macros:
3803  *
3804  */
3805 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */
3806 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_LSB 18
3807 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */
3808 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_MSB 31
3809 /* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */
3810 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_WIDTH 14
3811 /* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */
3812 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET_MSK 0xfffc0000
3813 /* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */
3814 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_CLR_MSK 0x0003ffff
3815 /* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field is UNKNOWN. */
3816 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_RESET 0x0
3817 /* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 field value from a register. */
3818 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_GET(value) (((value) & 0xfffc0000) >> 18)
3819 /* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value suitable for setting the register. */
3820 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET(value) (((value) << 18) & 0xfffc0000)
3821 
3822 #ifndef __ASSEMBLY__
3823 /*
3824  * WARNING: The C register and register group struct declarations are provided for
3825  * convenience and illustrative purposes. They should, however, be used with
3826  * caution as the C language standard provides no guarantees about the alignment or
3827  * atomicity of device memory accesses. The recommended practice for writing
3828  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3829  * alt_write_word() functions.
3830  *
3831  * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4.
3832  */
3833 struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s
3834 {
3835  uint32_t staticweight_49_32 : 18; /* Port Static Weights[49:32] */
3836  uint32_t sumofweights_13_0 : 14; /* Port Sum of Weights[13:0] */
3837 };
3838 
3839 /* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4. */
3840 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t;
3841 #endif /* __ASSEMBLY__ */
3842 
3843 /* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register from the beginning of the component. */
3844 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST 0x4
3845 /* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register. */
3846 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST))
3847 
3848 /*
3849  * Register : Port Sum of Weight Register[3/4] - mpweight_2_4
3850  *
3851  * This register is used to configure the DRAM burst operation scheduling.
3852  *
3853  * Register Layout
3854  *
3855  * Bits | Access | Reset | Description
3856  * :-------|:-------|:--------|:---------------------------
3857  * [31:0] | RW | Unknown | Port Sum of Weights[45:14]
3858  *
3859  */
3860 /*
3861  * Field : Port Sum of Weights[45:14] - sumofweights_45_14
3862  *
3863  * Set the sum of static weights for particular user priority. This register is
3864  * used as part of the deficit round robin implementation. It should be set to the
3865  * sum of the weights for the ports
3866  *
3867  * Field Access Macros:
3868  *
3869  */
3870 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */
3871 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_LSB 0
3872 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */
3873 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_MSB 31
3874 /* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */
3875 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_WIDTH 32
3876 /* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */
3877 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET_MSK 0xffffffff
3878 /* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */
3879 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_CLR_MSK 0x00000000
3880 /* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field is UNKNOWN. */
3881 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_RESET 0x0
3882 /* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 field value from a register. */
3883 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_GET(value) (((value) & 0xffffffff) >> 0)
3884 /* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value suitable for setting the register. */
3885 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET(value) (((value) << 0) & 0xffffffff)
3886 
3887 #ifndef __ASSEMBLY__
3888 /*
3889  * WARNING: The C register and register group struct declarations are provided for
3890  * convenience and illustrative purposes. They should, however, be used with
3891  * caution as the C language standard provides no guarantees about the alignment or
3892  * atomicity of device memory accesses. The recommended practice for writing
3893  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3894  * alt_write_word() functions.
3895  *
3896  * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4.
3897  */
3898 struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s
3899 {
3900  uint32_t sumofweights_45_14 : 32; /* Port Sum of Weights[45:14] */
3901 };
3902 
3903 /* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4. */
3904 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t;
3905 #endif /* __ASSEMBLY__ */
3906 
3907 /* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register from the beginning of the component. */
3908 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST 0x8
3909 /* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register. */
3910 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST))
3911 
3912 /*
3913  * Register : Port Sum of Weight Register[4/4] - mpweight_3_4
3914  *
3915  * This register is used to configure the DRAM burst operation scheduling.
3916  *
3917  * Register Layout
3918  *
3919  * Bits | Access | Reset | Description
3920  * :--------|:-------|:--------|:---------------------------
3921  * [17:0] | RW | Unknown | Port Sum of Weights[63:46]
3922  * [31:18] | ??? | 0x0 | *UNDEFINED*
3923  *
3924  */
3925 /*
3926  * Field : Port Sum of Weights[63:46] - sumofweights_63_46
3927  *
3928  * Set the sum of static weights for particular user priority. This register is
3929  * used as part of the deficit round robin implementation. It should be set to the
3930  * sum of the weights for the ports
3931  *
3932  * Field Access Macros:
3933  *
3934  */
3935 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */
3936 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_LSB 0
3937 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */
3938 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_MSB 17
3939 /* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */
3940 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_WIDTH 18
3941 /* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */
3942 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET_MSK 0x0003ffff
3943 /* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */
3944 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_CLR_MSK 0xfffc0000
3945 /* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field is UNKNOWN. */
3946 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_RESET 0x0
3947 /* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 field value from a register. */
3948 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_GET(value) (((value) & 0x0003ffff) >> 0)
3949 /* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value suitable for setting the register. */
3950 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET(value) (((value) << 0) & 0x0003ffff)
3951 
3952 #ifndef __ASSEMBLY__
3953 /*
3954  * WARNING: The C register and register group struct declarations are provided for
3955  * convenience and illustrative purposes. They should, however, be used with
3956  * caution as the C language standard provides no guarantees about the alignment or
3957  * atomicity of device memory accesses. The recommended practice for writing
3958  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3959  * alt_write_word() functions.
3960  *
3961  * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4.
3962  */
3963 struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s
3964 {
3965  uint32_t sumofweights_63_46 : 18; /* Port Sum of Weights[63:46] */
3966  uint32_t : 14; /* *UNDEFINED* */
3967 };
3968 
3969 /* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4. */
3970 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t;
3971 #endif /* __ASSEMBLY__ */
3972 
3973 /* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register from the beginning of the component. */
3974 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST 0xc
3975 /* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register. */
3976 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST))
3977 
3978 #ifndef __ASSEMBLY__
3979 /*
3980  * WARNING: The C register and register group struct declarations are provided for
3981  * convenience and illustrative purposes. They should, however, be used with
3982  * caution as the C language standard provides no guarantees about the alignment or
3983  * atomicity of device memory accesses. The recommended practice for writing
3984  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3985  * alt_write_word() functions.
3986  *
3987  * The struct declaration for register group ALT_SDR_CTL_MPWT.
3988  */
3989 struct ALT_SDR_CTL_MPWT_s
3990 {
3991  volatile ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */
3992  volatile ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */
3993  volatile ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */
3994  volatile ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */
3995 };
3996 
3997 /* The typedef declaration for register group ALT_SDR_CTL_MPWT. */
3998 typedef volatile struct ALT_SDR_CTL_MPWT_s ALT_SDR_CTL_MPWT_t;
3999 /* The struct declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */
4000 struct ALT_SDR_CTL_MPWT_raw_s
4001 {
4002  volatile uint32_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */
4003  volatile uint32_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */
4004  volatile uint32_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */
4005  volatile uint32_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */
4006 };
4007 
4008 /* The typedef declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */
4009 typedef volatile struct ALT_SDR_CTL_MPWT_raw_s ALT_SDR_CTL_MPWT_raw_t;
4010 #endif /* __ASSEMBLY__ */
4011 
4012 
4013 #ifndef __ASSEMBLY__
4014 /*
4015  * WARNING: The C register and register group struct declarations are provided for
4016  * convenience and illustrative purposes. They should, however, be used with
4017  * caution as the C language standard provides no guarantees about the alignment or
4018  * atomicity of device memory accesses. The recommended practice for writing
4019  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4020  * alt_write_word() functions.
4021  *
4022  * The struct declaration for register group ALT_SDR_CTL.
4023  */
4024 struct ALT_SDR_CTL_s
4025 {
4026  volatile ALT_SDR_CTL_CTLCFG_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */
4027  volatile ALT_SDR_CTL_DRAMTIMING1_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */
4028  volatile ALT_SDR_CTL_DRAMTIMING2_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */
4029  volatile ALT_SDR_CTL_DRAMTIMING3_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */
4030  volatile ALT_SDR_CTL_DRAMTIMING4_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */
4031  volatile ALT_SDR_CTL_LOWPWRTIMING_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */
4032  volatile ALT_SDR_CTL_DRAMODT_t dramodt; /* ALT_SDR_CTL_DRAMODT */
4033  volatile uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */
4034  volatile ALT_SDR_CTL_DRAMADDRW_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */
4035  volatile ALT_SDR_CTL_DRAMIFWIDTH_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */
4036  volatile ALT_SDR_CTL_DRAMDEVWIDTH_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */
4037  volatile ALT_SDR_CTL_DRAMSTS_t dramsts; /* ALT_SDR_CTL_DRAMSTS */
4038  volatile ALT_SDR_CTL_DRAMINTR_t dramintr; /* ALT_SDR_CTL_DRAMINTR */
4039  volatile ALT_SDR_CTL_SBECOUNT_t sbecount; /* ALT_SDR_CTL_SBECOUNT */
4040  volatile ALT_SDR_CTL_DBECOUNT_t dbecount; /* ALT_SDR_CTL_DBECOUNT */
4041  volatile ALT_SDR_CTL_ERRADDR_t erraddr; /* ALT_SDR_CTL_ERRADDR */
4042  volatile ALT_SDR_CTL_DROPCOUNT_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */
4043  volatile ALT_SDR_CTL_DROPADDR_t dropaddr; /* ALT_SDR_CTL_DROPADDR */
4044  volatile ALT_SDR_CTL_LOWPWREQ_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */
4045  volatile ALT_SDR_CTL_LOWPWRACK_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */
4046  volatile ALT_SDR_CTL_STATICCFG_t staticcfg; /* ALT_SDR_CTL_STATICCFG */
4047  volatile ALT_SDR_CTL_CTLWIDTH_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */
4048  volatile uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */
4049  volatile ALT_SDR_CTL_PORTCFG_t portcfg; /* ALT_SDR_CTL_PORTCFG */
4050  volatile ALT_SDR_CTL_FPGAPORTRST_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */
4051  volatile uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */
4052  volatile ALT_SDR_CTL_PROTPORTDEFAULT_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */
4053  volatile ALT_SDR_CTL_PROTRULEADDR_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */
4054  volatile ALT_SDR_CTL_PROTRULEID_t protruleid; /* ALT_SDR_CTL_PROTRULEID */
4055  volatile ALT_SDR_CTL_PROTRULEDATA_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */
4056  volatile ALT_SDR_CTL_PROTRULERDWR_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */
4057  volatile ALT_SDR_CTL_QOSLOWPRI_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */
4058  volatile ALT_SDR_CTL_QOSHIGHPRI_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */
4059  volatile ALT_SDR_CTL_QOSPRIORITYEN_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */
4060  volatile ALT_SDR_CTL_MPPRIORITY_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */
4061  volatile ALT_SDR_CTL_MPWT_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */
4062  volatile uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */
4063  volatile ALT_SDR_CTL_REMAPPRIORITY_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */
4064  volatile uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */
4065 };
4066 
4067 /* The typedef declaration for register group ALT_SDR_CTL. */
4068 typedef volatile struct ALT_SDR_CTL_s ALT_SDR_CTL_t;
4069 /* The struct declaration for the raw register contents of register group ALT_SDR_CTL. */
4070 struct ALT_SDR_CTL_raw_s
4071 {
4072  volatile uint32_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */
4073  volatile uint32_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */
4074  volatile uint32_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */
4075  volatile uint32_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */
4076  volatile uint32_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */
4077  volatile uint32_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */
4078  volatile uint32_t dramodt; /* ALT_SDR_CTL_DRAMODT */
4079  volatile uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */
4080  volatile uint32_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */
4081  volatile uint32_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */
4082  volatile uint32_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */
4083  volatile uint32_t dramsts; /* ALT_SDR_CTL_DRAMSTS */
4084  volatile uint32_t dramintr; /* ALT_SDR_CTL_DRAMINTR */
4085  volatile uint32_t sbecount; /* ALT_SDR_CTL_SBECOUNT */
4086  volatile uint32_t dbecount; /* ALT_SDR_CTL_DBECOUNT */
4087  volatile uint32_t erraddr; /* ALT_SDR_CTL_ERRADDR */
4088  volatile uint32_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */
4089  volatile uint32_t dropaddr; /* ALT_SDR_CTL_DROPADDR */
4090  volatile uint32_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */
4091  volatile uint32_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */
4092  volatile uint32_t staticcfg; /* ALT_SDR_CTL_STATICCFG */
4093  volatile uint32_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */
4094  volatile uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */
4095  volatile uint32_t portcfg; /* ALT_SDR_CTL_PORTCFG */
4096  volatile uint32_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */
4097  volatile uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */
4098  volatile uint32_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */
4099  volatile uint32_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */
4100  volatile uint32_t protruleid; /* ALT_SDR_CTL_PROTRULEID */
4101  volatile uint32_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */
4102  volatile uint32_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */
4103  volatile uint32_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */
4104  volatile uint32_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */
4105  volatile uint32_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */
4106  volatile uint32_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */
4107  volatile ALT_SDR_CTL_MPWT_raw_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */
4108  volatile uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */
4109  volatile uint32_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */
4110  volatile uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */
4111 };
4112 
4113 /* The typedef declaration for the raw register contents of register group ALT_SDR_CTL. */
4114 typedef volatile struct ALT_SDR_CTL_raw_s ALT_SDR_CTL_raw_t;
4115 #endif /* __ASSEMBLY__ */
4116 
4117 
4118 #ifndef __ASSEMBLY__
4119 /*
4120  * WARNING: The C register and register group struct declarations are provided for
4121  * convenience and illustrative purposes. They should, however, be used with
4122  * caution as the C language standard provides no guarantees about the alignment or
4123  * atomicity of device memory accesses. The recommended practice for writing
4124  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4125  * alt_write_word() functions.
4126  *
4127  * The struct declaration for register group ALT_SDR.
4128  */
4129 struct ALT_SDR_s
4130 {
4131  volatile uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */
4132  volatile ALT_SDR_CTL_t ctrlgrp; /* ALT_SDR_CTL */
4133  volatile uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */
4134 };
4135 
4136 /* The typedef declaration for register group ALT_SDR. */
4137 typedef volatile struct ALT_SDR_s ALT_SDR_t;
4138 /* The struct declaration for the raw register contents of register group ALT_SDR. */
4139 struct ALT_SDR_raw_s
4140 {
4141  volatile uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */
4142  volatile ALT_SDR_CTL_raw_t ctrlgrp; /* ALT_SDR_CTL */
4143  volatile uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */
4144 };
4145 
4146 /* The typedef declaration for the raw register contents of register group ALT_SDR. */
4147 typedef volatile struct ALT_SDR_raw_s ALT_SDR_raw_t;
4148 #endif /* __ASSEMBLY__ */
4149 
4150 
4151 #ifdef __cplusplus
4152 }
4153 #endif /* __cplusplus */
4154 #endif /* __ALTERA_ALT_SDR_H__ */
4155 
ALT_SDR_CTL_LOWPWRTIMING_s
Definition: alt_sdr.h:1233
ALT_SDR_CTL_DROPCOUNT_s
Definition: alt_sdr.h:2186
ALT_SDR_CTL_DRAMDEVWIDTH_s
Definition: alt_sdr.h:1599
ALT_SDR_CTL_raw_s
Definition: alt_sdr.h:4070
ALT_SDR_CTL_REMAPPRIORITY_s
Definition: alt_sdr.h:3673
ALT_SDR_CTL_DRAMTIMING2_s
Definition: alt_sdr.h:849
ALT_SDR_CTL_PROTRULEID_s
Definition: alt_sdr.h:3083
ALT_SDR_CTL_PROTPORTDEFAULT_s
Definition: alt_sdr.h:2890
ALT_SDR_CTL_DRAMIFWIDTH_s
Definition: alt_sdr.h:1537
ALT_SDR_CTL_DRAMADDRW_s
Definition: alt_sdr.h:1471
ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s
Definition: alt_sdr.h:3833
ALT_SDR_CTL_MPPRIORITY_s
Definition: alt_sdr.h:3609
ALT_SDR_CTL_PROTRULEDATA_s
Definition: alt_sdr.h:3232
ALT_SDR_CTL_PROTRULERDWR_s
Definition: alt_sdr.h:3356
ALT_SDR_CTL_DBECOUNT_s
Definition: alt_sdr.h:2065
ALT_SDR_CTL_ERRADDR_s
Definition: alt_sdr.h:2125
ALT_SDR_CTL_PORTCFG_s
Definition: alt_sdr.h:2750
ALT_SDR_CTL_STATICCFG_s
Definition: alt_sdr.h:2614
ALT_SDR_s
Definition: alt_sdr.h:4129
ALT_SDR_CTL_DRAMINTR_s
Definition: alt_sdr.h:1937
ALT_SDR_CTL_SBECOUNT_s
Definition: alt_sdr.h:2003
ALT_SDR_CTL_PROTRULEADDR_s
Definition: alt_sdr.h:2991
ALT_SDR_CTL_QOSPRIORITYEN_s
Definition: alt_sdr.h:3545
ALT_SDR_CTL_MPWT_s
Definition: alt_sdr.h:3989
ALT_SDR_CTL_s
Definition: alt_sdr.h:4024
ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s
Definition: alt_sdr.h:3898
ALT_SDR_CTL_CTLWIDTH_s
Definition: alt_sdr.h:2681
ALT_SDR_CTL_QOSLOWPRI_s
Definition: alt_sdr.h:3422
ALT_SDR_CTL_DROPADDR_s
Definition: alt_sdr.h:2246
ALT_SDR_CTL_FPGAPORTRST_s
Definition: alt_sdr.h:2821
ALT_SDR_CTL_DRAMSTS_s
Definition: alt_sdr.h:1765
ALT_SDR_CTL_QOSHIGHPRI_s
Definition: alt_sdr.h:3484
ALT_SDR_CTL_LOWPWRACK_s
Definition: alt_sdr.h:2486
ALT_SDR_CTL_DRAMTIMING4_s
Definition: alt_sdr.h:1140
ALT_SDR_CTL_MPWT_raw_s
Definition: alt_sdr.h:4000
ALT_SDR_CTL_CTLCFG_s
Definition: alt_sdr.h:473
ALT_SDR_raw_s
Definition: alt_sdr.h:4139
ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s
Definition: alt_sdr.h:3742
ALT_SDR_CTL_DRAMTIMING3_s
Definition: alt_sdr.h:1020
ALT_SDR_CTL_LOWPWREQ_s
Definition: alt_sdr.h:2394
ALT_SDR_CTL_DRAMODT_s
Definition: alt_sdr.h:1327
ALT_SDR_CTL_DRAMTIMING1_s
Definition: alt_sdr.h:678
ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s
Definition: alt_sdr.h:3963
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