RTEMS 5.2
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spwtdp.h
1/* SPWTDP - SpaceWire Time Distribution Protocol. The driver provides
2 * device discovery and interrupt management.
3 *
4 * COPYRIGHT (c) 2017.
5 * Cobham Gaisler AB
6 *
7 * The license and distribution terms for this file may be
8 * found in the file LICENSE in this distribution or at
9 * http://www.rtems.com/license/LICENSE.
10 *
11 */
12
13#ifndef __SPWTDP_H__
14#define __SPWTDP_H__
15
16#ifdef __cplusplus
17extern "C" {
18#endif
19
20#define SPWTDP_ERR_OK 0
21#define SPWTDP_ERR_EINVAL -1
22#define SPWTDP_ERR_ERROR -2
23#define SPWTDP_ERR_NOINIT -3
24
25/* Maximum number of SPWTDP devices supported by driver */
26#define SPWTDP_MAX 2
27
28/* SPWTDP Register layout */
29struct spwtdp_regs {
30 volatile unsigned int conf[4]; /* 0x000-0x00C */
31 volatile unsigned int stat[4]; /* 0x010-0x01C */
32 volatile unsigned int cmd_ctrl; /* 0x020 */
33 volatile unsigned int cmd_et[5]; /* 0x024-0x034 */
34 volatile unsigned int resv1[2]; /* 0x038-0x03C */
35 volatile unsigned int dat_ctrl; /* 0x040 */
36 volatile unsigned int dat_et[5]; /* 0x044-0x054 */
37 volatile unsigned int resv2[2]; /* 0x058-0x05C */
38 volatile unsigned int ts_rx_ctrl; /* 0x060 */
39 volatile unsigned int ts_rx_et[5]; /* 0x064-0x074 */
40 volatile unsigned int resv3[2]; /* 0x078-0x07C */
41 volatile unsigned int ts_tx_ctrl; /* 0x080 */
42 volatile unsigned int ts_tx_et[5]; /* 0x084-0x094 */
43 volatile unsigned int resv4[2]; /* 0x098 */
44 volatile unsigned int lat_ctrl; /* 0x0A0 */
45 volatile unsigned int lat_et[5]; /* 0x0A4-0x0B4 */
46 volatile unsigned int resv5[2]; /* 0x0B8-0x0BC */
47 volatile unsigned int ien; /* 0x0C0 */
48 volatile unsigned int ists; /* 0x0C4 */
49 volatile unsigned int dlycnt; /* 0x0C8 */
50 volatile unsigned int dissync; /* 0x0CC */
51 volatile unsigned int resv6[12]; /* 0x0D0-0x0FC */
52 volatile unsigned int edmask[4]; /* 0x100-0x10C */
53 struct {
54 volatile unsigned int ctrl; /* 0x110, 0x130, 0x150, 0x170 */
55 volatile unsigned int et[5]; /* 0x114-0x124, 0x134-0x144, 0x154-0x164, 0x174-0x184, */
56 volatile unsigned int resv0[2]; /* 0x128-0x12C, 0x148-0x14C, 0x168-0x16C, 0x188-0x18C, */
57 } edat[4]; /* 0x110-0x18C */
58 volatile unsigned int resv7[4]; /* 0x190-0x19C */
59 volatile unsigned int pulse[8]; /* 0x1A0-0x1BC */
60 volatile unsigned int resv8[16]; /* 0x1C0-0x1FC */
61};
62
63/*
64 * Configuration register definitions
65 */
66#define CONF0_JE (0x1 << CONF0_JE_BIT)
67#define CONF0_ST (0x1 << CONF0_ST_BIT)
68#define CONF0_EP (0x1 << CONF0_EP_BIT)
69#define CONF0_ET (0x1 << CONF0_ET_BIT)
70#define CONF0_SP (0x1 << CONF0_SP_BIT)
71#define CONF0_SE (0x1 << CONF0_SE_BIT)
72#define CONF0_LE (0x1 << CONF0_LE_BIT)
73#define CONF0_AE (0x1 << CONF0_AE_BIT)
74#define CONF0_MAP (0x1f << CONF0_MAP_BIT)
75#define CONF0_TD (0x1 << CONF0_TD_BIT)
76#define CONF0_MU (0x1 << CONF0_MU_BIT)
77#define CONF0_SEL (0x3 << CONF0_SEL_BIT)
78#define CONF0_ME (0x1 << CONF0_ME_BIT)
79#define CONF0_RE (0x1 << CONF0_RE_BIT)
80#define CONF0_TE (0x1 << CONF0_TE_BIT)
81#define CONF0_RS (0x1 << CONF0_RS_BIT)
82
83#define CONF0_JE_BIT 24
84#define CONF0_ST_BIT 21
85#define CONF0_EP_BIT 20
86#define CONF0_ET_BIT 19
87#define CONF0_SP_BIT 18
88#define CONF0_SE_BIT 17
89#define CONF0_LE_BIT 16
90#define CONF0_AE_BIT 15
91#define CONF0_MAP_BIT 8
92#define CONF0_TD_BIT 7
93#define CONF0_MU_BIT 6
94#define CONF0_SEL_BIT 4
95#define CONF0_ME_BIT 3
96#define CONF0_RE_BIT 2
97#define CONF0_TE_BIT 1
98#define CONF0_RS_BIT 0
99
100#define CONF1_FSINC (0x3fffffff << CONF1_FSINC_BIT)
101
102#define CONF1_FSINC_BIT 0
103
104#define CONF2_CV (0xffffff << CONF2_CV_BIT)
105#define CONF2_ETINC (0xff << CONF2_ETINC_BIT)
106
107#define CONF2_CV_BIT 8
108#define CONF2_ETINC_BIT 0
109
110#define CONF3_OUTPORT (0xf << CONF3_OUTPORT_BIT)
111#define CONF3_INPORT (0xf << CONF3_INPORT_BIT)
112#define CONF3_STM (0x3f << CONF3_STM_BIT)
113#define CONF3_DI64R (0x1 << CONF3_DI64R_BIT)
114#define CONF3_DI64T (0x1 << CONF3_DI64T_BIT)
115#define CONF3_DI64 (0x1 << CONF3_DI64_BIT)
116#define CONF3_DI (0x1 << CONF3_DI_BIT)
117#define CONF3_INRX (0x1f << CONF3_INRX_BIT)
118#define CONF3_INTX (0x1f << CONF3_INTX_BIT)
119
120#define CONF3_OUTPORT_BIT 28
121#define CONF3_INPORT_BIT 24
122#define CONF3_STM_BIT 16
123#define CONF3_DI64R_BIT 13
124#define CONF3_DI64T_BIT 12
125#define CONF3_DI64_BIT 11
126#define CONF3_DI_BIT 10
127#define CONF3_INRX_BIT 5
128#define CONF3_INTX_BIT 0
129
130/*
131 * Control register definitions
132 */
133#define CTRL_NC (0x1 << CTRL_NC_BIT)
134#define CTRL_IS (0x1 << CTRL_IS_BIT)
135#define CTRL_SPWTC (0xff << CTRL_SPWTC_BIT)
136#define CTRL_CPF (0xffff << CTRL_CPF_BIT)
137
138#define CTRL_NC_BIT 31
139#define CTRL_IS_BIT 30
140#define CTRL_SPWTC_BIT 16
141#define CTRL_CPF_BIT 0
142
143/*
144 * Interrupt register definition
145 */
146#define SPWTDP_IRQ_S (0x1 << SPWTDP_IRQ_S_BIT)
147#define SPWTDP_IRQ_TR (0x1 << SPWTDP_IRQ_TR_BIT)
148#define SPWTDP_IRQ_TM (0x1 << SPWTDP_IRQ_TM_BIT)
149#define SPWTDP_IRQ_TT (0x1 << SPWTDP_IRQ_TT_BIT)
150#define SPWTDP_IRQ_DIR (0x1 << SPWTDP_IRQ_DIR_BIT)
151#define SPWTDP_IRQ_DIT (0x1 << SPWTDP_IRQ_DIT_BIT)
152#define SPWTDP_IRQ_EDI0 (0x1 << SPWTDP_IRQ_EDI0_BIT)
153#define SPWTDP_IRQ_EDI1 (0x1 << SPWTDP_IRQ_EDI1_BIT)
154#define SPWTDP_IRQ_EDI2 (0x1 << SPWTDP_IRQ_EDI2_BIT)
155#define SPWTDP_IRQ_EDI3 (0x1 << SPWTDP_IRQ_EDI3_BIT)
156#define SPWTDP_IRQ_SET (0x1 << SPWTDP_IRQ_SET_BIT)
157#define SPWTDP_IRQ_P0 (0x1 << SPWTDP_IRQ_P0_BIT)
158#define SPWTDP_IRQ_P1 (0x1 << SPWTDP_IRQ_P1_BIT)
159#define SPWTDP_IRQ_P2 (0x1 << SPWTDP_IRQ_P2_BIT)
160#define SPWTDP_IRQ_P3 (0x1 << SPWTDP_IRQ_P3_BIT)
161#define SPWTDP_IRQ_P4 (0x1 << SPWTDP_IRQ_P4_BIT)
162#define SPWTDP_IRQ_P5 (0x1 << SPWTDP_IRQ_P5_BIT)
163#define SPWTDP_IRQ_P6 (0x1 << SPWTDP_IRQ_P6_BIT)
164#define SPWTDP_IRQ_P7 (0x1 << SPWTDP_IRQ_P7_BIT)
165#define SPWTDP_IRQ_NCTC (0x1 << SPWTDP_IRQ_NCTC_BIT)
166#define SPWTDP_IRQ_WCLEAR \
167 (SPWTDP_IRQ_S | SPWTDP_IRQ_TR | SPWTDP_IRQ_TM | \
168 SPWTDP_IRQ_TT | SPWTDP_IRQ_DIR | SPWTDP_IRQ_DIT | SPWTDP_IRQ_EDI0 | \
169 SPWTDP_IRQ_EDI1 | SPWTDP_IRQ_EDI2 | SPWTDP_IRQ_EDI3 | SPWTDP_IRQ_SET |\
170 SPWTDP_IRQ_P0 | SPWTDP_IRQ_P1 | SPWTDP_IRQ_P2 | SPWTDP_IRQ_P3 | \
171 SPWTDP_IRQ_P4 | SPWTDP_IRQ_P5 | SPWTDP_IRQ_P6 | SPWTDP_IRQ_P7 | \
172 SPWTDP_IRQ_NCTC)
173#define SPWTDP_IRQ_ALL (SPWTDP_IRQ_WCLEAR)
174
175#define SPWTDP_IRQ_S_BIT 0
176#define SPWTDP_IRQ_TR_BIT 1
177#define SPWTDP_IRQ_TM_BIT 2
178#define SPWTDP_IRQ_TT_BIT 3
179#define SPWTDP_IRQ_DIR_BIT 4
180#define SPWTDP_IRQ_DIT_BIT 5
181#define SPWTDP_IRQ_EDI0_BIT 6
182#define SPWTDP_IRQ_EDI1_BIT 7
183#define SPWTDP_IRQ_EDI2_BIT 8
184#define SPWTDP_IRQ_EDI3_BIT 9
185#define SPWTDP_IRQ_SET_BIT 10
186#define SPWTDP_IRQ_P0_BIT 11
187#define SPWTDP_IRQ_P1_BIT 12
188#define SPWTDP_IRQ_P2_BIT 13
189#define SPWTDP_IRQ_P3_BIT 14
190#define SPWTDP_IRQ_P4_BIT 15
191#define SPWTDP_IRQ_P5_BIT 16
192#define SPWTDP_IRQ_P6_BIT 17
193#define SPWTDP_IRQ_P7_BIT 18
194#define SPWTDP_IRQ_NCTC_BIT 19
195
196/* Register the SPWTDP Driver to the Driver Manager */
197void spwtdp_register_drv(void);
198
199/* Open a SPWTDP device by registration order index. A SPWTDP device can only by
200 * opened once. The handle returned must be used as the input parameter 'spwtdp'
201 * in the rest of the calls in the function interface.
202 */
203extern void *spwtdp_open(int dev_no);
204
205/* Close a previously opened SPWTDP device */
206extern int spwtdp_close(void *spwtdp);
207
208/* Reset SPWTDP Core */
209extern int spwtdp_reset(void *spwtdp);
210
211/* Setup the frequency configuration registers */
212extern int spwtdp_freq_setup(void *spwtdp, uint32_t fsinc, uint32_t cv,
213 uint8_t etinc);
214
215/* Unmask Interrupts at Interrupt controller */
216extern int spwtdp_interrupt_unmask(void *spwtdp, uint32_t irqmask);
217
218/* Mask Interrupts at Interrupt controller */
219extern int spwtdp_interrupt_mask(void *spwtdp, uint32_t irqmask);
220
221/* Function ISR callback prototype
222 *
223 * ists - Interrupt STatus register of the SPWTDP core read by ISR
224 * data - Custom data provided by user
225 */
226typedef void (*spwtdp_isr_t)(unsigned int ists, void *data);
227
228/* Register an Interrupt handler and custom data, the function call is
229 * removed by calling unregister function.
230 */
231extern int spwtdp_isr_register(void *spwtdp, spwtdp_isr_t isr, void *data);
232
233/* Unregister an Interrupt handler */
234extern int spwtdp_isr_unregister(void *spwtdp);
235
236/* Get and clear interrupt status */
237extern int spwtdp_interrupt_status(void *spwtdp, uint32_t *sts,
238 uint32_t clrmask);
239
240/* Setup Initiator and target */
241#define SPWTDP_TDP_ENABLE CONF0_TD
242#define SPWTDP_TDP_DISABLE 0
243#define SPWTDP_LATENCY_ENABLE CONF0_LE
244#define SPWTDP_LATENCY_DISABLE 0
245#define SPWTDP_EXTET_INC_POLARITY_RISING CONF0_EP
246#define SPWTDP_EXTET_INC_POLARITY_FALLING 0
247#define SPWTDP_EXTET_INC_ENABLE CONF0_ET
248#define SPWTDP_EXTET_INC_DISABLE 0
249#define SPWTDP_EXTET_POLARITY_RISING CONF0_SP
250#define SPWTDP_EXTET_POLARITY_FALLING 0
251#define SPWTDP_EXTET_ENABLE CONF0_SE
252#define SPWTDP_EXTET_DISABLE 0
253#define SPWTDP_TARGET_SPWSYNC_ENABLE CONF0_ST
254#define SPWTDP_TARGET_SPWSYNC_DISABLE 0
255#define SPWTDP_TARGET_JITTERC_ENABLE CONF0_JE
256#define SPWTDP_TARGET_JITTERC_DISABLE 0
257#define SPWTDP_TARGET_MITIGATION_ENABLE CONF0_ME
258#define SPWTDP_TARGET_MITIGATION_DISABLE 0
259extern int spwtdp_initiator_conf(void *spwtdp, uint8_t mapping,
260 uint32_t options);
261extern int spwtdp_target_conf(void *spwtdp, uint8_t mapping, uint32_t options);
262
263/* Setup Initiator and target dist interrupts */
264extern int spwtdp_initiator_int_conf(void *spwtdp, uint8_t stm, uint8_t inrx,
265 uint8_t intx);
266#define SPWTDP_TARGET_DISTINT_INTACK CONF3_DI
267#define SPWTDP_TARGET_DISTINT_INT 0
268extern int spwtdp_target_int_conf(void *spwtdp, uint8_t inrx, uint8_t intx,
269 uint32_t options);
270
271/* Enable Initiator and target */
272extern int spwtdp_initiator_enable(void *spwtdp);
273extern int spwtdp_target_enable(void *spwtdp);
274
275/* Disable Initiator and target */
276extern int spwtdp_initiator_disable(void *spwtdp);
277extern int spwtdp_target_disable(void *spwtdp);
278
279/* Get and clear status */
280extern int spwtdp_status(void *spwtdp, uint32_t *sts, uint32_t clrmask);
281
282/* Define time struct */
283/* Length of the max data sample (136 bits), aligned to the next 32-bit word
284 * (160 bits=20 byte=5 words)
285 */
286#define SPWTDP_TIME_DATA_LENGTH 20
287struct spwtdp_time_t {
288 uint8_t data[SPWTDP_TIME_DATA_LENGTH];
289 uint32_t preamble;
290};
291typedef struct spwtdp_time_t spwtdp_time_t;
292
293/* Get datation elapsed time */
294extern int spwtdp_dat_et_get(void *spwtdp, spwtdp_time_t * val);
295extern int spwtdp_tsrx_et_get(void *spwtdp, spwtdp_time_t * val);
296extern int spwtdp_tstx_et_get(void *spwtdp, spwtdp_time_t * val);
297extern int spwtdp_lat_et_get(void *spwtdp, spwtdp_time_t * val);
298extern int spwtdp_cmd_et_get(void *spwtdp, spwtdp_time_t * val);
299
300/* Configure TSTX */
301extern int spwtdp_initiator_tstx_conf(void *spwtdp, uint8_t tstc);
302
303/* Manage control register */
304extern int spwtdp_initiator_cmd_et_set(void *spwtdp, spwtdp_time_t val);
305extern int spwtdp_initiator_cmd_spwtc_set(void *spwtdp, uint8_t spwtc);
306#define SPWTDP_TARGET_CTRL_NEWCOMMAND_ENABLE CTRL_NC
307#define SPWTDP_TARGET_CTRL_NEWCOMMAND_DISABLE 0
308#define SPWTDP_TARGET_CTRL_INIT CTRL_IS
309#define SPWTDP_TARGET_CTRL_SYNC 0
310extern int spwtdp_target_cmd_conf(void *spwtdp, uint8_t spwtc, uint16_t cpf,
311 uint32_t options);
312
313/* Get precision */
314extern int spwtdp_precision_get(void *spwtdp, uint8_t *fine, uint8_t *coarse);
315
316#ifdef __cplusplus
317}
318#endif
319
320#endif
spwtdp_regs
Definition: spwtdp.h:29
spwtdp_time_t
Definition: spwtdp.h:287
cv
unsigned cv
Definition: tte.h:15
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