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component_sdramc.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMV71_SDRAMC_COMPONENT_
31#define _SAMV71_SDRAMC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __IO uint32_t SDRAMC_MR;
43 __IO uint32_t SDRAMC_TR;
44 __IO uint32_t SDRAMC_CR;
45 __I uint32_t Reserved1[1];
46 __IO uint32_t SDRAMC_LPR;
47 __O uint32_t SDRAMC_IER;
48 __O uint32_t SDRAMC_IDR;
49 __I uint32_t SDRAMC_IMR;
50 __I uint32_t SDRAMC_ISR;
51 __IO uint32_t SDRAMC_MDR;
52 __IO uint32_t SDRAMC_CFR1;
53 __IO uint32_t SDRAMC_OCMS;
54 __O uint32_t SDRAMC_OCMS_KEY1;
55 __O uint32_t SDRAMC_OCMS_KEY2;
56 __I uint32_t Reserved2[49];
57 __I uint32_t SDRAMC_VERSION;
58} Sdramc;
59#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
60/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */
61#define SDRAMC_MR_MODE_Pos 0
62#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos)
63#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos)))
64#define SDRAMC_MR_MODE_NORMAL (0x0u << 0)
65#define SDRAMC_MR_MODE_NOP (0x1u << 0)
66#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0)
67#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0)
68#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0)
69#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0)
70#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0)
71/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */
72#define SDRAMC_TR_COUNT_Pos 0
73#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos)
74#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)))
75/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */
76#define SDRAMC_CR_NC_Pos 0
77#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos)
78#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos)))
79#define SDRAMC_CR_NC_COL8 (0x0u << 0)
80#define SDRAMC_CR_NC_COL9 (0x1u << 0)
81#define SDRAMC_CR_NC_COL10 (0x2u << 0)
82#define SDRAMC_CR_NC_COL11 (0x3u << 0)
83#define SDRAMC_CR_NR_Pos 2
84#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos)
85#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos)))
86#define SDRAMC_CR_NR_ROW11 (0x0u << 2)
87#define SDRAMC_CR_NR_ROW12 (0x1u << 2)
88#define SDRAMC_CR_NR_ROW13 (0x2u << 2)
89#define SDRAMC_CR_NB (0x1u << 4)
90#define SDRAMC_CR_NB_BANK2 (0x0u << 4)
91#define SDRAMC_CR_NB_BANK4 (0x1u << 4)
92#define SDRAMC_CR_CAS_Pos 5
93#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos)
94#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos)))
95#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5)
96#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5)
97#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5)
98#define SDRAMC_CR_DBW (0x1u << 7)
99#define SDRAMC_CR_TWR_Pos 8
100#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos)
101#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)))
102#define SDRAMC_CR_TRC_TRFC_Pos 12
103#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos)
104#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)))
105#define SDRAMC_CR_TRP_Pos 16
106#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos)
107#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)))
108#define SDRAMC_CR_TRCD_Pos 20
109#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos)
110#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)))
111#define SDRAMC_CR_TRAS_Pos 24
112#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos)
113#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)))
114#define SDRAMC_CR_TXSR_Pos 28
115#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos)
116#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)))
117/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */
118#define SDRAMC_LPR_LPCB_Pos 0
119#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos)
120#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos)))
121#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0)
122#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0)
123#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0)
124#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0)
125#define SDRAMC_LPR_PASR_Pos 4
126#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos)
127#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)))
128#define SDRAMC_LPR_TCSR_Pos 8
129#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos)
130#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)))
131#define SDRAMC_LPR_DS_Pos 10
132#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos)
133#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)))
134#define SDRAMC_LPR_TIMEOUT_Pos 12
135#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos)
136#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos)))
137#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12)
138#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12)
139#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12)
140/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */
141#define SDRAMC_IER_RES (0x1u << 0)
142/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */
143#define SDRAMC_IDR_RES (0x1u << 0)
144/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */
145#define SDRAMC_IMR_RES (0x1u << 0)
146/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */
147#define SDRAMC_ISR_RES (0x1u << 0)
148/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */
149#define SDRAMC_MDR_MD_Pos 0
150#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos)
151#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos)))
152#define SDRAMC_MDR_MD_SDRAM (0x0u << 0)
153#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0)
154/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */
155#define SDRAMC_CFR1_TMRD_Pos 0
156#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos)
157#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos)))
158#define SDRAMC_CFR1_UNAL (0x1u << 8)
159#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8)
160#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8)
161/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */
162#define SDRAMC_OCMS_SDR_SE (0x1u << 0)
163/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */
164#define SDRAMC_OCMS_KEY1_KEY1_Pos 0
165#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos)
166#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos)))
167/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */
168#define SDRAMC_OCMS_KEY2_KEY2_Pos 0
169#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos)
170#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos)))
171/* -------- SDRAMC_VERSION : (SDRAMC Offset: 0xFC) SDRAMC Version Register -------- */
172#define SDRAMC_VERSION_VERSION_Pos 0
173#define SDRAMC_VERSION_VERSION_Msk (0xfffu << SDRAMC_VERSION_VERSION_Pos)
174#define SDRAMC_VERSION_MFN_Pos 16
175#define SDRAMC_VERSION_MFN_Msk (0x7u << SDRAMC_VERSION_MFN_Pos)
178
179
180#endif /* _SAMV71_SDRAMC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Sdramc
Sdramc hardware registers.
Definition: component_sdramc.h:41
Sdramc::SDRAMC_VERSION
__I uint32_t SDRAMC_VERSION
(Sdramc Offset: 0xFC) SDRAMC Version Register
Definition: component_sdramc.h:57
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