doxygen/5.2/samv71_2component_2component__rtc_8h_source.html

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/*                  Atmel Microcontroller Software Support                      */

/*                       SAM Software Package License                           */

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/* Copyright (c) 2015, Atmel Corporation                                        */

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#ifndef _SAMV71_RTC_COMPONENT_

#define _SAMV71_RTC_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __IO uint32_t RTC_CR;

  __IO uint32_t RTC_MR;

  __IO uint32_t RTC_TIMR;

  __IO uint32_t RTC_CALR;

  __IO uint32_t RTC_TIMALR;

  __IO uint32_t RTC_CALALR;

  __I  uint32_t RTC_SR;

  __O  uint32_t RTC_SCCR;

  __O  uint32_t RTC_IER;

  __O  uint32_t RTC_IDR;

  __I  uint32_t RTC_IMR;

  __I  uint32_t RTC_VER;

  __I  uint32_t Reserved1[45];

  __IO uint32_t RTC_WPMR;

  __I  uint32_t Reserved2[5];

  __I  uint32_t RTC_VERSION;

} Rtc;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */

#define RTC_CR_UPDTIM (0x1u << 0)

#define RTC_CR_UPDCAL (0x1u << 1)

#define RTC_CR_TIMEVSEL_Pos 8

#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos)

#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)))

#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8)

#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8)

#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8)

#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8)

#define RTC_CR_CALEVSEL_Pos 16

#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos)

#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)))

#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16)

#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16)

#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16)

/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */

#define RTC_MR_HRMOD (0x1u << 0)

#define RTC_MR_PERSIAN (0x1u << 1)

#define RTC_MR_NEGPPM (0x1u << 4)

#define RTC_MR_CORRECTION_Pos 8

#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos)

#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))

#define RTC_MR_HIGHPPM (0x1u << 15)

#define RTC_MR_OUT0_Pos 16

#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos)

#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)))

#define   RTC_MR_OUT0_NO_WAVE (0x0u << 16)

#define   RTC_MR_OUT0_FREQ1HZ (0x1u << 16)

#define   RTC_MR_OUT0_FREQ32HZ (0x2u << 16)

#define   RTC_MR_OUT0_FREQ64HZ (0x3u << 16)

#define   RTC_MR_OUT0_FREQ512HZ (0x4u << 16)

#define   RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16)

#define   RTC_MR_OUT0_ALARM_FLAG (0x6u << 16)

#define   RTC_MR_OUT0_PROG_PULSE (0x7u << 16)

#define RTC_MR_OUT1_Pos 20

#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos)

#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)))

#define   RTC_MR_OUT1_NO_WAVE (0x0u << 20)

#define   RTC_MR_OUT1_FREQ1HZ (0x1u << 20)

#define   RTC_MR_OUT1_FREQ32HZ (0x2u << 20)

#define   RTC_MR_OUT1_FREQ64HZ (0x3u << 20)

#define   RTC_MR_OUT1_FREQ512HZ (0x4u << 20)

#define   RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20)

#define   RTC_MR_OUT1_ALARM_FLAG (0x6u << 20)

#define   RTC_MR_OUT1_PROG_PULSE (0x7u << 20)

#define RTC_MR_THIGH_Pos 24

#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos)

#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos)))

#define   RTC_MR_THIGH_H_31MS (0x0u << 24)

#define   RTC_MR_THIGH_H_16MS (0x1u << 24)

#define   RTC_MR_THIGH_H_4MS (0x2u << 24)

#define   RTC_MR_THIGH_H_976US (0x3u << 24)

#define   RTC_MR_THIGH_H_488US (0x4u << 24)

#define   RTC_MR_THIGH_H_122US (0x5u << 24)

#define   RTC_MR_THIGH_H_30US (0x6u << 24)

#define   RTC_MR_THIGH_H_15US (0x7u << 24)

#define RTC_MR_TPERIOD_Pos 28

#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos)

#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos)))

#define   RTC_MR_TPERIOD_P_1S (0x0u << 28)

#define   RTC_MR_TPERIOD_P_500MS (0x1u << 28)

#define   RTC_MR_TPERIOD_P_250MS (0x2u << 28)

#define   RTC_MR_TPERIOD_P_125MS (0x3u << 28)

/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */

#define RTC_TIMR_SEC_Pos 0

#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos)

#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))

#define RTC_TIMR_MIN_Pos 8

#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos)

#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))

#define RTC_TIMR_HOUR_Pos 16

#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos)

#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))

#define RTC_TIMR_AMPM (0x1u << 22)

/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */

#define RTC_CALR_CENT_Pos 0

#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos)

#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))

#define RTC_CALR_YEAR_Pos 8

#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos)

#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))

#define RTC_CALR_MONTH_Pos 16

#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos)

#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))

#define RTC_CALR_DAY_Pos 21

#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos)

#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))

#define RTC_CALR_DATE_Pos 24

#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos)

#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))

/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */

#define RTC_TIMALR_SEC_Pos 0

#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos)

#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))

#define RTC_TIMALR_SECEN (0x1u << 7)

#define RTC_TIMALR_MIN_Pos 8

#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos)

#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))

#define RTC_TIMALR_MINEN (0x1u << 15)

#define RTC_TIMALR_HOUR_Pos 16

#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos)

#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))

#define RTC_TIMALR_AMPM (0x1u << 22)

#define RTC_TIMALR_HOUREN (0x1u << 23)

/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */

#define RTC_CALALR_MONTH_Pos 16

#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos)

#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))

#define RTC_CALALR_MTHEN (0x1u << 23)

#define RTC_CALALR_DATE_Pos 24

#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos)

#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))

#define RTC_CALALR_DATEEN (0x1u << 31)

/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */

#define RTC_SR_ACKUPD (0x1u << 0)

#define   RTC_SR_ACKUPD_FREERUN (0x0u << 0)

#define   RTC_SR_ACKUPD_UPDATE (0x1u << 0)

#define RTC_SR_ALARM (0x1u << 1)

#define   RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1)

#define   RTC_SR_ALARM_ALARMEVENT (0x1u << 1)

#define RTC_SR_SEC (0x1u << 2)

#define   RTC_SR_SEC_NO_SECEVENT (0x0u << 2)

#define   RTC_SR_SEC_SECEVENT (0x1u << 2)

#define RTC_SR_TIMEV (0x1u << 3)

#define   RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3)

#define   RTC_SR_TIMEV_TIMEVENT (0x1u << 3)

#define RTC_SR_CALEV (0x1u << 4)

#define   RTC_SR_CALEV_NO_CALEVENT (0x0u << 4)

#define   RTC_SR_CALEV_CALEVENT (0x1u << 4)

#define RTC_SR_TDERR (0x1u << 5)

#define   RTC_SR_TDERR_CORRECT (0x0u << 5)

#define   RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5)

/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */

#define RTC_SCCR_ACKCLR (0x1u << 0)

#define RTC_SCCR_ALRCLR (0x1u << 1)

#define RTC_SCCR_SECCLR (0x1u << 2)

#define RTC_SCCR_TIMCLR (0x1u << 3)

#define RTC_SCCR_CALCLR (0x1u << 4)

#define RTC_SCCR_TDERRCLR (0x1u << 5)

/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */

#define RTC_IER_ACKEN (0x1u << 0)

#define RTC_IER_ALREN (0x1u << 1)

#define RTC_IER_SECEN (0x1u << 2)

#define RTC_IER_TIMEN (0x1u << 3)

#define RTC_IER_CALEN (0x1u << 4)

#define RTC_IER_TDERREN (0x1u << 5)

/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */

#define RTC_IDR_ACKDIS (0x1u << 0)

#define RTC_IDR_ALRDIS (0x1u << 1)

#define RTC_IDR_SECDIS (0x1u << 2)

#define RTC_IDR_TIMDIS (0x1u << 3)

#define RTC_IDR_CALDIS (0x1u << 4)

#define RTC_IDR_TDERRDIS (0x1u << 5)

/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */

#define RTC_IMR_ACK (0x1u << 0)

#define RTC_IMR_ALR (0x1u << 1)

#define RTC_IMR_SEC (0x1u << 2)

#define RTC_IMR_TIM (0x1u << 3)

#define RTC_IMR_CAL (0x1u << 4)

#define RTC_IMR_TDERR (0x1u << 5)

/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */

#define RTC_VER_NVTIM (0x1u << 0)

#define RTC_VER_NVCAL (0x1u << 1)

#define RTC_VER_NVTIMALR (0x1u << 2)

#define RTC_VER_NVCALALR (0x1u << 3)

/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */

#define RTC_WPMR_WPEN (0x1u << 0)

#define RTC_WPMR_WPKEY_Pos 8

#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos)

#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))

#define   RTC_WPMR_WPKEY_PASSWD (0x525443u << 8)

/* -------- RTC_VERSION : (RTC Offset: 0xFC) Version Register -------- */

#define RTC_VERSION_VERSION_Pos 0

#define RTC_VERSION_VERSION_Msk (0xfffu << RTC_VERSION_VERSION_Pos)

#define RTC_VERSION_MFN_Pos 16

#define RTC_VERSION_MFN_Msk (0x7u << RTC_VERSION_MFN_Pos)


#endif /* _SAMV71_RTC_COMPONENT_ */

__O
#define __O
Definition: core_cm7.h:286

__IO
#define __IO
Definition: core_cm7.h:287

__I
#define __I
Definition: core_cm7.h:284

Rtc
Rtc hardware registers.
Definition: component_rtc.h:41

Rtc::RTC_VERSION
__I uint32_t RTC_VERSION
(Rtc Offset: 0xFC) Version Register
Definition: component_rtc.h:57