doxygen/5.2/samv71_2component_2component__mcan_8h_source.html

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/*                  Atmel Microcontroller Software Support                      */

/*                       SAM Software Package License                           */

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/* Copyright (c) 2015, Atmel Corporation                                        */

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#ifndef _SAMV71_MCAN_COMPONENT_

#define _SAMV71_MCAN_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __I  uint32_t MCAN_CREL;

  __I  uint32_t MCAN_ENDN;

  __IO uint32_t MCAN_CUST;

  __IO uint32_t MCAN_FBTP;

  __IO uint32_t MCAN_TEST;

  __IO uint32_t MCAN_RWD;

  __IO uint32_t MCAN_CCCR;

  __IO uint32_t MCAN_BTP;

  __IO uint32_t MCAN_TSCC;

  __IO uint32_t MCAN_TSCV;

  __IO uint32_t MCAN_TOCC;

  __IO uint32_t MCAN_TOCV;

  __I  uint32_t Reserved1[4];

  __I  uint32_t MCAN_ECR;

  __I  uint32_t MCAN_PSR;

  __I  uint32_t Reserved2[2];

  __IO uint32_t MCAN_IR;

  __IO uint32_t MCAN_IE;

  __IO uint32_t MCAN_ILS;

  __IO uint32_t MCAN_ILE;

  __I  uint32_t Reserved3[8];

  __IO uint32_t MCAN_GFC;

  __IO uint32_t MCAN_SIDFC;

  __IO uint32_t MCAN_XIDFC;

  __I  uint32_t Reserved4[1];

  __IO uint32_t MCAN_XIDAM;

  __I  uint32_t MCAN_HPMS;

  __IO uint32_t MCAN_NDAT1;

  __IO uint32_t MCAN_NDAT2;

  __IO uint32_t MCAN_RXF0C;

  __I  uint32_t MCAN_RXF0S;

  __IO uint32_t MCAN_RXF0A;

  __IO uint32_t MCAN_RXBC;

  __IO uint32_t MCAN_RXF1C;

  __I  uint32_t MCAN_RXF1S;

  __IO uint32_t MCAN_RXF1A;

  __IO uint32_t MCAN_RXESC;

  __IO uint32_t MCAN_TXBC;

  __I  uint32_t MCAN_TXFQS;

  __IO uint32_t MCAN_TXESC;

  __I  uint32_t MCAN_TXBRP;

  __IO uint32_t MCAN_TXBAR;

  __IO uint32_t MCAN_TXBCR;

  __I  uint32_t MCAN_TXBTO;

  __I  uint32_t MCAN_TXBCF;

  __IO uint32_t MCAN_TXBTIE;

  __IO uint32_t MCAN_TXBCIE;

  __I  uint32_t Reserved5[2];

  __IO uint32_t MCAN_TXEFC;

  __I  uint32_t MCAN_TXEFS;

  __IO uint32_t MCAN_TXEFA;

} Mcan;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- MCAN_CREL : (MCAN Offset: 0x00) Core Release Register -------- */

#define MCAN_CREL_DAY_Pos 0

#define MCAN_CREL_DAY_Msk (0xffu << MCAN_CREL_DAY_Pos)

#define MCAN_CREL_MON_Pos 8

#define MCAN_CREL_MON_Msk (0xffu << MCAN_CREL_MON_Pos)

#define MCAN_CREL_YEAR_Pos 16

#define MCAN_CREL_YEAR_Msk (0xfu << MCAN_CREL_YEAR_Pos)

#define MCAN_CREL_SUBSTEP_Pos 20

#define MCAN_CREL_SUBSTEP_Msk (0xfu << MCAN_CREL_SUBSTEP_Pos)

#define MCAN_CREL_STEP_Pos 24

#define MCAN_CREL_STEP_Msk (0xfu << MCAN_CREL_STEP_Pos)

#define MCAN_CREL_REL_Pos 28

#define MCAN_CREL_REL_Msk (0xfu << MCAN_CREL_REL_Pos)

/* -------- MCAN_ENDN : (MCAN Offset: 0x04) Endian Register -------- */

#define MCAN_ENDN_ETV_Pos 0

#define MCAN_ENDN_ETV_Msk (0xffffffffu << MCAN_ENDN_ETV_Pos)

/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */

#define MCAN_CUST_CSV_Pos 0

#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos)

#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)))

/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */

#define MCAN_FBTP_FSJW_Pos 0

#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos)

#define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos)))

#define MCAN_FBTP_FTSEG2_Pos 4

#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos)

#define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos)))

#define MCAN_FBTP_FTSEG1_Pos 8

#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos)

#define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos)))

#define MCAN_FBTP_FBRP_Pos 16

#define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos)

#define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos)))

#define MCAN_FBTP_TDC (0x1u << 23)

#define   MCAN_FBTP_TDC_DISABLED (0x0u << 23)

#define   MCAN_FBTP_TDC_ENABLED (0x1u << 23)

#define MCAN_FBTP_TDCO_Pos 24

#define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos)

#define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos)))

/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */

#define MCAN_TEST_LBCK (0x1u << 4)

#define   MCAN_TEST_LBCK_DISABLED (0x0u << 4)

#define   MCAN_TEST_LBCK_ENABLED (0x1u << 4)

#define MCAN_TEST_TX_Pos 5

#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos)

#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos)))

#define   MCAN_TEST_TX_RESET (0x0u << 5)

#define   MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5)

#define   MCAN_TEST_TX_DOMINANT (0x2u << 5)

#define   MCAN_TEST_TX_RECESSIVE (0x3u << 5)

#define MCAN_TEST_RX (0x1u << 7)

#define MCAN_TEST_TDCV_Pos 8

#define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos)

#define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos)))

/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */

#define MCAN_RWD_WDC_Pos 0

#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos)

#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos)))

#define MCAN_RWD_WDV_Pos 8

#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos)

#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos)))

/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */

#define MCAN_CCCR_INIT (0x1u << 0)

#define   MCAN_CCCR_INIT_DISABLED (0x0u << 0)

#define   MCAN_CCCR_INIT_ENABLED (0x1u << 0)

#define MCAN_CCCR_CCE (0x1u << 1)

#define   MCAN_CCCR_CCE_PROTECTED (0x0u << 1)

#define   MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1)

#define MCAN_CCCR_ASM (0x1u << 2)

#define   MCAN_CCCR_ASM_NORMAL (0x0u << 2)

#define   MCAN_CCCR_ASM_RESTRICTED (0x1u << 2)

#define MCAN_CCCR_CSA (0x1u << 3)

#define MCAN_CCCR_CSR (0x1u << 4)

#define   MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4)

#define   MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4)

#define MCAN_CCCR_MON (0x1u << 5)

#define   MCAN_CCCR_MON_DISABLED (0x0u << 5)

#define   MCAN_CCCR_MON_ENABLED (0x1u << 5)

#define MCAN_CCCR_DAR (0x1u << 6)

#define   MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6)

#define   MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6)

#define MCAN_CCCR_TEST (0x1u << 7)

#define   MCAN_CCCR_TEST_DISABLED (0x0u << 7)

#define   MCAN_CCCR_TEST_ENABLED (0x1u << 7)

#define MCAN_CCCR_CME_Pos 8

#define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos)

#define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos)))

#define   MCAN_CCCR_CME_ISO11898_1 (0x0u << 8)

#define   MCAN_CCCR_CME_FD (0x1u << 8)

#define MCAN_CCCR_CMR_Pos 10

#define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos)

#define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos)))

#define   MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10)

#define   MCAN_CCCR_CMR_FD (0x1u << 10)

#define   MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10)

#define   MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10)

#define MCAN_CCCR_FDO (0x1u << 12)

#define MCAN_CCCR_FDBS (0x1u << 13)

#define MCAN_CCCR_TXP (0x1u << 14)

/* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */

#define MCAN_BTP_SJW_Pos 0

#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos)

#define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos)))

#define MCAN_BTP_TSEG2_Pos 4

#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos)

#define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos)))

#define MCAN_BTP_TSEG1_Pos 8

#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos)

#define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos)))

#define MCAN_BTP_BRP_Pos 16

#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos)

#define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos)))

/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */

#define MCAN_TSCC_TSS_Pos 0

#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos)

#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos)))

#define   MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0)

#define   MCAN_TSCC_TSS_TCP_INC (0x1u << 0)

#define   MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0)

#define MCAN_TSCC_TCP_Pos 16

#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos)

#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos)))

/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */

#define MCAN_TSCV_TSC_Pos 0

#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos)

#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos)))

/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */

#define MCAN_TOCC_ETOC (0x1u << 0)

#define   MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0)

#define   MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0)

#define MCAN_TOCC_TOS_Pos 1

#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos)

#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos)))

#define   MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1)

#define   MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1)

#define   MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1)

#define   MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1)

#define MCAN_TOCC_TOP_Pos 16

#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos)

#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos)))

/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */

#define MCAN_TOCV_TOC_Pos 0

#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos)

#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos)))

/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */

#define MCAN_ECR_TEC_Pos 0

#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos)

#define MCAN_ECR_REC_Pos 8

#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos)

#define MCAN_ECR_RP (0x1u << 15)

#define MCAN_ECR_CEL_Pos 16

#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos)

/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */

#define MCAN_PSR_LEC_Pos 0

#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos)

#define   MCAN_PSR_LEC_NO_ERROR (0x0u << 0)

#define   MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0)

#define   MCAN_PSR_LEC_FORM_ERROR (0x2u << 0)

#define   MCAN_PSR_LEC_ACK_ERROR (0x3u << 0)

#define   MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0)

#define   MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0)

#define   MCAN_PSR_LEC_CRC_ERROR (0x6u << 0)

#define   MCAN_PSR_LEC_NO_CHANGE (0x7u << 0)

#define MCAN_PSR_ACT_Pos 3

#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos)

#define   MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3)

#define   MCAN_PSR_ACT_IDLE (0x1u << 3)

#define   MCAN_PSR_ACT_RECEIVER (0x2u << 3)

#define   MCAN_PSR_ACT_TRANSMITTER (0x3u << 3)

#define MCAN_PSR_EP (0x1u << 5)

#define MCAN_PSR_EW (0x1u << 6)

#define MCAN_PSR_BO (0x1u << 7)

#define MCAN_PSR_FLEC_Pos 8

#define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos)

#define MCAN_PSR_RESI (0x1u << 11)

#define MCAN_PSR_RBRS (0x1u << 12)

#define MCAN_PSR_REDL (0x1u << 13)

/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */

#define MCAN_IR_RF0N (0x1u << 0)

#define MCAN_IR_RF0W (0x1u << 1)

#define MCAN_IR_RF0F (0x1u << 2)

#define MCAN_IR_RF0L (0x1u << 3)

#define MCAN_IR_RF1N (0x1u << 4)

#define MCAN_IR_RF1W (0x1u << 5)

#define MCAN_IR_RF1F (0x1u << 6)

#define MCAN_IR_RF1L (0x1u << 7)

#define MCAN_IR_HPM (0x1u << 8)

#define MCAN_IR_TC (0x1u << 9)

#define MCAN_IR_TCF (0x1u << 10)

#define MCAN_IR_TFE (0x1u << 11)

#define MCAN_IR_TEFN (0x1u << 12)

#define MCAN_IR_TEFW (0x1u << 13)

#define MCAN_IR_TEFF (0x1u << 14)

#define MCAN_IR_TEFL (0x1u << 15)

#define MCAN_IR_TSW (0x1u << 16)

#define MCAN_IR_MRAF (0x1u << 17)

#define MCAN_IR_TOO (0x1u << 18)

#define MCAN_IR_DRX (0x1u << 19)

#define MCAN_IR_BEC (0x1u << 20)

#define MCAN_IR_BEU (0x1u << 21)

#define MCAN_IR_ELO (0x1u << 22)

#define MCAN_IR_EP (0x1u << 23)

#define MCAN_IR_EW (0x1u << 24)

#define MCAN_IR_BO (0x1u << 25)

#define MCAN_IR_WDI (0x1u << 26)

#define MCAN_IR_CRCE (0x1u << 27)

#define MCAN_IR_BE (0x1u << 28)

#define MCAN_IR_ACKE (0x1u << 29)

#define MCAN_IR_FOE (0x1u << 30)

#define MCAN_IR_STE (0x1u << 31)

/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */

#define MCAN_IE_RF0NE (0x1u << 0)

#define MCAN_IE_RF0WE (0x1u << 1)

#define MCAN_IE_RF0FE (0x1u << 2)

#define MCAN_IE_RF0LE (0x1u << 3)

#define MCAN_IE_RF1NE (0x1u << 4)

#define MCAN_IE_RF1WE (0x1u << 5)

#define MCAN_IE_RF1FE (0x1u << 6)

#define MCAN_IE_RF1LE (0x1u << 7)

#define MCAN_IE_HPME (0x1u << 8)

#define MCAN_IE_TCE (0x1u << 9)

#define MCAN_IE_TCFE (0x1u << 10)

#define MCAN_IE_TFEE (0x1u << 11)

#define MCAN_IE_TEFNE (0x1u << 12)

#define MCAN_IE_TEFWE (0x1u << 13)

#define MCAN_IE_TEFFE (0x1u << 14)

#define MCAN_IE_TEFLE (0x1u << 15)

#define MCAN_IE_TSWE (0x1u << 16)

#define MCAN_IE_MRAFE (0x1u << 17)

#define MCAN_IE_TOOE (0x1u << 18)

#define MCAN_IE_DRXE (0x1u << 19)

#define MCAN_IE_BECE (0x1u << 20)

#define MCAN_IE_BEUE (0x1u << 21)

#define MCAN_IE_ELOE (0x1u << 22)

#define MCAN_IE_EPE (0x1u << 23)

#define MCAN_IE_EWE (0x1u << 24)

#define MCAN_IE_BOE (0x1u << 25)

#define MCAN_IE_WDIE (0x1u << 26)

#define MCAN_IE_CRCEE (0x1u << 27)

#define MCAN_IE_BEE (0x1u << 28)

#define MCAN_IE_ACKEE (0x1u << 29)

#define MCAN_IE_FOEE (0x1u << 30)

#define MCAN_IE_STEE (0x1u << 31)

/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */

#define MCAN_ILS_RF0NL (0x1u << 0)

#define MCAN_ILS_RF0WL (0x1u << 1)

#define MCAN_ILS_RF0FL (0x1u << 2)

#define MCAN_ILS_RF0LL (0x1u << 3)

#define MCAN_ILS_RF1NL (0x1u << 4)

#define MCAN_ILS_RF1WL (0x1u << 5)

#define MCAN_ILS_RF1FL (0x1u << 6)

#define MCAN_ILS_RF1LL (0x1u << 7)

#define MCAN_ILS_HPML (0x1u << 8)

#define MCAN_ILS_TCL (0x1u << 9)

#define MCAN_ILS_TCFL (0x1u << 10)

#define MCAN_ILS_TFEL (0x1u << 11)

#define MCAN_ILS_TEFNL (0x1u << 12)

#define MCAN_ILS_TEFWL (0x1u << 13)

#define MCAN_ILS_TEFFL (0x1u << 14)

#define MCAN_ILS_TEFLL (0x1u << 15)

#define MCAN_ILS_TSWL (0x1u << 16)

#define MCAN_ILS_MRAFL (0x1u << 17)

#define MCAN_ILS_TOOL (0x1u << 18)

#define MCAN_ILS_DRXL (0x1u << 19)

#define MCAN_ILS_BECL (0x1u << 20)

#define MCAN_ILS_BEUL (0x1u << 21)

#define MCAN_ILS_ELOL (0x1u << 22)

#define MCAN_ILS_EPL (0x1u << 23)

#define MCAN_ILS_EWL (0x1u << 24)

#define MCAN_ILS_BOL (0x1u << 25)

#define MCAN_ILS_WDIL (0x1u << 26)

#define MCAN_ILS_CRCEL (0x1u << 27)

#define MCAN_ILS_BEL (0x1u << 28)

#define MCAN_ILS_ACKEL (0x1u << 29)

#define MCAN_ILS_FOEL (0x1u << 30)

#define MCAN_ILS_STEL (0x1u << 31)

/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */

#define MCAN_ILE_EINT0 (0x1u << 0)

#define MCAN_ILE_EINT1 (0x1u << 1)

/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */

#define MCAN_GFC_RRFE (0x1u << 0)

#define   MCAN_GFC_RRFE_FILTER (0x0u << 0)

#define   MCAN_GFC_RRFE_REJECT (0x1u << 0)

#define MCAN_GFC_RRFS (0x1u << 1)

#define   MCAN_GFC_RRFS_FILTER (0x0u << 1)

#define   MCAN_GFC_RRFS_REJECT (0x1u << 1)

#define MCAN_GFC_ANFE_Pos 2

#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos)

#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos)))

#define   MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2)

#define   MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2)

#define MCAN_GFC_ANFS_Pos 4

#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos)

#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos)))

#define   MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4)

#define   MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4)

/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */

#define MCAN_SIDFC_FLSSA_Pos 2

#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos)

#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos)))

#define MCAN_SIDFC_LSS_Pos 16

#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos)

#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos)))

/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */

#define MCAN_XIDFC_FLESA_Pos 2

#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos)

#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos)))

#define MCAN_XIDFC_LSE_Pos 16

#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos)

#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos)))

/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */

#define MCAN_XIDAM_EIDM_Pos 0

#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos)

#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos)))

/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */

#define MCAN_HPMS_BIDX_Pos 0

#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos)

#define MCAN_HPMS_MSI_Pos 6

#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos)

#define   MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6)

#define   MCAN_HPMS_MSI_LOST (0x1u << 6)

#define   MCAN_HPMS_MSI_FIFO_0 (0x2u << 6)

#define   MCAN_HPMS_MSI_FIFO_1 (0x3u << 6)

#define MCAN_HPMS_FIDX_Pos 8

#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos)

#define MCAN_HPMS_FLST (0x1u << 15)

/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */

#define MCAN_NDAT1_ND0 (0x1u << 0)

#define MCAN_NDAT1_ND1 (0x1u << 1)

#define MCAN_NDAT1_ND2 (0x1u << 2)

#define MCAN_NDAT1_ND3 (0x1u << 3)

#define MCAN_NDAT1_ND4 (0x1u << 4)

#define MCAN_NDAT1_ND5 (0x1u << 5)

#define MCAN_NDAT1_ND6 (0x1u << 6)

#define MCAN_NDAT1_ND7 (0x1u << 7)

#define MCAN_NDAT1_ND8 (0x1u << 8)

#define MCAN_NDAT1_ND9 (0x1u << 9)

#define MCAN_NDAT1_ND10 (0x1u << 10)

#define MCAN_NDAT1_ND11 (0x1u << 11)

#define MCAN_NDAT1_ND12 (0x1u << 12)

#define MCAN_NDAT1_ND13 (0x1u << 13)

#define MCAN_NDAT1_ND14 (0x1u << 14)

#define MCAN_NDAT1_ND15 (0x1u << 15)

#define MCAN_NDAT1_ND16 (0x1u << 16)

#define MCAN_NDAT1_ND17 (0x1u << 17)

#define MCAN_NDAT1_ND18 (0x1u << 18)

#define MCAN_NDAT1_ND19 (0x1u << 19)

#define MCAN_NDAT1_ND20 (0x1u << 20)

#define MCAN_NDAT1_ND21 (0x1u << 21)

#define MCAN_NDAT1_ND22 (0x1u << 22)

#define MCAN_NDAT1_ND23 (0x1u << 23)

#define MCAN_NDAT1_ND24 (0x1u << 24)

#define MCAN_NDAT1_ND25 (0x1u << 25)

#define MCAN_NDAT1_ND26 (0x1u << 26)

#define MCAN_NDAT1_ND27 (0x1u << 27)

#define MCAN_NDAT1_ND28 (0x1u << 28)

#define MCAN_NDAT1_ND29 (0x1u << 29)

#define MCAN_NDAT1_ND30 (0x1u << 30)

#define MCAN_NDAT1_ND31 (0x1u << 31)

/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */

#define MCAN_NDAT2_ND32 (0x1u << 0)

#define MCAN_NDAT2_ND33 (0x1u << 1)

#define MCAN_NDAT2_ND34 (0x1u << 2)

#define MCAN_NDAT2_ND35 (0x1u << 3)

#define MCAN_NDAT2_ND36 (0x1u << 4)

#define MCAN_NDAT2_ND37 (0x1u << 5)

#define MCAN_NDAT2_ND38 (0x1u << 6)

#define MCAN_NDAT2_ND39 (0x1u << 7)

#define MCAN_NDAT2_ND40 (0x1u << 8)

#define MCAN_NDAT2_ND41 (0x1u << 9)

#define MCAN_NDAT2_ND42 (0x1u << 10)

#define MCAN_NDAT2_ND43 (0x1u << 11)

#define MCAN_NDAT2_ND44 (0x1u << 12)

#define MCAN_NDAT2_ND45 (0x1u << 13)

#define MCAN_NDAT2_ND46 (0x1u << 14)

#define MCAN_NDAT2_ND47 (0x1u << 15)

#define MCAN_NDAT2_ND48 (0x1u << 16)

#define MCAN_NDAT2_ND49 (0x1u << 17)

#define MCAN_NDAT2_ND50 (0x1u << 18)

#define MCAN_NDAT2_ND51 (0x1u << 19)

#define MCAN_NDAT2_ND52 (0x1u << 20)

#define MCAN_NDAT2_ND53 (0x1u << 21)

#define MCAN_NDAT2_ND54 (0x1u << 22)

#define MCAN_NDAT2_ND55 (0x1u << 23)

#define MCAN_NDAT2_ND56 (0x1u << 24)

#define MCAN_NDAT2_ND57 (0x1u << 25)

#define MCAN_NDAT2_ND58 (0x1u << 26)

#define MCAN_NDAT2_ND59 (0x1u << 27)

#define MCAN_NDAT2_ND60 (0x1u << 28)

#define MCAN_NDAT2_ND61 (0x1u << 29)

#define MCAN_NDAT2_ND62 (0x1u << 30)

#define MCAN_NDAT2_ND63 (0x1u << 31)

/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */

#define MCAN_RXF0C_F0SA_Pos 2

#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos)

#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos)))

#define MCAN_RXF0C_F0S_Pos 16

#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos)

#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos)))

#define MCAN_RXF0C_F0WM_Pos 24

#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos)

#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos)))

#define MCAN_RXF0C_F0OM (0x1u << 31)

/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */

#define MCAN_RXF0S_F0FL_Pos 0

#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos)

#define MCAN_RXF0S_F0GI_Pos 8

#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos)

#define MCAN_RXF0S_F0PI_Pos 16

#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos)

#define MCAN_RXF0S_F0F (0x1u << 24)

#define MCAN_RXF0S_RF0L (0x1u << 25)

/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */

#define MCAN_RXF0A_F0AI_Pos 0

#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos)

#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos)))

/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */

#define MCAN_RXBC_RBSA_Pos 2

#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos)

#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos)))

/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */

#define MCAN_RXF1C_F1SA_Pos 2

#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos)

#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos)))

#define MCAN_RXF1C_F1S_Pos 16

#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos)

#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos)))

#define MCAN_RXF1C_F1WM_Pos 24

#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos)

#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos)))

#define MCAN_RXF1C_F1OM (0x1u << 31)

/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */

#define MCAN_RXF1S_F1FL_Pos 0

#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos)

#define MCAN_RXF1S_F1GI_Pos 8

#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos)

#define MCAN_RXF1S_F1PI_Pos 16

#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos)

#define MCAN_RXF1S_F1F (0x1u << 24)

#define MCAN_RXF1S_RF1L (0x1u << 25)

#define MCAN_RXF1S_DMS_Pos 30

#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos)

#define   MCAN_RXF1S_DMS_IDLE (0x0u << 30)

#define   MCAN_RXF1S_DMS_MSG_A (0x1u << 30)

#define   MCAN_RXF1S_DMS_MSG_AB (0x2u << 30)

#define   MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30)

/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */

#define MCAN_RXF1A_F1AI_Pos 0

#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos)

#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos)))

/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */

#define MCAN_RXESC_F0DS_Pos 0

#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos)

#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos)))

#define   MCAN_RXESC_F0DS_8_BYTE (0x0u << 0)

#define   MCAN_RXESC_F0DS_12_BYTE (0x1u << 0)

#define   MCAN_RXESC_F0DS_16_BYTE (0x2u << 0)

#define   MCAN_RXESC_F0DS_20_BYTE (0x3u << 0)

#define   MCAN_RXESC_F0DS_24_BYTE (0x4u << 0)

#define   MCAN_RXESC_F0DS_32_BYTE (0x5u << 0)

#define   MCAN_RXESC_F0DS_48_BYTE (0x6u << 0)

#define   MCAN_RXESC_F0DS_64_BYTE (0x7u << 0)

#define MCAN_RXESC_F1DS_Pos 4

#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos)

#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos)))

#define   MCAN_RXESC_F1DS_8_BYTE (0x0u << 4)

#define   MCAN_RXESC_F1DS_12_BYTE (0x1u << 4)

#define   MCAN_RXESC_F1DS_16_BYTE (0x2u << 4)

#define   MCAN_RXESC_F1DS_20_BYTE (0x3u << 4)

#define   MCAN_RXESC_F1DS_24_BYTE (0x4u << 4)

#define   MCAN_RXESC_F1DS_32_BYTE (0x5u << 4)

#define   MCAN_RXESC_F1DS_48_BYTE (0x6u << 4)

#define   MCAN_RXESC_F1DS_64_BYTE (0x7u << 4)

#define MCAN_RXESC_RBDS_Pos 8

#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos)

#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos)))

#define   MCAN_RXESC_RBDS_8_BYTE (0x0u << 8)

#define   MCAN_RXESC_RBDS_12_BYTE (0x1u << 8)

#define   MCAN_RXESC_RBDS_16_BYTE (0x2u << 8)

#define   MCAN_RXESC_RBDS_20_BYTE (0x3u << 8)

#define   MCAN_RXESC_RBDS_24_BYTE (0x4u << 8)

#define   MCAN_RXESC_RBDS_32_BYTE (0x5u << 8)

#define   MCAN_RXESC_RBDS_48_BYTE (0x6u << 8)

#define   MCAN_RXESC_RBDS_64_BYTE (0x7u << 8)

/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */

#define MCAN_TXBC_TBSA_Pos 2

#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos)

#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos)))

#define MCAN_TXBC_NDTB_Pos 16

#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos)

#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos)))

#define MCAN_TXBC_TFQS_Pos 24

#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos)

#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos)))

#define MCAN_TXBC_TFQM (0x1u << 30)

/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */

#define MCAN_TXFQS_TFFL_Pos 0

#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos)

#define MCAN_TXFQS_TFGI_Pos 8

#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos)

#define MCAN_TXFQS_TFQPI_Pos 16

#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos)

#define MCAN_TXFQS_TFQF (0x1u << 21)

/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */

#define MCAN_TXESC_TBDS_Pos 0

#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos)

#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos)))

#define   MCAN_TXESC_TBDS_8_BYTE (0x0u << 0)

#define   MCAN_TXESC_TBDS_12_BYTE (0x1u << 0)

#define   MCAN_TXESC_TBDS_16_BYTE (0x2u << 0)

#define   MCAN_TXESC_TBDS_20_BYTE (0x3u << 0)

#define   MCAN_TXESC_TBDS_24_BYTE (0x4u << 0)

#define   MCAN_TXESC_TBDS_32_BYTE (0x5u << 0)

#define   MCAN_TXESC_TBDS_48_BYTE (0x6u << 0)

#define   MCAN_TXESC_TBDS_64_BYTE (0x7u << 0)

/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */

#define MCAN_TXBRP_TRP0 (0x1u << 0)

#define MCAN_TXBRP_TRP1 (0x1u << 1)

#define MCAN_TXBRP_TRP2 (0x1u << 2)

#define MCAN_TXBRP_TRP3 (0x1u << 3)

#define MCAN_TXBRP_TRP4 (0x1u << 4)

#define MCAN_TXBRP_TRP5 (0x1u << 5)

#define MCAN_TXBRP_TRP6 (0x1u << 6)

#define MCAN_TXBRP_TRP7 (0x1u << 7)

#define MCAN_TXBRP_TRP8 (0x1u << 8)

#define MCAN_TXBRP_TRP9 (0x1u << 9)

#define MCAN_TXBRP_TRP10 (0x1u << 10)

#define MCAN_TXBRP_TRP11 (0x1u << 11)

#define MCAN_TXBRP_TRP12 (0x1u << 12)

#define MCAN_TXBRP_TRP13 (0x1u << 13)

#define MCAN_TXBRP_TRP14 (0x1u << 14)

#define MCAN_TXBRP_TRP15 (0x1u << 15)

#define MCAN_TXBRP_TRP16 (0x1u << 16)

#define MCAN_TXBRP_TRP17 (0x1u << 17)

#define MCAN_TXBRP_TRP18 (0x1u << 18)

#define MCAN_TXBRP_TRP19 (0x1u << 19)

#define MCAN_TXBRP_TRP20 (0x1u << 20)

#define MCAN_TXBRP_TRP21 (0x1u << 21)

#define MCAN_TXBRP_TRP22 (0x1u << 22)

#define MCAN_TXBRP_TRP23 (0x1u << 23)

#define MCAN_TXBRP_TRP24 (0x1u << 24)

#define MCAN_TXBRP_TRP25 (0x1u << 25)

#define MCAN_TXBRP_TRP26 (0x1u << 26)

#define MCAN_TXBRP_TRP27 (0x1u << 27)

#define MCAN_TXBRP_TRP28 (0x1u << 28)

#define MCAN_TXBRP_TRP29 (0x1u << 29)

#define MCAN_TXBRP_TRP30 (0x1u << 30)

#define MCAN_TXBRP_TRP31 (0x1u << 31)

/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */

#define MCAN_TXBAR_AR0 (0x1u << 0)

#define MCAN_TXBAR_AR1 (0x1u << 1)

#define MCAN_TXBAR_AR2 (0x1u << 2)

#define MCAN_TXBAR_AR3 (0x1u << 3)

#define MCAN_TXBAR_AR4 (0x1u << 4)

#define MCAN_TXBAR_AR5 (0x1u << 5)

#define MCAN_TXBAR_AR6 (0x1u << 6)

#define MCAN_TXBAR_AR7 (0x1u << 7)

#define MCAN_TXBAR_AR8 (0x1u << 8)

#define MCAN_TXBAR_AR9 (0x1u << 9)

#define MCAN_TXBAR_AR10 (0x1u << 10)

#define MCAN_TXBAR_AR11 (0x1u << 11)

#define MCAN_TXBAR_AR12 (0x1u << 12)

#define MCAN_TXBAR_AR13 (0x1u << 13)

#define MCAN_TXBAR_AR14 (0x1u << 14)

#define MCAN_TXBAR_AR15 (0x1u << 15)

#define MCAN_TXBAR_AR16 (0x1u << 16)

#define MCAN_TXBAR_AR17 (0x1u << 17)

#define MCAN_TXBAR_AR18 (0x1u << 18)

#define MCAN_TXBAR_AR19 (0x1u << 19)

#define MCAN_TXBAR_AR20 (0x1u << 20)

#define MCAN_TXBAR_AR21 (0x1u << 21)

#define MCAN_TXBAR_AR22 (0x1u << 22)

#define MCAN_TXBAR_AR23 (0x1u << 23)

#define MCAN_TXBAR_AR24 (0x1u << 24)

#define MCAN_TXBAR_AR25 (0x1u << 25)

#define MCAN_TXBAR_AR26 (0x1u << 26)

#define MCAN_TXBAR_AR27 (0x1u << 27)

#define MCAN_TXBAR_AR28 (0x1u << 28)

#define MCAN_TXBAR_AR29 (0x1u << 29)

#define MCAN_TXBAR_AR30 (0x1u << 30)

#define MCAN_TXBAR_AR31 (0x1u << 31)

/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */

#define MCAN_TXBCR_CR0 (0x1u << 0)

#define MCAN_TXBCR_CR1 (0x1u << 1)

#define MCAN_TXBCR_CR2 (0x1u << 2)

#define MCAN_TXBCR_CR3 (0x1u << 3)

#define MCAN_TXBCR_CR4 (0x1u << 4)

#define MCAN_TXBCR_CR5 (0x1u << 5)

#define MCAN_TXBCR_CR6 (0x1u << 6)

#define MCAN_TXBCR_CR7 (0x1u << 7)

#define MCAN_TXBCR_CR8 (0x1u << 8)

#define MCAN_TXBCR_CR9 (0x1u << 9)

#define MCAN_TXBCR_CR10 (0x1u << 10)

#define MCAN_TXBCR_CR11 (0x1u << 11)

#define MCAN_TXBCR_CR12 (0x1u << 12)

#define MCAN_TXBCR_CR13 (0x1u << 13)

#define MCAN_TXBCR_CR14 (0x1u << 14)

#define MCAN_TXBCR_CR15 (0x1u << 15)

#define MCAN_TXBCR_CR16 (0x1u << 16)

#define MCAN_TXBCR_CR17 (0x1u << 17)

#define MCAN_TXBCR_CR18 (0x1u << 18)

#define MCAN_TXBCR_CR19 (0x1u << 19)

#define MCAN_TXBCR_CR20 (0x1u << 20)

#define MCAN_TXBCR_CR21 (0x1u << 21)

#define MCAN_TXBCR_CR22 (0x1u << 22)

#define MCAN_TXBCR_CR23 (0x1u << 23)

#define MCAN_TXBCR_CR24 (0x1u << 24)

#define MCAN_TXBCR_CR25 (0x1u << 25)

#define MCAN_TXBCR_CR26 (0x1u << 26)

#define MCAN_TXBCR_CR27 (0x1u << 27)

#define MCAN_TXBCR_CR28 (0x1u << 28)

#define MCAN_TXBCR_CR29 (0x1u << 29)

#define MCAN_TXBCR_CR30 (0x1u << 30)

#define MCAN_TXBCR_CR31 (0x1u << 31)

/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */

#define MCAN_TXBTO_TO0 (0x1u << 0)

#define MCAN_TXBTO_TO1 (0x1u << 1)

#define MCAN_TXBTO_TO2 (0x1u << 2)

#define MCAN_TXBTO_TO3 (0x1u << 3)

#define MCAN_TXBTO_TO4 (0x1u << 4)

#define MCAN_TXBTO_TO5 (0x1u << 5)

#define MCAN_TXBTO_TO6 (0x1u << 6)

#define MCAN_TXBTO_TO7 (0x1u << 7)

#define MCAN_TXBTO_TO8 (0x1u << 8)

#define MCAN_TXBTO_TO9 (0x1u << 9)

#define MCAN_TXBTO_TO10 (0x1u << 10)

#define MCAN_TXBTO_TO11 (0x1u << 11)

#define MCAN_TXBTO_TO12 (0x1u << 12)

#define MCAN_TXBTO_TO13 (0x1u << 13)

#define MCAN_TXBTO_TO14 (0x1u << 14)

#define MCAN_TXBTO_TO15 (0x1u << 15)

#define MCAN_TXBTO_TO16 (0x1u << 16)

#define MCAN_TXBTO_TO17 (0x1u << 17)

#define MCAN_TXBTO_TO18 (0x1u << 18)

#define MCAN_TXBTO_TO19 (0x1u << 19)

#define MCAN_TXBTO_TO20 (0x1u << 20)

#define MCAN_TXBTO_TO21 (0x1u << 21)

#define MCAN_TXBTO_TO22 (0x1u << 22)

#define MCAN_TXBTO_TO23 (0x1u << 23)

#define MCAN_TXBTO_TO24 (0x1u << 24)

#define MCAN_TXBTO_TO25 (0x1u << 25)

#define MCAN_TXBTO_TO26 (0x1u << 26)

#define MCAN_TXBTO_TO27 (0x1u << 27)

#define MCAN_TXBTO_TO28 (0x1u << 28)

#define MCAN_TXBTO_TO29 (0x1u << 29)

#define MCAN_TXBTO_TO30 (0x1u << 30)

#define MCAN_TXBTO_TO31 (0x1u << 31)

/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */

#define MCAN_TXBCF_CF0 (0x1u << 0)

#define MCAN_TXBCF_CF1 (0x1u << 1)

#define MCAN_TXBCF_CF2 (0x1u << 2)

#define MCAN_TXBCF_CF3 (0x1u << 3)

#define MCAN_TXBCF_CF4 (0x1u << 4)

#define MCAN_TXBCF_CF5 (0x1u << 5)

#define MCAN_TXBCF_CF6 (0x1u << 6)

#define MCAN_TXBCF_CF7 (0x1u << 7)

#define MCAN_TXBCF_CF8 (0x1u << 8)

#define MCAN_TXBCF_CF9 (0x1u << 9)

#define MCAN_TXBCF_CF10 (0x1u << 10)

#define MCAN_TXBCF_CF11 (0x1u << 11)

#define MCAN_TXBCF_CF12 (0x1u << 12)

#define MCAN_TXBCF_CF13 (0x1u << 13)

#define MCAN_TXBCF_CF14 (0x1u << 14)

#define MCAN_TXBCF_CF15 (0x1u << 15)

#define MCAN_TXBCF_CF16 (0x1u << 16)

#define MCAN_TXBCF_CF17 (0x1u << 17)

#define MCAN_TXBCF_CF18 (0x1u << 18)

#define MCAN_TXBCF_CF19 (0x1u << 19)

#define MCAN_TXBCF_CF20 (0x1u << 20)

#define MCAN_TXBCF_CF21 (0x1u << 21)

#define MCAN_TXBCF_CF22 (0x1u << 22)

#define MCAN_TXBCF_CF23 (0x1u << 23)

#define MCAN_TXBCF_CF24 (0x1u << 24)

#define MCAN_TXBCF_CF25 (0x1u << 25)

#define MCAN_TXBCF_CF26 (0x1u << 26)

#define MCAN_TXBCF_CF27 (0x1u << 27)

#define MCAN_TXBCF_CF28 (0x1u << 28)

#define MCAN_TXBCF_CF29 (0x1u << 29)

#define MCAN_TXBCF_CF30 (0x1u << 30)

#define MCAN_TXBCF_CF31 (0x1u << 31)

/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */

#define MCAN_TXBTIE_TIE0 (0x1u << 0)

#define MCAN_TXBTIE_TIE1 (0x1u << 1)

#define MCAN_TXBTIE_TIE2 (0x1u << 2)

#define MCAN_TXBTIE_TIE3 (0x1u << 3)

#define MCAN_TXBTIE_TIE4 (0x1u << 4)

#define MCAN_TXBTIE_TIE5 (0x1u << 5)

#define MCAN_TXBTIE_TIE6 (0x1u << 6)

#define MCAN_TXBTIE_TIE7 (0x1u << 7)

#define MCAN_TXBTIE_TIE8 (0x1u << 8)

#define MCAN_TXBTIE_TIE9 (0x1u << 9)

#define MCAN_TXBTIE_TIE10 (0x1u << 10)

#define MCAN_TXBTIE_TIE11 (0x1u << 11)

#define MCAN_TXBTIE_TIE12 (0x1u << 12)

#define MCAN_TXBTIE_TIE13 (0x1u << 13)

#define MCAN_TXBTIE_TIE14 (0x1u << 14)

#define MCAN_TXBTIE_TIE15 (0x1u << 15)

#define MCAN_TXBTIE_TIE16 (0x1u << 16)

#define MCAN_TXBTIE_TIE17 (0x1u << 17)

#define MCAN_TXBTIE_TIE18 (0x1u << 18)

#define MCAN_TXBTIE_TIE19 (0x1u << 19)

#define MCAN_TXBTIE_TIE20 (0x1u << 20)

#define MCAN_TXBTIE_TIE21 (0x1u << 21)

#define MCAN_TXBTIE_TIE22 (0x1u << 22)

#define MCAN_TXBTIE_TIE23 (0x1u << 23)

#define MCAN_TXBTIE_TIE24 (0x1u << 24)

#define MCAN_TXBTIE_TIE25 (0x1u << 25)

#define MCAN_TXBTIE_TIE26 (0x1u << 26)

#define MCAN_TXBTIE_TIE27 (0x1u << 27)

#define MCAN_TXBTIE_TIE28 (0x1u << 28)

#define MCAN_TXBTIE_TIE29 (0x1u << 29)

#define MCAN_TXBTIE_TIE30 (0x1u << 30)

#define MCAN_TXBTIE_TIE31 (0x1u << 31)

/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */

#define MCAN_TXBCIE_CFIE0 (0x1u << 0)

#define MCAN_TXBCIE_CFIE1 (0x1u << 1)

#define MCAN_TXBCIE_CFIE2 (0x1u << 2)

#define MCAN_TXBCIE_CFIE3 (0x1u << 3)

#define MCAN_TXBCIE_CFIE4 (0x1u << 4)

#define MCAN_TXBCIE_CFIE5 (0x1u << 5)

#define MCAN_TXBCIE_CFIE6 (0x1u << 6)

#define MCAN_TXBCIE_CFIE7 (0x1u << 7)

#define MCAN_TXBCIE_CFIE8 (0x1u << 8)

#define MCAN_TXBCIE_CFIE9 (0x1u << 9)

#define MCAN_TXBCIE_CFIE10 (0x1u << 10)

#define MCAN_TXBCIE_CFIE11 (0x1u << 11)

#define MCAN_TXBCIE_CFIE12 (0x1u << 12)

#define MCAN_TXBCIE_CFIE13 (0x1u << 13)

#define MCAN_TXBCIE_CFIE14 (0x1u << 14)

#define MCAN_TXBCIE_CFIE15 (0x1u << 15)

#define MCAN_TXBCIE_CFIE16 (0x1u << 16)

#define MCAN_TXBCIE_CFIE17 (0x1u << 17)

#define MCAN_TXBCIE_CFIE18 (0x1u << 18)

#define MCAN_TXBCIE_CFIE19 (0x1u << 19)

#define MCAN_TXBCIE_CFIE20 (0x1u << 20)

#define MCAN_TXBCIE_CFIE21 (0x1u << 21)

#define MCAN_TXBCIE_CFIE22 (0x1u << 22)

#define MCAN_TXBCIE_CFIE23 (0x1u << 23)

#define MCAN_TXBCIE_CFIE24 (0x1u << 24)

#define MCAN_TXBCIE_CFIE25 (0x1u << 25)

#define MCAN_TXBCIE_CFIE26 (0x1u << 26)

#define MCAN_TXBCIE_CFIE27 (0x1u << 27)

#define MCAN_TXBCIE_CFIE28 (0x1u << 28)

#define MCAN_TXBCIE_CFIE29 (0x1u << 29)

#define MCAN_TXBCIE_CFIE30 (0x1u << 30)

#define MCAN_TXBCIE_CFIE31 (0x1u << 31)

/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */

#define MCAN_TXEFC_EFSA_Pos 2

#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos)

#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos)))

#define MCAN_TXEFC_EFS_Pos 16

#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos)

#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos)))

#define MCAN_TXEFC_EFWM_Pos 24

#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos)

#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos)))

/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */

#define MCAN_TXEFS_EFFL_Pos 0

#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos)

#define MCAN_TXEFS_EFGI_Pos 8

#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos)

#define MCAN_TXEFS_EFPI_Pos 16

#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos)

#define MCAN_TXEFS_EFF (0x1u << 24)

#define MCAN_TXEFS_TEFL (0x1u << 25)

/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */

#define MCAN_TXEFA_EFAI_Pos 0

#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos)

#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos)))


#endif /* _SAMV71_MCAN_COMPONENT_ */

__IO
#define __IO
Definition: core_cm7.h:287

__I
#define __I
Definition: core_cm7.h:284

Mcan
Mcan hardware registers.
Definition: component_mcan.h:41

Mcan::MCAN_ENDN
__I uint32_t MCAN_ENDN
(Mcan Offset: 0x04) Endian Register
Definition: component_mcan.h:43

Mcan::MCAN_CREL
__I uint32_t MCAN_CREL
(Mcan Offset: 0x00) Core Release Register
Definition: component_mcan.h:42