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component_matrix.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMV71_MATRIX_COMPONENT_
31#define _SAMV71_MATRIX_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __IO uint32_t MATRIX_PRAS;
43 __IO uint32_t MATRIX_PRBS;
44} MatrixPr;
46#define MATRIXPR_NUMBER 9
47typedef struct {
48 __IO uint32_t MATRIX_MCFG[12];
49 __I uint32_t Reserved1[4];
50 __IO uint32_t MATRIX_SCFG[9];
51 __I uint32_t Reserved2[7];
52 MatrixPr MATRIX_PR[MATRIXPR_NUMBER];
53 __I uint32_t Reserved3[14];
54 __IO uint32_t MATRIX_MRCR;
55 __I uint32_t Reserved4[3];
56 __IO uint32_t CCFG_CAN0;
57 __IO uint32_t CCFG_SYSIO;
58 __I uint32_t Reserved5[3];
59 __IO uint32_t CCFG_SMCNFCS;
60 __I uint32_t Reserved6[47];
61 __IO uint32_t MATRIX_WPMR;
62 __I uint32_t MATRIX_WPSR;
63 __I uint32_t Reserved7[4];
64 __I uint32_t MATRIX_VERSION;
65} Matrix;
66#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
67/* -------- MATRIX_MCFG[12] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
68#define MATRIX_MCFG_ULBT_Pos 0
69#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos)
70#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
71#define MATRIX_MCFG_ULBT_UNLTD_LENGTH (0x0u << 0)
72#define MATRIX_MCFG_ULBT_SINGLE_ACCESS (0x1u << 0)
73#define MATRIX_MCFG_ULBT_4BEAT_BURST (0x2u << 0)
74#define MATRIX_MCFG_ULBT_8BEAT_BURST (0x3u << 0)
75#define MATRIX_MCFG_ULBT_16BEAT_BURST (0x4u << 0)
76#define MATRIX_MCFG_ULBT_32BEAT_BURST (0x5u << 0)
77#define MATRIX_MCFG_ULBT_64BEAT_BURST (0x6u << 0)
78#define MATRIX_MCFG_ULBT_128BEAT_BURST (0x7u << 0)
79/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
80#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
81#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos)
82#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
83#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
84#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos)
85#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
86#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16)
87#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16)
88#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16)
89#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
90#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos)
91#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
92/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */
93#define MATRIX_PRAS_M0PR_Pos 0
94#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos)
95#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)))
96#define MATRIX_PRAS_M1PR_Pos 4
97#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos)
98#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)))
99#define MATRIX_PRAS_M2PR_Pos 8
100#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos)
101#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)))
102#define MATRIX_PRAS_M3PR_Pos 12
103#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos)
104#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)))
105#define MATRIX_PRAS_M4PR_Pos 16
106#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos)
107#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)))
108#define MATRIX_PRAS_M5PR_Pos 20
109#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos)
110#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)))
111#define MATRIX_PRAS_M6PR_Pos 24
112#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos)
113#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)))
114#define MATRIX_PRAS_M7PR_Pos 28
115#define MATRIX_PRAS_M7PR_Msk (0x3u << MATRIX_PRAS_M7PR_Pos)
116#define MATRIX_PRAS_M7PR(value) ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos)))
117/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */
118#define MATRIX_PRBS_M8PR_Pos 0
119#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos)
120#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)))
121#define MATRIX_PRBS_M9PR_Pos 4
122#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos)
123#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)))
124#define MATRIX_PRBS_M10PR_Pos 8
125#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos)
126#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)))
127#define MATRIX_PRBS_M11PR_Pos 12
128#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos)
129#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)))
130/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
131#define MATRIX_MRCR_RCB0 (0x1u << 0)
132#define MATRIX_MRCR_RCB1 (0x1u << 1)
133#define MATRIX_MRCR_RCB2 (0x1u << 2)
134#define MATRIX_MRCR_RCB3 (0x1u << 3)
135#define MATRIX_MRCR_RCB4 (0x1u << 4)
136#define MATRIX_MRCR_RCB5 (0x1u << 5)
137#define MATRIX_MRCR_RCB6 (0x1u << 6)
138#define MATRIX_MRCR_RCB7 (0x1u << 7)
139#define MATRIX_MRCR_RCB8 (0x1u << 8)
140#define MATRIX_MRCR_RCB9 (0x1u << 9)
141#define MATRIX_MRCR_RCB10 (0x1u << 10)
142#define MATRIX_MRCR_RCB11 (0x1u << 11)
143/* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */
144#define CCFG_CAN0_CAN0DMABA_Pos 16
145#define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos)
146#define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos)))
147/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */
148#define CCFG_SYSIO_SYSIO4 (0x1u << 4)
149#define CCFG_SYSIO_SYSIO5 (0x1u << 5)
150#define CCFG_SYSIO_SYSIO6 (0x1u << 6)
151#define CCFG_SYSIO_SYSIO7 (0x1u << 7)
152#define CCFG_SYSIO_SYSIO12 (0x1u << 12)
153#define CCFG_SYSIO_CAN1DMABA_Pos 16
154#define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos)
155#define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos)))
156/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */
157#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0)
158#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1)
159#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2)
160#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3)
161#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4)
162/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */
163#define MATRIX_WPMR_WPEN (0x1u << 0)
164#define MATRIX_WPMR_WPKEY_Pos 8
165#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos)
166#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
167#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8)
168/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */
169#define MATRIX_WPSR_WPVS (0x1u << 0)
170#define MATRIX_WPSR_WPVSRC_Pos 8
171#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos)
172/* -------- MATRIX_VERSION : (MATRIX Offset: 0x01FC) Version Register -------- */
173#define MATRIX_VERSION_VERSION_Pos 0
174#define MATRIX_VERSION_VERSION_Msk (0xfffu << MATRIX_VERSION_VERSION_Pos)
175#define MATRIX_VERSION_MFN_Pos 16
176#define MATRIX_VERSION_MFN_Msk (0x7u << MATRIX_VERSION_MFN_Pos)
179
180
181#endif /* _SAMV71_MATRIX_COMPONENT_ */
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
MatrixPr
MatrixPr hardware registers.
Definition: component_matrix.h:41
Matrix
Matrix hardware registers.
Definition: component_matrix.h:47
Matrix::MATRIX_VERSION
__I uint32_t MATRIX_VERSION
(Matrix Offset: 0x01FC) Version Register
Definition: component_matrix.h:64
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