doxygen/5.2/samv71_2component_2component__isi_8h_source.html

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/*                  Atmel Microcontroller Software Support                      */

/*                       SAM Software Package License                           */

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/* Copyright (c) 2015, Atmel Corporation                                        */

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#ifndef _SAMV71_ISI_COMPONENT_

#define _SAMV71_ISI_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __IO uint32_t ISI_CFG1;

  __IO uint32_t ISI_CFG2;

  __IO uint32_t ISI_PSIZE;

  __IO uint32_t ISI_PDECF;

  __IO uint32_t ISI_Y2R_SET0;

  __IO uint32_t ISI_Y2R_SET1;

  __IO uint32_t ISI_R2Y_SET0;

  __IO uint32_t ISI_R2Y_SET1;

  __IO uint32_t ISI_R2Y_SET2;

  __O  uint32_t ISI_CR;

  __I  uint32_t ISI_SR;

  __O  uint32_t ISI_IER;

  __O  uint32_t ISI_IDR;

  __I  uint32_t ISI_IMR;

  __O  uint32_t ISI_DMA_CHER;

  __O  uint32_t ISI_DMA_CHDR;

  __I  uint32_t ISI_DMA_CHSR;

  __IO uint32_t ISI_DMA_P_ADDR;

  __IO uint32_t ISI_DMA_P_CTRL;

  __IO uint32_t ISI_DMA_P_DSCR;

  __IO uint32_t ISI_DMA_C_ADDR;

  __IO uint32_t ISI_DMA_C_CTRL;

  __IO uint32_t ISI_DMA_C_DSCR;

  __I  uint32_t Reserved1[34];

  __IO uint32_t ISI_WPMR;

  __I  uint32_t ISI_WPSR;

  __I  uint32_t Reserved2[4];

  __I  uint32_t ISI_VERSION;

} Isi;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */

#define ISI_CFG1_HSYNC_POL (0x1u << 2)

#define ISI_CFG1_VSYNC_POL (0x1u << 3)

#define ISI_CFG1_PIXCLK_POL (0x1u << 4)

#define ISI_CFG1_EMB_SYNC (0x1u << 6)

#define ISI_CFG1_CRC_SYNC (0x1u << 7)

#define ISI_CFG1_FRATE_Pos 8

#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos)

#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos)))

#define ISI_CFG1_DISCR (0x1u << 11)

#define ISI_CFG1_FULL (0x1u << 12)

#define ISI_CFG1_THMASK_Pos 13

#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos)

#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos)))

#define   ISI_CFG1_THMASK_BEATS_4 (0x0u << 13)

#define   ISI_CFG1_THMASK_BEATS_8 (0x1u << 13)

#define   ISI_CFG1_THMASK_BEATS_16 (0x2u << 13)

#define ISI_CFG1_SLD_Pos 16

#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos)

#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos)))

#define ISI_CFG1_SFD_Pos 24

#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos)

#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos)))

/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */

#define ISI_CFG2_IM_VSIZE_Pos 0

#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos)

#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos)))

#define ISI_CFG2_GS_MODE (0x1u << 11)

#define ISI_CFG2_RGB_MODE (0x1u << 12)

#define ISI_CFG2_GRAYSCALE (0x1u << 13)

#define ISI_CFG2_RGB_SWAP (0x1u << 14)

#define ISI_CFG2_COL_SPACE (0x1u << 15)

#define ISI_CFG2_IM_HSIZE_Pos 16

#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos)

#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos)))

#define ISI_CFG2_YCC_SWAP_Pos 28

#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos)

#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos)))

#define   ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28)

#define   ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28)

#define   ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28)

#define   ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28)

#define ISI_CFG2_RGB_CFG_Pos 30

#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos)

#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos)))

#define   ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30)

#define   ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30)

#define   ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30)

#define   ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30)

/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */

#define ISI_PSIZE_PREV_VSIZE_Pos 0

#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos)

#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos)))

#define ISI_PSIZE_PREV_HSIZE_Pos 16

#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos)

#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos)))

/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */

#define ISI_PDECF_DEC_FACTOR_Pos 0

#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos)

#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos)))

/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */

#define ISI_Y2R_SET0_C0_Pos 0

#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos)

#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos)))

#define ISI_Y2R_SET0_C1_Pos 8

#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos)

#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos)))

#define ISI_Y2R_SET0_C2_Pos 16

#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos)

#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos)))

#define ISI_Y2R_SET0_C3_Pos 24

#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos)

#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos)))

/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */

#define ISI_Y2R_SET1_C4_Pos 0

#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos)

#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos)))

#define ISI_Y2R_SET1_Yoff (0x1u << 12)

#define ISI_Y2R_SET1_Croff (0x1u << 13)

#define ISI_Y2R_SET1_Cboff (0x1u << 14)

/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */

#define ISI_R2Y_SET0_C0_Pos 0

#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos)

#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos)))

#define ISI_R2Y_SET0_C1_Pos 8

#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos)

#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos)))

#define ISI_R2Y_SET0_C2_Pos 16

#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos)

#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos)))

#define ISI_R2Y_SET0_Roff (0x1u << 24)

/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */

#define ISI_R2Y_SET1_C3_Pos 0

#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos)

#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos)))

#define ISI_R2Y_SET1_C4_Pos 8

#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos)

#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos)))

#define ISI_R2Y_SET1_C5_Pos 16

#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos)

#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos)))

#define ISI_R2Y_SET1_Goff (0x1u << 24)

/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */

#define ISI_R2Y_SET2_C6_Pos 0

#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos)

#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos)))

#define ISI_R2Y_SET2_C7_Pos 8

#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos)

#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos)))

#define ISI_R2Y_SET2_C8_Pos 16

#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos)

#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos)))

#define ISI_R2Y_SET2_Boff (0x1u << 24)

/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */

#define ISI_CR_ISI_EN (0x1u << 0)

#define ISI_CR_ISI_DIS (0x1u << 1)

#define ISI_CR_ISI_SRST (0x1u << 2)

#define ISI_CR_ISI_CDC (0x1u << 8)

/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */

#define ISI_SR_ENABLE (0x1u << 0)

#define ISI_SR_DIS_DONE (0x1u << 1)

#define ISI_SR_SRST (0x1u << 2)

#define ISI_SR_CDC_PND (0x1u << 8)

#define ISI_SR_VSYNC (0x1u << 10)

#define ISI_SR_PXFR_DONE (0x1u << 16)

#define ISI_SR_CXFR_DONE (0x1u << 17)

#define ISI_SR_SIP (0x1u << 19)

#define ISI_SR_P_OVR (0x1u << 24)

#define ISI_SR_C_OVR (0x1u << 25)

#define ISI_SR_CRC_ERR (0x1u << 26)

#define ISI_SR_FR_OVR (0x1u << 27)

/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */

#define ISI_IER_DIS_DONE (0x1u << 1)

#define ISI_IER_SRST (0x1u << 2)

#define ISI_IER_VSYNC (0x1u << 10)

#define ISI_IER_PXFR_DONE (0x1u << 16)

#define ISI_IER_CXFR_DONE (0x1u << 17)

#define ISI_IER_P_OVR (0x1u << 24)

#define ISI_IER_C_OVR (0x1u << 25)

#define ISI_IER_CRC_ERR (0x1u << 26)

#define ISI_IER_FR_OVR (0x1u << 27)

/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */

#define ISI_IDR_DIS_DONE (0x1u << 1)

#define ISI_IDR_SRST (0x1u << 2)

#define ISI_IDR_VSYNC (0x1u << 10)

#define ISI_IDR_PXFR_DONE (0x1u << 16)

#define ISI_IDR_CXFR_DONE (0x1u << 17)

#define ISI_IDR_P_OVR (0x1u << 24)

#define ISI_IDR_C_OVR (0x1u << 25)

#define ISI_IDR_CRC_ERR (0x1u << 26)

#define ISI_IDR_FR_OVR (0x1u << 27)

/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */

#define ISI_IMR_DIS_DONE (0x1u << 1)

#define ISI_IMR_SRST (0x1u << 2)

#define ISI_IMR_VSYNC (0x1u << 10)

#define ISI_IMR_PXFR_DONE (0x1u << 16)

#define ISI_IMR_CXFR_DONE (0x1u << 17)

#define ISI_IMR_P_OVR (0x1u << 24)

#define ISI_IMR_C_OVR (0x1u << 25)

#define ISI_IMR_CRC_ERR (0x1u << 26)

#define ISI_IMR_FR_OVR (0x1u << 27)

/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */

#define ISI_DMA_CHER_P_CH_EN (0x1u << 0)

#define ISI_DMA_CHER_C_CH_EN (0x1u << 1)

/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */

#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0)

#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1)

/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */

#define ISI_DMA_CHSR_P_CH_S (0x1u << 0)

#define ISI_DMA_CHSR_C_CH_S (0x1u << 1)

/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */

#define ISI_DMA_P_ADDR_P_ADDR_Pos 2

#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos)

#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos)))

/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */

#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0)

#define ISI_DMA_P_CTRL_P_WB (0x1u << 1)

#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2)

#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3)

/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */

#define ISI_DMA_P_DSCR_P_DSCR_Pos 2

#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos)

#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos)))

/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */

#define ISI_DMA_C_ADDR_C_ADDR_Pos 2

#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos)

#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos)))

/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */

#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0)

#define ISI_DMA_C_CTRL_C_WB (0x1u << 1)

#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2)

#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3)

/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */

#define ISI_DMA_C_DSCR_C_DSCR_Pos 2

#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos)

#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos)))

/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */

#define ISI_WPMR_WPEN (0x1u << 0)

#define ISI_WPMR_WPKEY_Pos 8

#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos)

#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos)))

#define   ISI_WPMR_WPKEY_PASSWD (0x495349u << 8)

/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */

#define ISI_WPSR_WPVS (0x1u << 0)

#define ISI_WPSR_WPVSRC_Pos 8

#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos)

/* -------- ISI_VERSION : (ISI Offset: 0xFC) Version Register -------- */

#define ISI_VERSION_VERSION_Pos 0

#define ISI_VERSION_VERSION_Msk (0xfffu << ISI_VERSION_VERSION_Pos)

#define ISI_VERSION_MFN_Pos 16

#define ISI_VERSION_MFN_Msk (0x7u << ISI_VERSION_MFN_Pos)


#endif /* _SAMV71_ISI_COMPONENT_ */

__O
#define __O
Definition: core_cm7.h:286

__IO
#define __IO
Definition: core_cm7.h:287

__I
#define __I
Definition: core_cm7.h:284

Isi
Isi hardware registers.
Definition: component_isi.h:41

Isi::ISI_VERSION
__I uint32_t ISI_VERSION
(Isi Offset: 0xFC) Version Register
Definition: component_isi.h:69