30#ifndef _SAMV71_AES_COMPONENT_
31#define _SAMV71_AES_COMPONENT_
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 __I uint32_t Reserved1[2];
49 __O uint32_t AES_KEYWR[8];
50 __O uint32_t AES_IDATAR[4];
51 __I uint32_t AES_ODATAR[4];
52 __O uint32_t AES_IVR[4];
53 __IO uint32_t AES_AADLENR;
54 __IO uint32_t AES_CLENR;
55 __IO uint32_t AES_GHASHR[4];
56 __I uint32_t AES_TAGR[4];
57 __I uint32_t AES_CTRR;
58 __IO uint32_t AES_GCMHR[4];
59 __I uint32_t Reserved2[20];
64#define AES_CR_START (0x1u << 0)
65#define AES_CR_SWRST (0x1u << 8)
66#define AES_CR_LOADSEED (0x1u << 16)
68#define AES_MR_CIPHER (0x1u << 0)
69#define AES_MR_GTAGEN (0x1u << 1)
70#define AES_MR_DUALBUFF (0x1u << 3)
71#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3)
72#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3)
73#define AES_MR_PROCDLY_Pos 4
74#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos)
75#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)))
76#define AES_MR_SMOD_Pos 8
77#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos)
78#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)))
79#define AES_MR_SMOD_MANUAL_START (0x0u << 8)
80#define AES_MR_SMOD_AUTO_START (0x1u << 8)
81#define AES_MR_SMOD_IDATAR0_START (0x2u << 8)
82#define AES_MR_KEYSIZE_Pos 10
83#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos)
84#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)))
85#define AES_MR_KEYSIZE_AES128 (0x0u << 10)
86#define AES_MR_KEYSIZE_AES192 (0x1u << 10)
87#define AES_MR_KEYSIZE_AES256 (0x2u << 10)
88#define AES_MR_OPMOD_Pos 12
89#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos)
90#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)))
91#define AES_MR_OPMOD_ECB (0x0u << 12)
92#define AES_MR_OPMOD_CBC (0x1u << 12)
93#define AES_MR_OPMOD_OFB (0x2u << 12)
94#define AES_MR_OPMOD_CFB (0x3u << 12)
95#define AES_MR_OPMOD_CTR (0x4u << 12)
96#define AES_MR_OPMOD_GCM (0x5u << 12)
97#define AES_MR_LOD (0x1u << 15)
98#define AES_MR_CFBS_Pos 16
99#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos)
100#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)))
101#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16)
102#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16)
103#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16)
104#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16)
105#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16)
106#define AES_MR_CKEY_Pos 20
107#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos)
108#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)))
109#define AES_MR_CKEY_PASSWD (0xEu << 20)
110#define AES_MR_CMTYP1 (0x1u << 24)
111#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24)
112#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24)
113#define AES_MR_CMTYP2 (0x1u << 25)
114#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25)
115#define AES_MR_CMTYP2_PAUSE (0x1u << 25)
116#define AES_MR_CMTYP3 (0x1u << 26)
117#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26)
118#define AES_MR_CMTYP3_DUMMY (0x1u << 26)
119#define AES_MR_CMTYP4 (0x1u << 27)
120#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27)
121#define AES_MR_CMTYP4_RESTART (0x1u << 27)
122#define AES_MR_CMTYP5 (0x1u << 28)
123#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28)
124#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28)
125#define AES_MR_CMTYP6 (0x1u << 29)
126#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29)
127#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29)
129#define AES_IER_DATRDY (0x1u << 0)
130#define AES_IER_URAD (0x1u << 8)
131#define AES_IER_TAGRDY (0x1u << 16)
133#define AES_IDR_DATRDY (0x1u << 0)
134#define AES_IDR_URAD (0x1u << 8)
135#define AES_IDR_TAGRDY (0x1u << 16)
137#define AES_IMR_DATRDY (0x1u << 0)
138#define AES_IMR_URAD (0x1u << 8)
139#define AES_IMR_TAGRDY (0x1u << 16)
141#define AES_ISR_DATRDY (0x1u << 0)
142#define AES_ISR_URAD (0x1u << 8)
143#define AES_ISR_URAT_Pos 12
144#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos)
145#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12)
146#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12)
147#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12)
148#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12)
149#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12)
150#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12)
151#define AES_ISR_TAGRDY (0x1u << 16)
153#define AES_KEYWR_KEYW_Pos 0
154#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos)
155#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)))
157#define AES_IDATAR_IDATA_Pos 0
158#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos)
159#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)))
161#define AES_ODATAR_ODATA_Pos 0
162#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos)
164#define AES_IVR_IV_Pos 0
165#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos)
166#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)))
168#define AES_AADLENR_AADLEN_Pos 0
169#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos)
170#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)))
172#define AES_CLENR_CLEN_Pos 0
173#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos)
174#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)))
176#define AES_GHASHR_GHASH_Pos 0
177#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos)
178#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)))
180#define AES_TAGR_TAG_Pos 0
181#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos)
183#define AES_CTRR_CTR_Pos 0
184#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos)
186#define AES_GCMHR_H_Pos 0
187#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos)
188#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)))
190#define AES_VERSION_VERSION_Pos 0
191#define AES_VERSION_VERSION_Msk (0xfffu << AES_VERSION_VERSION_Pos)
192#define AES_VERSION_MFN_Pos 16
193#define AES_VERSION_MFN_Msk (0x7u << AES_VERSION_MFN_Pos)
#define __O
Definition: core_cm7.h:286
#define __IO
Definition: core_cm7.h:287
#define __I
Definition: core_cm7.h:284
Aes hardware registers.
Definition: component_aes.h:41
__I uint32_t AES_VERSION
(Aes Offset: 0xFC) Version Register
Definition: component_aes.h:60