doxygen/5.2/sams70_2component_2component__pwm_8h_source.html

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/*                  Atmel Microcontroller Software Support                      */

/*                       SAM Software Package License                           */

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/* Copyright (c) 2015, Atmel Corporation                                        */

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#ifndef _SAMS70_PWM_COMPONENT_

#define _SAMS70_PWM_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __IO uint32_t PWM_CMR;

  __IO uint32_t PWM_CDTY;

  __O  uint32_t PWM_CDTYUPD;

  __IO uint32_t PWM_CPRD;

  __O  uint32_t PWM_CPRDUPD;

  __I  uint32_t PWM_CCNT;

  __IO uint32_t PWM_DT;

  __O  uint32_t PWM_DTUPD;

} PwmCh_num;

#define PWMCH_NUM_NUMBER 4

typedef struct {

  __IO uint32_t  PWM_CLK;

  __O  uint32_t  PWM_ENA;

  __O  uint32_t  PWM_DIS;

  __I  uint32_t  PWM_SR;

  __O  uint32_t  PWM_IER1;

  __O  uint32_t  PWM_IDR1;

  __I  uint32_t  PWM_IMR1;

  __I  uint32_t  PWM_ISR1;

  __IO uint32_t  PWM_SCM;

  __O  uint32_t  PWM_DMAR;

  __IO uint32_t  PWM_SCUC;

  __IO uint32_t  PWM_SCUP;

  __O  uint32_t  PWM_SCUPUPD;

  __O  uint32_t  PWM_IER2;

  __O  uint32_t  PWM_IDR2;

  __I  uint32_t  PWM_IMR2;

  __I  uint32_t  PWM_ISR2;

  __IO uint32_t  PWM_OOV;

  __IO uint32_t  PWM_OS;

  __O  uint32_t  PWM_OSS;

  __O  uint32_t  PWM_OSC;

  __O  uint32_t  PWM_OSSUPD;

  __O  uint32_t  PWM_OSCUPD;

  __IO uint32_t  PWM_FMR;

  __I  uint32_t  PWM_FSR;

  __O  uint32_t  PWM_FCR;

  __IO uint32_t  PWM_FPV1;

  __IO uint32_t  PWM_FPE;

  __I  uint32_t  Reserved1[3];

  __IO uint32_t  PWM_ELMR[2];

  __I  uint32_t  Reserved2[7];

  __IO uint32_t  PWM_SSPR;

  __O  uint32_t  PWM_SSPUP;

  __I  uint32_t  Reserved3[2];

  __IO uint32_t  PWM_SMMR;

  __I  uint32_t  Reserved4[3];

  __IO uint32_t  PWM_FPV2;

  __I  uint32_t  Reserved5[8];

  __O  uint32_t  PWM_WPCR;

  __I  uint32_t  PWM_WPSR;

  __I  uint32_t  Reserved6[17];

  __IO uint32_t  PWM_CMPV0;

  __O  uint32_t  PWM_CMPVUPD0;

  __IO uint32_t  PWM_CMPM0;

  __O  uint32_t  PWM_CMPMUPD0;

  __IO uint32_t  PWM_CMPV1;

  __O  uint32_t  PWM_CMPVUPD1;

  __IO uint32_t  PWM_CMPM1;

  __O  uint32_t  PWM_CMPMUPD1;

  __IO uint32_t  PWM_CMPV2;

  __O  uint32_t  PWM_CMPVUPD2;

  __IO uint32_t  PWM_CMPM2;

  __O  uint32_t  PWM_CMPMUPD2;

  __IO uint32_t  PWM_CMPV3;

  __O  uint32_t  PWM_CMPVUPD3;

  __IO uint32_t  PWM_CMPM3;

  __O  uint32_t  PWM_CMPMUPD3;

  __IO uint32_t  PWM_CMPV4;

  __O  uint32_t  PWM_CMPVUPD4;

  __IO uint32_t  PWM_CMPM4;

  __O  uint32_t  PWM_CMPMUPD4;

  __IO uint32_t  PWM_CMPV5;

  __O  uint32_t  PWM_CMPVUPD5;

  __IO uint32_t  PWM_CMPM5;

  __O  uint32_t  PWM_CMPMUPD5;

  __IO uint32_t  PWM_CMPV6;

  __O  uint32_t  PWM_CMPVUPD6;

  __IO uint32_t  PWM_CMPM6;

  __O  uint32_t  PWM_CMPMUPD6;

  __IO uint32_t  PWM_CMPV7;

  __O  uint32_t  PWM_CMPVUPD7;

  __IO uint32_t  PWM_CMPM7;

  __O  uint32_t  PWM_CMPMUPD7;

  __I  uint32_t  Reserved7[20];

       PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER];

  __I  uint32_t  Reserved8[96];

  __O  uint32_t  PWM_CMUPD0;

  __I  uint32_t  Reserved9[7];

  __O  uint32_t  PWM_CMUPD1;

  __I  uint32_t  Reserved10[2];

  __IO uint32_t  PWM_ETRG1;

  __IO uint32_t  PWM_LEBR1;

  __I  uint32_t  Reserved11[3];

  __O  uint32_t  PWM_CMUPD2;

  __I  uint32_t  Reserved12[2];

  __IO uint32_t  PWM_ETRG2;

  __IO uint32_t  PWM_LEBR2;

  __I  uint32_t  Reserved13[3];

  __O  uint32_t  PWM_CMUPD3;

} Pwm;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */

#define PWM_CLK_DIVA_Pos 0

#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos)

#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))

#define   PWM_CLK_DIVA_CLKA_POFF (0x0u << 0)

#define   PWM_CLK_DIVA_PREA (0x1u << 0)

#define PWM_CLK_PREA_Pos 8

#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos)

#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))

#define   PWM_CLK_PREA_CLK (0x0u << 8)

#define   PWM_CLK_PREA_CLK_DIV2 (0x1u << 8)

#define   PWM_CLK_PREA_CLK_DIV4 (0x2u << 8)

#define   PWM_CLK_PREA_CLK_DIV8 (0x3u << 8)

#define   PWM_CLK_PREA_CLK_DIV16 (0x4u << 8)

#define   PWM_CLK_PREA_CLK_DIV32 (0x5u << 8)

#define   PWM_CLK_PREA_CLK_DIV64 (0x6u << 8)

#define   PWM_CLK_PREA_CLK_DIV128 (0x7u << 8)

#define   PWM_CLK_PREA_CLK_DIV256 (0x8u << 8)

#define   PWM_CLK_PREA_CLK_DIV512 (0x9u << 8)

#define   PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8)

#define PWM_CLK_DIVB_Pos 16

#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos)

#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))

#define   PWM_CLK_DIVB_CLKB_POFF (0x0u << 16)

#define   PWM_CLK_DIVB_PREB (0x1u << 16)

#define PWM_CLK_PREB_Pos 24

#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos)

#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))

#define   PWM_CLK_PREB_CLK (0x0u << 24)

#define   PWM_CLK_PREB_CLK_DIV2 (0x1u << 24)

#define   PWM_CLK_PREB_CLK_DIV4 (0x2u << 24)

#define   PWM_CLK_PREB_CLK_DIV8 (0x3u << 24)

#define   PWM_CLK_PREB_CLK_DIV16 (0x4u << 24)

#define   PWM_CLK_PREB_CLK_DIV32 (0x5u << 24)

#define   PWM_CLK_PREB_CLK_DIV64 (0x6u << 24)

#define   PWM_CLK_PREB_CLK_DIV128 (0x7u << 24)

#define   PWM_CLK_PREB_CLK_DIV256 (0x8u << 24)

#define   PWM_CLK_PREB_CLK_DIV512 (0x9u << 24)

#define   PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24)

/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */

#define PWM_ENA_CHID0 (0x1u << 0)

#define PWM_ENA_CHID1 (0x1u << 1)

#define PWM_ENA_CHID2 (0x1u << 2)

#define PWM_ENA_CHID3 (0x1u << 3)

/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */

#define PWM_DIS_CHID0 (0x1u << 0)

#define PWM_DIS_CHID1 (0x1u << 1)

#define PWM_DIS_CHID2 (0x1u << 2)

#define PWM_DIS_CHID3 (0x1u << 3)

/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */

#define PWM_SR_CHID0 (0x1u << 0)

#define PWM_SR_CHID1 (0x1u << 1)

#define PWM_SR_CHID2 (0x1u << 2)

#define PWM_SR_CHID3 (0x1u << 3)

/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */

#define PWM_IER1_CHID0 (0x1u << 0)

#define PWM_IER1_CHID1 (0x1u << 1)

#define PWM_IER1_CHID2 (0x1u << 2)

#define PWM_IER1_CHID3 (0x1u << 3)

#define PWM_IER1_FCHID0 (0x1u << 16)

#define PWM_IER1_FCHID1 (0x1u << 17)

#define PWM_IER1_FCHID2 (0x1u << 18)

#define PWM_IER1_FCHID3 (0x1u << 19)

/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */

#define PWM_IDR1_CHID0 (0x1u << 0)

#define PWM_IDR1_CHID1 (0x1u << 1)

#define PWM_IDR1_CHID2 (0x1u << 2)

#define PWM_IDR1_CHID3 (0x1u << 3)

#define PWM_IDR1_FCHID0 (0x1u << 16)

#define PWM_IDR1_FCHID1 (0x1u << 17)

#define PWM_IDR1_FCHID2 (0x1u << 18)

#define PWM_IDR1_FCHID3 (0x1u << 19)

/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */

#define PWM_IMR1_CHID0 (0x1u << 0)

#define PWM_IMR1_CHID1 (0x1u << 1)

#define PWM_IMR1_CHID2 (0x1u << 2)

#define PWM_IMR1_CHID3 (0x1u << 3)

#define PWM_IMR1_FCHID0 (0x1u << 16)

#define PWM_IMR1_FCHID1 (0x1u << 17)

#define PWM_IMR1_FCHID2 (0x1u << 18)

#define PWM_IMR1_FCHID3 (0x1u << 19)

/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */

#define PWM_ISR1_CHID0 (0x1u << 0)

#define PWM_ISR1_CHID1 (0x1u << 1)

#define PWM_ISR1_CHID2 (0x1u << 2)

#define PWM_ISR1_CHID3 (0x1u << 3)

#define PWM_ISR1_FCHID0 (0x1u << 16)

#define PWM_ISR1_FCHID1 (0x1u << 17)

#define PWM_ISR1_FCHID2 (0x1u << 18)

#define PWM_ISR1_FCHID3 (0x1u << 19)

/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */

#define PWM_SCM_SYNC0 (0x1u << 0)

#define PWM_SCM_SYNC1 (0x1u << 1)

#define PWM_SCM_SYNC2 (0x1u << 2)

#define PWM_SCM_SYNC3 (0x1u << 3)

#define PWM_SCM_UPDM_Pos 16

#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos)

#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos)))

#define   PWM_SCM_UPDM_MODE0 (0x0u << 16)

#define   PWM_SCM_UPDM_MODE1 (0x1u << 16)

#define   PWM_SCM_UPDM_MODE2 (0x2u << 16)

#define PWM_SCM_PTRM (0x1u << 20)

#define PWM_SCM_PTRCS_Pos 21

#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos)

#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))

/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */

#define PWM_DMAR_DMADUTY_Pos 0

#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos)

#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)))

/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */

#define PWM_SCUC_UPDULOCK (0x1u << 0)

/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */

#define PWM_SCUP_UPR_Pos 0

#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos)

#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))

#define PWM_SCUP_UPRCNT_Pos 4

#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos)

#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))

/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */

#define PWM_SCUPUPD_UPRUPD_Pos 0

#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos)

#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))

/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */

#define PWM_IER2_WRDY (0x1u << 0)

#define PWM_IER2_UNRE (0x1u << 3)

#define PWM_IER2_CMPM0 (0x1u << 8)

#define PWM_IER2_CMPM1 (0x1u << 9)

#define PWM_IER2_CMPM2 (0x1u << 10)

#define PWM_IER2_CMPM3 (0x1u << 11)

#define PWM_IER2_CMPM4 (0x1u << 12)

#define PWM_IER2_CMPM5 (0x1u << 13)

#define PWM_IER2_CMPM6 (0x1u << 14)

#define PWM_IER2_CMPM7 (0x1u << 15)

#define PWM_IER2_CMPU0 (0x1u << 16)

#define PWM_IER2_CMPU1 (0x1u << 17)

#define PWM_IER2_CMPU2 (0x1u << 18)

#define PWM_IER2_CMPU3 (0x1u << 19)

#define PWM_IER2_CMPU4 (0x1u << 20)

#define PWM_IER2_CMPU5 (0x1u << 21)

#define PWM_IER2_CMPU6 (0x1u << 22)

#define PWM_IER2_CMPU7 (0x1u << 23)

/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */

#define PWM_IDR2_WRDY (0x1u << 0)

#define PWM_IDR2_UNRE (0x1u << 3)

#define PWM_IDR2_CMPM0 (0x1u << 8)

#define PWM_IDR2_CMPM1 (0x1u << 9)

#define PWM_IDR2_CMPM2 (0x1u << 10)

#define PWM_IDR2_CMPM3 (0x1u << 11)

#define PWM_IDR2_CMPM4 (0x1u << 12)

#define PWM_IDR2_CMPM5 (0x1u << 13)

#define PWM_IDR2_CMPM6 (0x1u << 14)

#define PWM_IDR2_CMPM7 (0x1u << 15)

#define PWM_IDR2_CMPU0 (0x1u << 16)

#define PWM_IDR2_CMPU1 (0x1u << 17)

#define PWM_IDR2_CMPU2 (0x1u << 18)

#define PWM_IDR2_CMPU3 (0x1u << 19)

#define PWM_IDR2_CMPU4 (0x1u << 20)

#define PWM_IDR2_CMPU5 (0x1u << 21)

#define PWM_IDR2_CMPU6 (0x1u << 22)

#define PWM_IDR2_CMPU7 (0x1u << 23)

/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */

#define PWM_IMR2_WRDY (0x1u << 0)

#define PWM_IMR2_UNRE (0x1u << 3)

#define PWM_IMR2_CMPM0 (0x1u << 8)

#define PWM_IMR2_CMPM1 (0x1u << 9)

#define PWM_IMR2_CMPM2 (0x1u << 10)

#define PWM_IMR2_CMPM3 (0x1u << 11)

#define PWM_IMR2_CMPM4 (0x1u << 12)

#define PWM_IMR2_CMPM5 (0x1u << 13)

#define PWM_IMR2_CMPM6 (0x1u << 14)

#define PWM_IMR2_CMPM7 (0x1u << 15)

#define PWM_IMR2_CMPU0 (0x1u << 16)

#define PWM_IMR2_CMPU1 (0x1u << 17)

#define PWM_IMR2_CMPU2 (0x1u << 18)

#define PWM_IMR2_CMPU3 (0x1u << 19)

#define PWM_IMR2_CMPU4 (0x1u << 20)

#define PWM_IMR2_CMPU5 (0x1u << 21)

#define PWM_IMR2_CMPU6 (0x1u << 22)

#define PWM_IMR2_CMPU7 (0x1u << 23)

/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */

#define PWM_ISR2_WRDY (0x1u << 0)

#define PWM_ISR2_UNRE (0x1u << 3)

#define PWM_ISR2_CMPM0 (0x1u << 8)

#define PWM_ISR2_CMPM1 (0x1u << 9)

#define PWM_ISR2_CMPM2 (0x1u << 10)

#define PWM_ISR2_CMPM3 (0x1u << 11)

#define PWM_ISR2_CMPM4 (0x1u << 12)

#define PWM_ISR2_CMPM5 (0x1u << 13)

#define PWM_ISR2_CMPM6 (0x1u << 14)

#define PWM_ISR2_CMPM7 (0x1u << 15)

#define PWM_ISR2_CMPU0 (0x1u << 16)

#define PWM_ISR2_CMPU1 (0x1u << 17)

#define PWM_ISR2_CMPU2 (0x1u << 18)

#define PWM_ISR2_CMPU3 (0x1u << 19)

#define PWM_ISR2_CMPU4 (0x1u << 20)

#define PWM_ISR2_CMPU5 (0x1u << 21)

#define PWM_ISR2_CMPU6 (0x1u << 22)

#define PWM_ISR2_CMPU7 (0x1u << 23)

/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */

#define PWM_OOV_OOVH0 (0x1u << 0)

#define PWM_OOV_OOVH1 (0x1u << 1)

#define PWM_OOV_OOVH2 (0x1u << 2)

#define PWM_OOV_OOVH3 (0x1u << 3)

#define PWM_OOV_OOVL0 (0x1u << 16)

#define PWM_OOV_OOVL1 (0x1u << 17)

#define PWM_OOV_OOVL2 (0x1u << 18)

#define PWM_OOV_OOVL3 (0x1u << 19)

/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */

#define PWM_OS_OSH0 (0x1u << 0)

#define PWM_OS_OSH1 (0x1u << 1)

#define PWM_OS_OSH2 (0x1u << 2)

#define PWM_OS_OSH3 (0x1u << 3)

#define PWM_OS_OSL0 (0x1u << 16)

#define PWM_OS_OSL1 (0x1u << 17)

#define PWM_OS_OSL2 (0x1u << 18)

#define PWM_OS_OSL3 (0x1u << 19)

/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */

#define PWM_OSS_OSSH0 (0x1u << 0)

#define PWM_OSS_OSSH1 (0x1u << 1)

#define PWM_OSS_OSSH2 (0x1u << 2)

#define PWM_OSS_OSSH3 (0x1u << 3)

#define PWM_OSS_OSSL0 (0x1u << 16)

#define PWM_OSS_OSSL1 (0x1u << 17)

#define PWM_OSS_OSSL2 (0x1u << 18)

#define PWM_OSS_OSSL3 (0x1u << 19)

/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */

#define PWM_OSC_OSCH0 (0x1u << 0)

#define PWM_OSC_OSCH1 (0x1u << 1)

#define PWM_OSC_OSCH2 (0x1u << 2)

#define PWM_OSC_OSCH3 (0x1u << 3)

#define PWM_OSC_OSCL0 (0x1u << 16)

#define PWM_OSC_OSCL1 (0x1u << 17)

#define PWM_OSC_OSCL2 (0x1u << 18)

#define PWM_OSC_OSCL3 (0x1u << 19)

/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */

#define PWM_OSSUPD_OSSUPH0 (0x1u << 0)

#define PWM_OSSUPD_OSSUPH1 (0x1u << 1)

#define PWM_OSSUPD_OSSUPH2 (0x1u << 2)

#define PWM_OSSUPD_OSSUPH3 (0x1u << 3)

#define PWM_OSSUPD_OSSUPL0 (0x1u << 16)

#define PWM_OSSUPD_OSSUPL1 (0x1u << 17)

#define PWM_OSSUPD_OSSUPL2 (0x1u << 18)

#define PWM_OSSUPD_OSSUPL3 (0x1u << 19)

/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */

#define PWM_OSCUPD_OSCUPH0 (0x1u << 0)

#define PWM_OSCUPD_OSCUPH1 (0x1u << 1)

#define PWM_OSCUPD_OSCUPH2 (0x1u << 2)

#define PWM_OSCUPD_OSCUPH3 (0x1u << 3)

#define PWM_OSCUPD_OSCUPL0 (0x1u << 16)

#define PWM_OSCUPD_OSCUPL1 (0x1u << 17)

#define PWM_OSCUPD_OSCUPL2 (0x1u << 18)

#define PWM_OSCUPD_OSCUPL3 (0x1u << 19)

/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */

#define PWM_FMR_FPOL_Pos 0

#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos)

#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))

#define PWM_FMR_FMOD_Pos 8

#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos)

#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))

#define PWM_FMR_FFIL_Pos 16

#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos)

#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))

/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */

#define PWM_FSR_FIV_Pos 0

#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos)

#define PWM_FSR_FS_Pos 8

#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos)

/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */

#define PWM_FCR_FCLR_Pos 0

#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos)

#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))

/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */

#define PWM_FPV1_FPVH0 (0x1u << 0)

#define PWM_FPV1_FPVH1 (0x1u << 1)

#define PWM_FPV1_FPVH2 (0x1u << 2)

#define PWM_FPV1_FPVH3 (0x1u << 3)

#define PWM_FPV1_FPVL0 (0x1u << 16)

#define PWM_FPV1_FPVL1 (0x1u << 17)

#define PWM_FPV1_FPVL2 (0x1u << 18)

#define PWM_FPV1_FPVL3 (0x1u << 19)

/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */

#define PWM_FPE_FPE0_Pos 0

#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos)

#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))

#define PWM_FPE_FPE1_Pos 8

#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos)

#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))

#define PWM_FPE_FPE2_Pos 16

#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos)

#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))

#define PWM_FPE_FPE3_Pos 24

#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos)

#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))

/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */

#define PWM_ELMR_CSEL0 (0x1u << 0)

#define PWM_ELMR_CSEL1 (0x1u << 1)

#define PWM_ELMR_CSEL2 (0x1u << 2)

#define PWM_ELMR_CSEL3 (0x1u << 3)

#define PWM_ELMR_CSEL4 (0x1u << 4)

#define PWM_ELMR_CSEL5 (0x1u << 5)

#define PWM_ELMR_CSEL6 (0x1u << 6)

#define PWM_ELMR_CSEL7 (0x1u << 7)

/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */

#define PWM_SSPR_SPRD_Pos 0

#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos)

#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)))

#define PWM_SSPR_SPRDM (0x1u << 24)

/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */

#define PWM_SSPUP_SPRDUP_Pos 0

#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos)

#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)))

/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */

#define PWM_SMMR_GCEN0 (0x1u << 0)

#define PWM_SMMR_GCEN1 (0x1u << 1)

#define PWM_SMMR_DOWN0 (0x1u << 16)

#define PWM_SMMR_DOWN1 (0x1u << 17)

/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */

#define PWM_FPV2_FPZH0 (0x1u << 0)

#define PWM_FPV2_FPZH1 (0x1u << 1)

#define PWM_FPV2_FPZH2 (0x1u << 2)

#define PWM_FPV2_FPZH3 (0x1u << 3)

#define PWM_FPV2_FPZL0 (0x1u << 16)

#define PWM_FPV2_FPZL1 (0x1u << 17)

#define PWM_FPV2_FPZL2 (0x1u << 18)

#define PWM_FPV2_FPZL3 (0x1u << 19)

/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */

#define PWM_WPCR_WPCMD_Pos 0

#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos)

#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))

#define   PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0)

#define   PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0)

#define   PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0)

#define PWM_WPCR_WPRG0 (0x1u << 2)

#define PWM_WPCR_WPRG1 (0x1u << 3)

#define PWM_WPCR_WPRG2 (0x1u << 4)

#define PWM_WPCR_WPRG3 (0x1u << 5)

#define PWM_WPCR_WPRG4 (0x1u << 6)

#define PWM_WPCR_WPRG5 (0x1u << 7)

#define PWM_WPCR_WPKEY_Pos 8

#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos)

#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))

#define   PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8)

/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */

#define PWM_WPSR_WPSWS0 (0x1u << 0)

#define PWM_WPSR_WPSWS1 (0x1u << 1)

#define PWM_WPSR_WPSWS2 (0x1u << 2)

#define PWM_WPSR_WPSWS3 (0x1u << 3)

#define PWM_WPSR_WPSWS4 (0x1u << 4)

#define PWM_WPSR_WPSWS5 (0x1u << 5)

#define PWM_WPSR_WPVS (0x1u << 7)

#define PWM_WPSR_WPHWS0 (0x1u << 8)

#define PWM_WPSR_WPHWS1 (0x1u << 9)

#define PWM_WPSR_WPHWS2 (0x1u << 10)

#define PWM_WPSR_WPHWS3 (0x1u << 11)

#define PWM_WPSR_WPHWS4 (0x1u << 12)

#define PWM_WPSR_WPHWS5 (0x1u << 13)

#define PWM_WPSR_WPVSRC_Pos 16

#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos)

/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */

#define PWM_CMPV_CV_Pos 0

#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos)

#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))

#define PWM_CMPV_CVM (0x1u << 24)

/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */

#define PWM_CMPVUPD_CVUPD_Pos 0

#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos)

#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))

#define PWM_CMPVUPD_CVMUPD (0x1u << 24)

/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */

#define PWM_CMPM_CEN (0x1u << 0)

#define PWM_CMPM_CTR_Pos 4

#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos)

#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))

#define PWM_CMPM_CPR_Pos 8

#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos)

#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))

#define PWM_CMPM_CPRCNT_Pos 12

#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos)

#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))

#define PWM_CMPM_CUPR_Pos 16

#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos)

#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))

#define PWM_CMPM_CUPRCNT_Pos 20

#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos)

#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))

/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */

#define PWM_CMPMUPD_CENUPD (0x1u << 0)

#define PWM_CMPMUPD_CTRUPD_Pos 4

#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos)

#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))

#define PWM_CMPMUPD_CPRUPD_Pos 8

#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos)

#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))

#define PWM_CMPMUPD_CUPRUPD_Pos 16

#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos)

#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))

/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */

#define PWM_CMR_CPRE_Pos 0

#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos)

#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos)))

#define   PWM_CMR_CPRE_MCK (0x0u << 0)

#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0)

#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0)

#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0)

#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0)

#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0)

#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0)

#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0)

#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0)

#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0)

#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0)

#define   PWM_CMR_CPRE_CLKA (0xBu << 0)

#define   PWM_CMR_CPRE_CLKB (0xCu << 0)

#define PWM_CMR_CALG (0x1u << 8)

#define PWM_CMR_CPOL (0x1u << 9)

#define PWM_CMR_CES (0x1u << 10)

#define PWM_CMR_UPDS (0x1u << 11)

#define PWM_CMR_DPOLI (0x1u << 12)

#define PWM_CMR_TCTS (0x1u << 13)

#define PWM_CMR_DTE (0x1u << 16)

#define PWM_CMR_DTHI (0x1u << 17)

#define PWM_CMR_DTLI (0x1u << 18)

#define PWM_CMR_PPM (0x1u << 19)

/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */

#define PWM_CDTY_CDTY_Pos 0

#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos)

#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))

/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */

#define PWM_CDTYUPD_CDTYUPD_Pos 0

#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos)

#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))

/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */

#define PWM_CPRD_CPRD_Pos 0

#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos)

#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))

/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */

#define PWM_CPRDUPD_CPRDUPD_Pos 0

#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos)

#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))

/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */

#define PWM_CCNT_CNT_Pos 0

#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos)

/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */

#define PWM_DT_DTH_Pos 0

#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos)

#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))

#define PWM_DT_DTL_Pos 16

#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos)

#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))

/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */

#define PWM_DTUPD_DTHUPD_Pos 0

#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos)

#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))

#define PWM_DTUPD_DTLUPD_Pos 16

#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos)

#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))

/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */

#define PWM_CMUPD0_CPOLUP (0x1u << 9)

#define PWM_CMUPD0_CPOLINVUP (0x1u << 13)

/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */

#define PWM_CMUPD1_CPOLUP (0x1u << 9)

#define PWM_CMUPD1_CPOLINVUP (0x1u << 13)

/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */

#define PWM_ETRG1_MAXCNT_Pos 0

#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos)

#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)))

#define PWM_ETRG1_TRGMODE_Pos 24

#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos)

#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos)))

#define   PWM_ETRG1_TRGMODE_OFF (0x0u << 24)

#define   PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24)

#define   PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24)

#define   PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24)

#define PWM_ETRG1_TRGEDGE (0x1u << 28)

#define   PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28)

#define   PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28)

#define PWM_ETRG1_TRGFILT (0x1u << 29)

#define PWM_ETRG1_TRGSRC (0x1u << 30)

#define PWM_ETRG1_RFEN (0x1u << 31)

/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */

#define PWM_LEBR1_LEBDELAY_Pos 0

#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos)

#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)))

#define PWM_LEBR1_PWMLFEN (0x1u << 16)

#define PWM_LEBR1_PWMLREN (0x1u << 17)

#define PWM_LEBR1_PWMHFEN (0x1u << 18)

#define PWM_LEBR1_PWMHREN (0x1u << 19)

/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */

#define PWM_CMUPD2_CPOLUP (0x1u << 9)

#define PWM_CMUPD2_CPOLINVUP (0x1u << 13)

/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */

#define PWM_ETRG2_MAXCNT_Pos 0

#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos)

#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)))

#define PWM_ETRG2_TRGMODE_Pos 24

#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos)

#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos)))

#define   PWM_ETRG2_TRGMODE_OFF (0x0u << 24)

#define   PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24)

#define   PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24)

#define   PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24)

#define PWM_ETRG2_TRGEDGE (0x1u << 28)

#define   PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28)

#define   PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28)

#define PWM_ETRG2_TRGFILT (0x1u << 29)

#define PWM_ETRG2_TRGSRC (0x1u << 30)

#define PWM_ETRG2_RFEN (0x1u << 31)

/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */

#define PWM_LEBR2_LEBDELAY_Pos 0

#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos)

#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)))

#define PWM_LEBR2_PWMLFEN (0x1u << 16)

#define PWM_LEBR2_PWMLREN (0x1u << 17)

#define PWM_LEBR2_PWMHFEN (0x1u << 18)

#define PWM_LEBR2_PWMHREN (0x1u << 19)

/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */

#define PWM_CMUPD3_CPOLUP (0x1u << 9)

#define PWM_CMUPD3_CPOLINVUP (0x1u << 13)


#endif /* _SAMS70_PWM_COMPONENT_ */

__O
#define __O
Definition: core_cm7.h:286

__IO
#define __IO
Definition: core_cm7.h:287

__I
#define __I
Definition: core_cm7.h:284

PwmCh_num
PwmCh_num hardware registers.
Definition: component_pwm.h:41

Pwm
Definition: component_pwm.h:61

Pwm::PWM_CMPM6
__IO uint32_t PWM_CMPM6
(Pwm Offset: 0x198) PWM Comparison 6 Mode Register
Definition: component_pwm.h:121

Pwm::PWM_CMPMUPD1
__O uint32_t PWM_CMPMUPD1
(Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register
Definition: component_pwm.h:102

Pwm::PWM_CMPV0
__IO uint32_t PWM_CMPV0
(Pwm Offset: 0x130) PWM Comparison 0 Value Register
Definition: component_pwm.h:95

Pwm::PWM_CMPM7
__IO uint32_t PWM_CMPM7
(Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register
Definition: component_pwm.h:125

Pwm::PWM_CMPV1
__IO uint32_t PWM_CMPV1
(Pwm Offset: 0x140) PWM Comparison 1 Value Register
Definition: component_pwm.h:99

Pwm::PWM_CMPMUPD0
__O uint32_t PWM_CMPMUPD0
(Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register
Definition: component_pwm.h:98

Pwm::PWM_CMPMUPD7
__O uint32_t PWM_CMPMUPD7
(Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register
Definition: component_pwm.h:126

Pwm::PWM_CMPV4
__IO uint32_t PWM_CMPV4
(Pwm Offset: 0x170) PWM Comparison 4 Value Register
Definition: component_pwm.h:111

Pwm::PWM_CMPM1
__IO uint32_t PWM_CMPM1
(Pwm Offset: 0x148) PWM Comparison 1 Mode Register
Definition: component_pwm.h:101

Pwm::PWM_CMPV7
__IO uint32_t PWM_CMPV7
(Pwm Offset: 0x1A0) PWM Comparison 7 Value Register
Definition: component_pwm.h:123

Pwm::PWM_CMPMUPD3
__O uint32_t PWM_CMPMUPD3
(Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register
Definition: component_pwm.h:110

Pwm::PWM_CMPV2
__IO uint32_t PWM_CMPV2
(Pwm Offset: 0x150) PWM Comparison 2 Value Register
Definition: component_pwm.h:103

Pwm::PWM_CMPVUPD6
__O uint32_t PWM_CMPVUPD6
(Pwm Offset: 0x194) PWM Comparison 6 Value Update Register
Definition: component_pwm.h:120

Pwm::PWM_CMPMUPD6
__O uint32_t PWM_CMPMUPD6
(Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register
Definition: component_pwm.h:122

Pwm::PWM_CMPM0
__IO uint32_t PWM_CMPM0
(Pwm Offset: 0x138) PWM Comparison 0 Mode Register
Definition: component_pwm.h:97

Pwm::PWM_CMPM3
__IO uint32_t PWM_CMPM3
(Pwm Offset: 0x168) PWM Comparison 3 Mode Register
Definition: component_pwm.h:109

Pwm::PWM_CMPVUPD1
__O uint32_t PWM_CMPVUPD1
(Pwm Offset: 0x144) PWM Comparison 1 Value Update Register
Definition: component_pwm.h:100

Pwm::PWM_CMPVUPD3
__O uint32_t PWM_CMPVUPD3
(Pwm Offset: 0x164) PWM Comparison 3 Value Update Register
Definition: component_pwm.h:108

Pwm::PWM_CMPMUPD4
__O uint32_t PWM_CMPMUPD4
(Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register
Definition: component_pwm.h:114

Pwm::PWM_CMPV5
__IO uint32_t PWM_CMPV5
(Pwm Offset: 0x180) PWM Comparison 5 Value Register
Definition: component_pwm.h:115

Pwm::PWM_CMPVUPD4
__O uint32_t PWM_CMPVUPD4
(Pwm Offset: 0x174) PWM Comparison 4 Value Update Register
Definition: component_pwm.h:112

Pwm::PWM_CMPVUPD0
__O uint32_t PWM_CMPVUPD0
(Pwm Offset: 0x134) PWM Comparison 0 Value Update Register
Definition: component_pwm.h:96

Pwm::PWM_CMPMUPD2
__O uint32_t PWM_CMPMUPD2
(Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register
Definition: component_pwm.h:106

Pwm::PWM_CMPVUPD7
__O uint32_t PWM_CMPVUPD7
(Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register
Definition: component_pwm.h:124

Pwm::PWM_CMPM5
__IO uint32_t PWM_CMPM5
(Pwm Offset: 0x188) PWM Comparison 5 Mode Register
Definition: component_pwm.h:117

Pwm::PWM_CMPV6
__IO uint32_t PWM_CMPV6
(Pwm Offset: 0x190) PWM Comparison 6 Value Register
Definition: component_pwm.h:119

Pwm::PWM_CMPM4
__IO uint32_t PWM_CMPM4
(Pwm Offset: 0x178) PWM Comparison 4 Mode Register
Definition: component_pwm.h:113

Pwm::PWM_CMPVUPD2
__O uint32_t PWM_CMPVUPD2
(Pwm Offset: 0x154) PWM Comparison 2 Value Update Register
Definition: component_pwm.h:104

Pwm::PWM_CMPV3
__IO uint32_t PWM_CMPV3
(Pwm Offset: 0x160) PWM Comparison 3 Value Register
Definition: component_pwm.h:107

Pwm::PWM_CMPMUPD5
__O uint32_t PWM_CMPMUPD5
(Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register
Definition: component_pwm.h:118

Pwm::PWM_CMPVUPD5
__O uint32_t PWM_CMPVUPD5
(Pwm Offset: 0x184) PWM Comparison 5 Value Update Register
Definition: component_pwm.h:116

Pwm::PWM_CMPM2
__IO uint32_t PWM_CMPM2
(Pwm Offset: 0x158) PWM Comparison 2 Mode Register
Definition: component_pwm.h:105