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component_dacc.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70_DACC_COMPONENT_
31#define _SAMS70_DACC_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __O uint32_t DACC_CR;
43 __IO uint32_t DACC_MR;
44 __IO uint32_t DACC_TRIGR;
45 __I uint32_t Reserved1[1];
46 __O uint32_t DACC_CHER;
47 __O uint32_t DACC_CHDR;
48 __I uint32_t DACC_CHSR;
49 __O uint32_t DACC_CDR[2];
50 __O uint32_t DACC_IER;
51 __O uint32_t DACC_IDR;
52 __I uint32_t DACC_IMR;
53 __I uint32_t DACC_ISR;
54 __I uint32_t Reserved2[24];
55 __IO uint32_t DACC_ACR;
56 __I uint32_t Reserved3[19];
57 __IO uint32_t DACC_WPMR;
58 __I uint32_t DACC_WPSR;
59} Dacc;
60#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
61/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
62#define DACC_CR_SWRST (0x1u << 0)
63/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
64#define DACC_MR_MAXS0 (0x1u << 0)
65#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0)
66#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0)
67#define DACC_MR_MAXS1 (0x1u << 1)
68#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1)
69#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1)
70#define DACC_MR_WORD (0x1u << 4)
71#define DACC_MR_WORD_DISABLED (0x0u << 4)
72#define DACC_MR_WORD_ENABLED (0x1u << 4)
73#define DACC_MR_ZERO (0x1u << 5)
74#define DACC_MR_DIFF (0x1u << 23)
75#define DACC_MR_DIFF_DISABLED (0x0u << 23)
76#define DACC_MR_DIFF_ENABLED (0x1u << 23)
77#define DACC_MR_PRESCALER_Pos 24
78#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos)
79#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)))
80/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */
81#define DACC_TRIGR_TRGEN0 (0x1u << 0)
82#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0)
83#define DACC_TRIGR_TRGEN0_EN (0x1u << 0)
84#define DACC_TRIGR_TRGEN1 (0x1u << 1)
85#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1)
86#define DACC_TRIGR_TRGEN1_EN (0x1u << 1)
87#define DACC_TRIGR_TRGSEL0_Pos 4
88#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos)
89#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos)))
90#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4)
91#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4)
92#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4)
93#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4)
94#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4)
95#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4)
96#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4)
97#define DACC_TRIGR_TRGSEL1_Pos 8
98#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos)
99#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos)))
100#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8)
101#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8)
102#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8)
103#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8)
104#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8)
105#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8)
106#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8)
107#define DACC_TRIGR_OSR0_Pos 16
108#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos)
109#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos)))
110#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16)
111#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16)
112#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16)
113#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16)
114#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16)
115#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16)
116#define DACC_TRIGR_OSR1_Pos 20
117#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos)
118#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos)))
119#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20)
120#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20)
121#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20)
122#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20)
123#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20)
124#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20)
125/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
126#define DACC_CHER_CH0 (0x1u << 0)
127#define DACC_CHER_CH1 (0x1u << 1)
128/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
129#define DACC_CHDR_CH0 (0x1u << 0)
130#define DACC_CHDR_CH1 (0x1u << 1)
131/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
132#define DACC_CHSR_CH0 (0x1u << 0)
133#define DACC_CHSR_CH1 (0x1u << 1)
134#define DACC_CHSR_DACRDY0 (0x1u << 8)
135#define DACC_CHSR_DACRDY1 (0x1u << 9)
136/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */
137#define DACC_CDR_DATA0_Pos 0
138#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos)
139#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)))
140#define DACC_CDR_DATA1_Pos 16
141#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos)
142#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)))
143/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
144#define DACC_IER_TXRDY0 (0x1u << 0)
145#define DACC_IER_TXRDY1 (0x1u << 1)
146#define DACC_IER_EOC0 (0x1u << 4)
147#define DACC_IER_EOC1 (0x1u << 5)
148/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
149#define DACC_IDR_TXRDY0 (0x1u << 0)
150#define DACC_IDR_TXRDY1 (0x1u << 1)
151#define DACC_IDR_EOC0 (0x1u << 4)
152#define DACC_IDR_EOC1 (0x1u << 5)
153/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
154#define DACC_IMR_TXRDY0 (0x1u << 0)
155#define DACC_IMR_TXRDY1 (0x1u << 1)
156#define DACC_IMR_EOC0 (0x1u << 4)
157#define DACC_IMR_EOC1 (0x1u << 5)
158/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
159#define DACC_ISR_TXRDY0 (0x1u << 0)
160#define DACC_ISR_TXRDY1 (0x1u << 1)
161#define DACC_ISR_EOC0 (0x1u << 4)
162#define DACC_ISR_EOC1 (0x1u << 5)
163/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
164#define DACC_ACR_IBCTLCH0_Pos 0
165#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos)
166#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
167#define DACC_ACR_IBCTLCH1_Pos 2
168#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos)
169#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
170/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode Register -------- */
171#define DACC_WPMR_WPEN (0x1u << 0)
172#define DACC_WPMR_WPKEY_Pos 8
173#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos)
174#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
175#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8)
176/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status Register -------- */
177#define DACC_WPSR_WPVS (0x1u << 0)
178#define DACC_WPSR_WPVSRC_Pos 8
179#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos)
182
183
184#endif /* _SAMS70_DACC_COMPONENT_ */
__O
#define __O
Definition: core_cm7.h:286
__IO
#define __IO
Definition: core_cm7.h:287
__I
#define __I
Definition: core_cm7.h:284
Dacc
Dacc hardware registers.
Definition: component_dacc.h:41
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