doxygen/5.2/same70_2component_2component__xdmac_8h_source.html

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/*                  Atmel Microcontroller Software Support                      */

/*                       SAM Software Package License                           */

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/* Copyright (c) 2015, Atmel Corporation                                        */

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#ifndef _SAME70_XDMAC_COMPONENT_

#define _SAME70_XDMAC_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __O  uint32_t XDMAC_CIE;

  __O  uint32_t XDMAC_CID;

  __O  uint32_t XDMAC_CIM;

  __I  uint32_t XDMAC_CIS;

  __IO uint32_t XDMAC_CSA;

  __IO uint32_t XDMAC_CDA;

  __IO uint32_t XDMAC_CNDA;

  __IO uint32_t XDMAC_CNDC;

  __IO uint32_t XDMAC_CUBC;

  __IO uint32_t XDMAC_CBC;

  __IO uint32_t XDMAC_CC;

  __IO uint32_t XDMAC_CDS_MSP;

  __IO uint32_t XDMAC_CSUS;

  __IO uint32_t XDMAC_CDUS;

  __I  uint32_t Reserved1[2];

} XdmacChid;

#define XDMACCHID_NUMBER 24

typedef struct {

  __IO uint32_t  XDMAC_GTYPE;

  __I  uint32_t  XDMAC_GCFG;

  __IO uint32_t  XDMAC_GWAC;

  __O  uint32_t  XDMAC_GIE;

  __O  uint32_t  XDMAC_GID;

  __I  uint32_t  XDMAC_GIM;

  __I  uint32_t  XDMAC_GIS;

  __O  uint32_t  XDMAC_GE;

  __O  uint32_t  XDMAC_GD;

  __I  uint32_t  XDMAC_GS;

  __IO uint32_t  XDMAC_GRS;

  __IO uint32_t  XDMAC_GWS;

  __O  uint32_t  XDMAC_GRWS;

  __O  uint32_t  XDMAC_GRWR;

  __O  uint32_t  XDMAC_GSWR;

  __I  uint32_t  XDMAC_GSWS;

  __O  uint32_t  XDMAC_GSWF;

  __I  uint32_t  Reserved1[3];

       XdmacChid XDMAC_CHID[XDMACCHID_NUMBER];

} Xdmac;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */

#define XDMAC_GTYPE_NB_CH_Pos 0

#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos)

#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)))

#define XDMAC_GTYPE_FIFO_SZ_Pos 5

#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos)

#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)))

#define XDMAC_GTYPE_NB_REQ_Pos 16

#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos)

#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)))

/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */

#define XDMAC_GCFG_CGDISREG (0x1u << 0)

#define XDMAC_GCFG_CGDISPIPE (0x1u << 1)

#define XDMAC_GCFG_CGDISFIFO (0x1u << 2)

#define XDMAC_GCFG_CGDISIF (0x1u << 3)

#define XDMAC_GCFG_BXKBEN (0x1u << 8)

/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */

#define XDMAC_GWAC_PW0_Pos 0

#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos)

#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)))

#define XDMAC_GWAC_PW1_Pos 4

#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos)

#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)))

#define XDMAC_GWAC_PW2_Pos 8

#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos)

#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)))

#define XDMAC_GWAC_PW3_Pos 12

#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos)

#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)))

/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */

#define XDMAC_GIE_IE0 (0x1u << 0)

#define XDMAC_GIE_IE1 (0x1u << 1)

#define XDMAC_GIE_IE2 (0x1u << 2)

#define XDMAC_GIE_IE3 (0x1u << 3)

#define XDMAC_GIE_IE4 (0x1u << 4)

#define XDMAC_GIE_IE5 (0x1u << 5)

#define XDMAC_GIE_IE6 (0x1u << 6)

#define XDMAC_GIE_IE7 (0x1u << 7)

#define XDMAC_GIE_IE8 (0x1u << 8)

#define XDMAC_GIE_IE9 (0x1u << 9)

#define XDMAC_GIE_IE10 (0x1u << 10)

#define XDMAC_GIE_IE11 (0x1u << 11)

#define XDMAC_GIE_IE12 (0x1u << 12)

#define XDMAC_GIE_IE13 (0x1u << 13)

#define XDMAC_GIE_IE14 (0x1u << 14)

#define XDMAC_GIE_IE15 (0x1u << 15)

#define XDMAC_GIE_IE16 (0x1u << 16)

#define XDMAC_GIE_IE17 (0x1u << 17)

#define XDMAC_GIE_IE18 (0x1u << 18)

#define XDMAC_GIE_IE19 (0x1u << 19)

#define XDMAC_GIE_IE20 (0x1u << 20)

#define XDMAC_GIE_IE21 (0x1u << 21)

#define XDMAC_GIE_IE22 (0x1u << 22)

#define XDMAC_GIE_IE23 (0x1u << 23)

/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */

#define XDMAC_GID_ID0 (0x1u << 0)

#define XDMAC_GID_ID1 (0x1u << 1)

#define XDMAC_GID_ID2 (0x1u << 2)

#define XDMAC_GID_ID3 (0x1u << 3)

#define XDMAC_GID_ID4 (0x1u << 4)

#define XDMAC_GID_ID5 (0x1u << 5)

#define XDMAC_GID_ID6 (0x1u << 6)

#define XDMAC_GID_ID7 (0x1u << 7)

#define XDMAC_GID_ID8 (0x1u << 8)

#define XDMAC_GID_ID9 (0x1u << 9)

#define XDMAC_GID_ID10 (0x1u << 10)

#define XDMAC_GID_ID11 (0x1u << 11)

#define XDMAC_GID_ID12 (0x1u << 12)

#define XDMAC_GID_ID13 (0x1u << 13)

#define XDMAC_GID_ID14 (0x1u << 14)

#define XDMAC_GID_ID15 (0x1u << 15)

#define XDMAC_GID_ID16 (0x1u << 16)

#define XDMAC_GID_ID17 (0x1u << 17)

#define XDMAC_GID_ID18 (0x1u << 18)

#define XDMAC_GID_ID19 (0x1u << 19)

#define XDMAC_GID_ID20 (0x1u << 20)

#define XDMAC_GID_ID21 (0x1u << 21)

#define XDMAC_GID_ID22 (0x1u << 22)

#define XDMAC_GID_ID23 (0x1u << 23)

/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */

#define XDMAC_GIM_IM0 (0x1u << 0)

#define XDMAC_GIM_IM1 (0x1u << 1)

#define XDMAC_GIM_IM2 (0x1u << 2)

#define XDMAC_GIM_IM3 (0x1u << 3)

#define XDMAC_GIM_IM4 (0x1u << 4)

#define XDMAC_GIM_IM5 (0x1u << 5)

#define XDMAC_GIM_IM6 (0x1u << 6)

#define XDMAC_GIM_IM7 (0x1u << 7)

#define XDMAC_GIM_IM8 (0x1u << 8)

#define XDMAC_GIM_IM9 (0x1u << 9)

#define XDMAC_GIM_IM10 (0x1u << 10)

#define XDMAC_GIM_IM11 (0x1u << 11)

#define XDMAC_GIM_IM12 (0x1u << 12)

#define XDMAC_GIM_IM13 (0x1u << 13)

#define XDMAC_GIM_IM14 (0x1u << 14)

#define XDMAC_GIM_IM15 (0x1u << 15)

#define XDMAC_GIM_IM16 (0x1u << 16)

#define XDMAC_GIM_IM17 (0x1u << 17)

#define XDMAC_GIM_IM18 (0x1u << 18)

#define XDMAC_GIM_IM19 (0x1u << 19)

#define XDMAC_GIM_IM20 (0x1u << 20)

#define XDMAC_GIM_IM21 (0x1u << 21)

#define XDMAC_GIM_IM22 (0x1u << 22)

#define XDMAC_GIM_IM23 (0x1u << 23)

/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */

#define XDMAC_GIS_IS0 (0x1u << 0)

#define XDMAC_GIS_IS1 (0x1u << 1)

#define XDMAC_GIS_IS2 (0x1u << 2)

#define XDMAC_GIS_IS3 (0x1u << 3)

#define XDMAC_GIS_IS4 (0x1u << 4)

#define XDMAC_GIS_IS5 (0x1u << 5)

#define XDMAC_GIS_IS6 (0x1u << 6)

#define XDMAC_GIS_IS7 (0x1u << 7)

#define XDMAC_GIS_IS8 (0x1u << 8)

#define XDMAC_GIS_IS9 (0x1u << 9)

#define XDMAC_GIS_IS10 (0x1u << 10)

#define XDMAC_GIS_IS11 (0x1u << 11)

#define XDMAC_GIS_IS12 (0x1u << 12)

#define XDMAC_GIS_IS13 (0x1u << 13)

#define XDMAC_GIS_IS14 (0x1u << 14)

#define XDMAC_GIS_IS15 (0x1u << 15)

#define XDMAC_GIS_IS16 (0x1u << 16)

#define XDMAC_GIS_IS17 (0x1u << 17)

#define XDMAC_GIS_IS18 (0x1u << 18)

#define XDMAC_GIS_IS19 (0x1u << 19)

#define XDMAC_GIS_IS20 (0x1u << 20)

#define XDMAC_GIS_IS21 (0x1u << 21)

#define XDMAC_GIS_IS22 (0x1u << 22)

#define XDMAC_GIS_IS23 (0x1u << 23)

/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */

#define XDMAC_GE_EN0 (0x1u << 0)

#define XDMAC_GE_EN1 (0x1u << 1)

#define XDMAC_GE_EN2 (0x1u << 2)

#define XDMAC_GE_EN3 (0x1u << 3)

#define XDMAC_GE_EN4 (0x1u << 4)

#define XDMAC_GE_EN5 (0x1u << 5)

#define XDMAC_GE_EN6 (0x1u << 6)

#define XDMAC_GE_EN7 (0x1u << 7)

#define XDMAC_GE_EN8 (0x1u << 8)

#define XDMAC_GE_EN9 (0x1u << 9)

#define XDMAC_GE_EN10 (0x1u << 10)

#define XDMAC_GE_EN11 (0x1u << 11)

#define XDMAC_GE_EN12 (0x1u << 12)

#define XDMAC_GE_EN13 (0x1u << 13)

#define XDMAC_GE_EN14 (0x1u << 14)

#define XDMAC_GE_EN15 (0x1u << 15)

#define XDMAC_GE_EN16 (0x1u << 16)

#define XDMAC_GE_EN17 (0x1u << 17)

#define XDMAC_GE_EN18 (0x1u << 18)

#define XDMAC_GE_EN19 (0x1u << 19)

#define XDMAC_GE_EN20 (0x1u << 20)

#define XDMAC_GE_EN21 (0x1u << 21)

#define XDMAC_GE_EN22 (0x1u << 22)

#define XDMAC_GE_EN23 (0x1u << 23)

/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */

#define XDMAC_GD_DI0 (0x1u << 0)

#define XDMAC_GD_DI1 (0x1u << 1)

#define XDMAC_GD_DI2 (0x1u << 2)

#define XDMAC_GD_DI3 (0x1u << 3)

#define XDMAC_GD_DI4 (0x1u << 4)

#define XDMAC_GD_DI5 (0x1u << 5)

#define XDMAC_GD_DI6 (0x1u << 6)

#define XDMAC_GD_DI7 (0x1u << 7)

#define XDMAC_GD_DI8 (0x1u << 8)

#define XDMAC_GD_DI9 (0x1u << 9)

#define XDMAC_GD_DI10 (0x1u << 10)

#define XDMAC_GD_DI11 (0x1u << 11)

#define XDMAC_GD_DI12 (0x1u << 12)

#define XDMAC_GD_DI13 (0x1u << 13)

#define XDMAC_GD_DI14 (0x1u << 14)

#define XDMAC_GD_DI15 (0x1u << 15)

#define XDMAC_GD_DI16 (0x1u << 16)

#define XDMAC_GD_DI17 (0x1u << 17)

#define XDMAC_GD_DI18 (0x1u << 18)

#define XDMAC_GD_DI19 (0x1u << 19)

#define XDMAC_GD_DI20 (0x1u << 20)

#define XDMAC_GD_DI21 (0x1u << 21)

#define XDMAC_GD_DI22 (0x1u << 22)

#define XDMAC_GD_DI23 (0x1u << 23)

/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */

#define XDMAC_GS_ST0 (0x1u << 0)

#define XDMAC_GS_ST1 (0x1u << 1)

#define XDMAC_GS_ST2 (0x1u << 2)

#define XDMAC_GS_ST3 (0x1u << 3)

#define XDMAC_GS_ST4 (0x1u << 4)

#define XDMAC_GS_ST5 (0x1u << 5)

#define XDMAC_GS_ST6 (0x1u << 6)

#define XDMAC_GS_ST7 (0x1u << 7)

#define XDMAC_GS_ST8 (0x1u << 8)

#define XDMAC_GS_ST9 (0x1u << 9)

#define XDMAC_GS_ST10 (0x1u << 10)

#define XDMAC_GS_ST11 (0x1u << 11)

#define XDMAC_GS_ST12 (0x1u << 12)

#define XDMAC_GS_ST13 (0x1u << 13)

#define XDMAC_GS_ST14 (0x1u << 14)

#define XDMAC_GS_ST15 (0x1u << 15)

#define XDMAC_GS_ST16 (0x1u << 16)

#define XDMAC_GS_ST17 (0x1u << 17)

#define XDMAC_GS_ST18 (0x1u << 18)

#define XDMAC_GS_ST19 (0x1u << 19)

#define XDMAC_GS_ST20 (0x1u << 20)

#define XDMAC_GS_ST21 (0x1u << 21)

#define XDMAC_GS_ST22 (0x1u << 22)

#define XDMAC_GS_ST23 (0x1u << 23)

/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */

#define XDMAC_GRS_RS0 (0x1u << 0)

#define XDMAC_GRS_RS1 (0x1u << 1)

#define XDMAC_GRS_RS2 (0x1u << 2)

#define XDMAC_GRS_RS3 (0x1u << 3)

#define XDMAC_GRS_RS4 (0x1u << 4)

#define XDMAC_GRS_RS5 (0x1u << 5)

#define XDMAC_GRS_RS6 (0x1u << 6)

#define XDMAC_GRS_RS7 (0x1u << 7)

#define XDMAC_GRS_RS8 (0x1u << 8)

#define XDMAC_GRS_RS9 (0x1u << 9)

#define XDMAC_GRS_RS10 (0x1u << 10)

#define XDMAC_GRS_RS11 (0x1u << 11)

#define XDMAC_GRS_RS12 (0x1u << 12)

#define XDMAC_GRS_RS13 (0x1u << 13)

#define XDMAC_GRS_RS14 (0x1u << 14)

#define XDMAC_GRS_RS15 (0x1u << 15)

#define XDMAC_GRS_RS16 (0x1u << 16)

#define XDMAC_GRS_RS17 (0x1u << 17)

#define XDMAC_GRS_RS18 (0x1u << 18)

#define XDMAC_GRS_RS19 (0x1u << 19)

#define XDMAC_GRS_RS20 (0x1u << 20)

#define XDMAC_GRS_RS21 (0x1u << 21)

#define XDMAC_GRS_RS22 (0x1u << 22)

#define XDMAC_GRS_RS23 (0x1u << 23)

/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */

#define XDMAC_GWS_WS0 (0x1u << 0)

#define XDMAC_GWS_WS1 (0x1u << 1)

#define XDMAC_GWS_WS2 (0x1u << 2)

#define XDMAC_GWS_WS3 (0x1u << 3)

#define XDMAC_GWS_WS4 (0x1u << 4)

#define XDMAC_GWS_WS5 (0x1u << 5)

#define XDMAC_GWS_WS6 (0x1u << 6)

#define XDMAC_GWS_WS7 (0x1u << 7)

#define XDMAC_GWS_WS8 (0x1u << 8)

#define XDMAC_GWS_WS9 (0x1u << 9)

#define XDMAC_GWS_WS10 (0x1u << 10)

#define XDMAC_GWS_WS11 (0x1u << 11)

#define XDMAC_GWS_WS12 (0x1u << 12)

#define XDMAC_GWS_WS13 (0x1u << 13)

#define XDMAC_GWS_WS14 (0x1u << 14)

#define XDMAC_GWS_WS15 (0x1u << 15)

#define XDMAC_GWS_WS16 (0x1u << 16)

#define XDMAC_GWS_WS17 (0x1u << 17)

#define XDMAC_GWS_WS18 (0x1u << 18)

#define XDMAC_GWS_WS19 (0x1u << 19)

#define XDMAC_GWS_WS20 (0x1u << 20)

#define XDMAC_GWS_WS21 (0x1u << 21)

#define XDMAC_GWS_WS22 (0x1u << 22)

#define XDMAC_GWS_WS23 (0x1u << 23)

/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */

#define XDMAC_GRWS_RWS0 (0x1u << 0)

#define XDMAC_GRWS_RWS1 (0x1u << 1)

#define XDMAC_GRWS_RWS2 (0x1u << 2)

#define XDMAC_GRWS_RWS3 (0x1u << 3)

#define XDMAC_GRWS_RWS4 (0x1u << 4)

#define XDMAC_GRWS_RWS5 (0x1u << 5)

#define XDMAC_GRWS_RWS6 (0x1u << 6)

#define XDMAC_GRWS_RWS7 (0x1u << 7)

#define XDMAC_GRWS_RWS8 (0x1u << 8)

#define XDMAC_GRWS_RWS9 (0x1u << 9)

#define XDMAC_GRWS_RWS10 (0x1u << 10)

#define XDMAC_GRWS_RWS11 (0x1u << 11)

#define XDMAC_GRWS_RWS12 (0x1u << 12)

#define XDMAC_GRWS_RWS13 (0x1u << 13)

#define XDMAC_GRWS_RWS14 (0x1u << 14)

#define XDMAC_GRWS_RWS15 (0x1u << 15)

#define XDMAC_GRWS_RWS16 (0x1u << 16)

#define XDMAC_GRWS_RWS17 (0x1u << 17)

#define XDMAC_GRWS_RWS18 (0x1u << 18)

#define XDMAC_GRWS_RWS19 (0x1u << 19)

#define XDMAC_GRWS_RWS20 (0x1u << 20)

#define XDMAC_GRWS_RWS21 (0x1u << 21)

#define XDMAC_GRWS_RWS22 (0x1u << 22)

#define XDMAC_GRWS_RWS23 (0x1u << 23)

/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */

#define XDMAC_GRWR_RWR0 (0x1u << 0)

#define XDMAC_GRWR_RWR1 (0x1u << 1)

#define XDMAC_GRWR_RWR2 (0x1u << 2)

#define XDMAC_GRWR_RWR3 (0x1u << 3)

#define XDMAC_GRWR_RWR4 (0x1u << 4)

#define XDMAC_GRWR_RWR5 (0x1u << 5)

#define XDMAC_GRWR_RWR6 (0x1u << 6)

#define XDMAC_GRWR_RWR7 (0x1u << 7)

#define XDMAC_GRWR_RWR8 (0x1u << 8)

#define XDMAC_GRWR_RWR9 (0x1u << 9)

#define XDMAC_GRWR_RWR10 (0x1u << 10)

#define XDMAC_GRWR_RWR11 (0x1u << 11)

#define XDMAC_GRWR_RWR12 (0x1u << 12)

#define XDMAC_GRWR_RWR13 (0x1u << 13)

#define XDMAC_GRWR_RWR14 (0x1u << 14)

#define XDMAC_GRWR_RWR15 (0x1u << 15)

#define XDMAC_GRWR_RWR16 (0x1u << 16)

#define XDMAC_GRWR_RWR17 (0x1u << 17)

#define XDMAC_GRWR_RWR18 (0x1u << 18)

#define XDMAC_GRWR_RWR19 (0x1u << 19)

#define XDMAC_GRWR_RWR20 (0x1u << 20)

#define XDMAC_GRWR_RWR21 (0x1u << 21)

#define XDMAC_GRWR_RWR22 (0x1u << 22)

#define XDMAC_GRWR_RWR23 (0x1u << 23)

/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */

#define XDMAC_GSWR_SWREQ0 (0x1u << 0)

#define XDMAC_GSWR_SWREQ1 (0x1u << 1)

#define XDMAC_GSWR_SWREQ2 (0x1u << 2)

#define XDMAC_GSWR_SWREQ3 (0x1u << 3)

#define XDMAC_GSWR_SWREQ4 (0x1u << 4)

#define XDMAC_GSWR_SWREQ5 (0x1u << 5)

#define XDMAC_GSWR_SWREQ6 (0x1u << 6)

#define XDMAC_GSWR_SWREQ7 (0x1u << 7)

#define XDMAC_GSWR_SWREQ8 (0x1u << 8)

#define XDMAC_GSWR_SWREQ9 (0x1u << 9)

#define XDMAC_GSWR_SWREQ10 (0x1u << 10)

#define XDMAC_GSWR_SWREQ11 (0x1u << 11)

#define XDMAC_GSWR_SWREQ12 (0x1u << 12)

#define XDMAC_GSWR_SWREQ13 (0x1u << 13)

#define XDMAC_GSWR_SWREQ14 (0x1u << 14)

#define XDMAC_GSWR_SWREQ15 (0x1u << 15)

#define XDMAC_GSWR_SWREQ16 (0x1u << 16)

#define XDMAC_GSWR_SWREQ17 (0x1u << 17)

#define XDMAC_GSWR_SWREQ18 (0x1u << 18)

#define XDMAC_GSWR_SWREQ19 (0x1u << 19)

#define XDMAC_GSWR_SWREQ20 (0x1u << 20)

#define XDMAC_GSWR_SWREQ21 (0x1u << 21)

#define XDMAC_GSWR_SWREQ22 (0x1u << 22)

#define XDMAC_GSWR_SWREQ23 (0x1u << 23)

/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */

#define XDMAC_GSWS_SWRS0 (0x1u << 0)

#define XDMAC_GSWS_SWRS1 (0x1u << 1)

#define XDMAC_GSWS_SWRS2 (0x1u << 2)

#define XDMAC_GSWS_SWRS3 (0x1u << 3)

#define XDMAC_GSWS_SWRS4 (0x1u << 4)

#define XDMAC_GSWS_SWRS5 (0x1u << 5)

#define XDMAC_GSWS_SWRS6 (0x1u << 6)

#define XDMAC_GSWS_SWRS7 (0x1u << 7)

#define XDMAC_GSWS_SWRS8 (0x1u << 8)

#define XDMAC_GSWS_SWRS9 (0x1u << 9)

#define XDMAC_GSWS_SWRS10 (0x1u << 10)

#define XDMAC_GSWS_SWRS11 (0x1u << 11)

#define XDMAC_GSWS_SWRS12 (0x1u << 12)

#define XDMAC_GSWS_SWRS13 (0x1u << 13)

#define XDMAC_GSWS_SWRS14 (0x1u << 14)

#define XDMAC_GSWS_SWRS15 (0x1u << 15)

#define XDMAC_GSWS_SWRS16 (0x1u << 16)

#define XDMAC_GSWS_SWRS17 (0x1u << 17)

#define XDMAC_GSWS_SWRS18 (0x1u << 18)

#define XDMAC_GSWS_SWRS19 (0x1u << 19)

#define XDMAC_GSWS_SWRS20 (0x1u << 20)

#define XDMAC_GSWS_SWRS21 (0x1u << 21)

#define XDMAC_GSWS_SWRS22 (0x1u << 22)

#define XDMAC_GSWS_SWRS23 (0x1u << 23)

/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */

#define XDMAC_GSWF_SWF0 (0x1u << 0)

#define XDMAC_GSWF_SWF1 (0x1u << 1)

#define XDMAC_GSWF_SWF2 (0x1u << 2)

#define XDMAC_GSWF_SWF3 (0x1u << 3)

#define XDMAC_GSWF_SWF4 (0x1u << 4)

#define XDMAC_GSWF_SWF5 (0x1u << 5)

#define XDMAC_GSWF_SWF6 (0x1u << 6)

#define XDMAC_GSWF_SWF7 (0x1u << 7)

#define XDMAC_GSWF_SWF8 (0x1u << 8)

#define XDMAC_GSWF_SWF9 (0x1u << 9)

#define XDMAC_GSWF_SWF10 (0x1u << 10)

#define XDMAC_GSWF_SWF11 (0x1u << 11)

#define XDMAC_GSWF_SWF12 (0x1u << 12)

#define XDMAC_GSWF_SWF13 (0x1u << 13)

#define XDMAC_GSWF_SWF14 (0x1u << 14)

#define XDMAC_GSWF_SWF15 (0x1u << 15)

#define XDMAC_GSWF_SWF16 (0x1u << 16)

#define XDMAC_GSWF_SWF17 (0x1u << 17)

#define XDMAC_GSWF_SWF18 (0x1u << 18)

#define XDMAC_GSWF_SWF19 (0x1u << 19)

#define XDMAC_GSWF_SWF20 (0x1u << 20)

#define XDMAC_GSWF_SWF21 (0x1u << 21)

#define XDMAC_GSWF_SWF22 (0x1u << 22)

#define XDMAC_GSWF_SWF23 (0x1u << 23)

/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */

#define XDMAC_CIE_BIE (0x1u << 0)

#define XDMAC_CIE_LIE (0x1u << 1)

#define XDMAC_CIE_DIE (0x1u << 2)

#define XDMAC_CIE_FIE (0x1u << 3)

#define XDMAC_CIE_RBIE (0x1u << 4)

#define XDMAC_CIE_WBIE (0x1u << 5)

#define XDMAC_CIE_ROIE (0x1u << 6)

/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */

#define XDMAC_CID_BID (0x1u << 0)

#define XDMAC_CID_LID (0x1u << 1)

#define XDMAC_CID_DID (0x1u << 2)

#define XDMAC_CID_FID (0x1u << 3)

#define XDMAC_CID_RBEID (0x1u << 4)

#define XDMAC_CID_WBEID (0x1u << 5)

#define XDMAC_CID_ROID (0x1u << 6)

/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */

#define XDMAC_CIM_BIM (0x1u << 0)

#define XDMAC_CIM_LIM (0x1u << 1)

#define XDMAC_CIM_DIM (0x1u << 2)

#define XDMAC_CIM_FIM (0x1u << 3)

#define XDMAC_CIM_RBEIM (0x1u << 4)

#define XDMAC_CIM_WBEIM (0x1u << 5)

#define XDMAC_CIM_ROIM (0x1u << 6)

/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */

#define XDMAC_CIS_BIS (0x1u << 0)

#define XDMAC_CIS_LIS (0x1u << 1)

#define XDMAC_CIS_DIS (0x1u << 2)

#define XDMAC_CIS_FIS (0x1u << 3)

#define XDMAC_CIS_RBEIS (0x1u << 4)

#define XDMAC_CIS_WBEIS (0x1u << 5)

#define XDMAC_CIS_ROIS (0x1u << 6)

/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */

#define XDMAC_CSA_SA_Pos 0

#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos)

#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)))

/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */

#define XDMAC_CDA_DA_Pos 0

#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos)

#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)))

/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */

#define XDMAC_CNDA_NDAIF (0x1u << 0)

#define XDMAC_CNDA_NDA_Pos 2

#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos)

#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos)))

/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */

#define XDMAC_CNDC_NDE (0x1u << 0)

#define   XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0)

#define   XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0)

#define XDMAC_CNDC_NDSUP (0x1u << 1)

#define   XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1)

#define   XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1)

#define XDMAC_CNDC_NDDUP (0x1u << 2)

#define   XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2)

#define   XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2)

#define XDMAC_CNDC_NDVIEW_Pos 3

#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos)

#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos)))

#define   XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3)

#define   XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3)

#define   XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3)

#define   XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3)

/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */

#define XDMAC_CUBC_UBLEN_Pos 0

#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos)

#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)))

/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */

#define XDMAC_CBC_BLEN_Pos 0

#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos)

#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)))

/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */

#define XDMAC_CC_TYPE (0x1u << 0)

#define   XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0)

#define   XDMAC_CC_TYPE_PER_TRAN (0x1u << 0)

#define XDMAC_CC_MBSIZE_Pos 1

#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos)

#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos)))

#define   XDMAC_CC_MBSIZE_SINGLE (0x0u << 1)

#define   XDMAC_CC_MBSIZE_FOUR (0x1u << 1)

#define   XDMAC_CC_MBSIZE_EIGHT (0x2u << 1)

#define   XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1)

#define XDMAC_CC_DSYNC (0x1u << 4)

#define   XDMAC_CC_DSYNC_PER2MEM (0x0u << 4)

#define   XDMAC_CC_DSYNC_MEM2PER (0x1u << 4)

#define XDMAC_CC_SWREQ (0x1u << 6)

#define   XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6)

#define   XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6)

#define XDMAC_CC_MEMSET (0x1u << 7)

#define   XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7)

#define   XDMAC_CC_MEMSET_HW_MODE (0x1u << 7)

#define XDMAC_CC_CSIZE_Pos 8

#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos)

#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos)))

#define   XDMAC_CC_CSIZE_CHK_1 (0x0u << 8)

#define   XDMAC_CC_CSIZE_CHK_2 (0x1u << 8)

#define   XDMAC_CC_CSIZE_CHK_4 (0x2u << 8)

#define   XDMAC_CC_CSIZE_CHK_8 (0x3u << 8)

#define   XDMAC_CC_CSIZE_CHK_16 (0x4u << 8)

#define XDMAC_CC_DWIDTH_Pos 11

#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos)

#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos)))

#define   XDMAC_CC_DWIDTH_BYTE (0x0u << 11)

#define   XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11)

#define   XDMAC_CC_DWIDTH_WORD (0x2u << 11)

#define XDMAC_CC_SIF (0x1u << 13)

#define   XDMAC_CC_SIF_AHB_IF0 (0x0u << 13)

#define   XDMAC_CC_SIF_AHB_IF1 (0x1u << 13)

#define XDMAC_CC_DIF (0x1u << 14)

#define   XDMAC_CC_DIF_AHB_IF0 (0x0u << 14)

#define   XDMAC_CC_DIF_AHB_IF1 (0x1u << 14)

#define XDMAC_CC_SAM_Pos 16

#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos)

#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos)))

#define   XDMAC_CC_SAM_FIXED_AM (0x0u << 16)

#define   XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16)

#define   XDMAC_CC_SAM_UBS_AM (0x2u << 16)

#define   XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16)

#define XDMAC_CC_DAM_Pos 18

#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos)

#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos)))

#define   XDMAC_CC_DAM_FIXED_AM (0x0u << 18)

#define   XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18)

#define   XDMAC_CC_DAM_UBS_AM (0x2u << 18)

#define   XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18)

#define XDMAC_CC_INITD (0x1u << 21)

#define   XDMAC_CC_INITD_TERMINATED (0x0u << 21)

#define   XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21)

#define XDMAC_CC_RDIP (0x1u << 22)

#define   XDMAC_CC_RDIP_DONE (0x0u << 22)

#define   XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22)

#define XDMAC_CC_WRIP (0x1u << 23)

#define   XDMAC_CC_WRIP_DONE (0x0u << 23)

#define   XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23)

#define XDMAC_CC_PERID_Pos 24

#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos)

#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)))

/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */

#define XDMAC_CDS_MSP_SDS_MSP_Pos 0

#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos)

#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)))

#define XDMAC_CDS_MSP_DDS_MSP_Pos 16

#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos)

#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)))

/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */

#define XDMAC_CSUS_SUBS_Pos 0

#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos)

#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)))

/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */

#define XDMAC_CDUS_DUBS_Pos 0

#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos)

#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)))


#endif /* _SAME70_XDMAC_COMPONENT_ */

__O
#define __O
Definition: core_cm7.h:286

__IO
#define __IO
Definition: core_cm7.h:287

__I
#define __I
Definition: core_cm7.h:284

XdmacChid
XdmacChid hardware registers.
Definition: component_xdmac.h:41

XdmacChid::XDMAC_CDS_MSP
__IO uint32_t XDMAC_CDS_MSP
(XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern
Definition: component_xdmac.h:53

XdmacChid::XDMAC_CID
__O uint32_t XDMAC_CID
(XdmacChid Offset: 0x4) Channel Interrupt Disable Register
Definition: component_xdmac.h:43

XdmacChid::XDMAC_CC
__IO uint32_t XDMAC_CC
(XdmacChid Offset: 0x28) Channel Configuration Register
Definition: component_xdmac.h:52

XdmacChid::XDMAC_CIE
__O uint32_t XDMAC_CIE
(XdmacChid Offset: 0x0) Channel Interrupt Enable Register
Definition: component_xdmac.h:42

XdmacChid::XDMAC_CIS
__I uint32_t XDMAC_CIS
(XdmacChid Offset: 0xC) Channel Interrupt Status Register
Definition: component_xdmac.h:45

XdmacChid::XDMAC_CIM
__O uint32_t XDMAC_CIM
(XdmacChid Offset: 0x8) Channel Interrupt Mask Register
Definition: component_xdmac.h:44

XdmacChid::XDMAC_CUBC
__IO uint32_t XDMAC_CUBC
(XdmacChid Offset: 0x20) Channel Microblock Control Register
Definition: component_xdmac.h:50

XdmacChid::XDMAC_CSUS
__IO uint32_t XDMAC_CSUS
(XdmacChid Offset: 0x30) Channel Source Microblock Stride
Definition: component_xdmac.h:54

XdmacChid::XDMAC_CBC
__IO uint32_t XDMAC_CBC
(XdmacChid Offset: 0x24) Channel Block Control Register
Definition: component_xdmac.h:51

XdmacChid::XDMAC_CDUS
__IO uint32_t XDMAC_CDUS
(XdmacChid Offset: 0x34) Channel Destination Microblock Stride
Definition: component_xdmac.h:55

XdmacChid::XDMAC_CNDC
__IO uint32_t XDMAC_CNDC
(XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register
Definition: component_xdmac.h:49

XdmacChid::XDMAC_CDA
__IO uint32_t XDMAC_CDA
(XdmacChid Offset: 0x14) Channel Destination Address Register
Definition: component_xdmac.h:47

XdmacChid::XDMAC_CSA
__IO uint32_t XDMAC_CSA
(XdmacChid Offset: 0x10) Channel Source Address Register
Definition: component_xdmac.h:46

XdmacChid::XDMAC_CNDA
__IO uint32_t XDMAC_CNDA
(XdmacChid Offset: 0x18) Channel Next Descriptor Address Register
Definition: component_xdmac.h:48

Xdmac
Definition: component_xdmac.h:60

Xdmac::XDMAC_GWS
__IO uint32_t XDMAC_GWS
(Xdmac Offset: 0x2C) Global Channel Write Suspend Register
Definition: component_xdmac.h:72

Xdmac::XDMAC_GSWF
__O uint32_t XDMAC_GSWF
(Xdmac Offset: 0x40) Global Channel Software Flush Request Register
Definition: component_xdmac.h:77

Xdmac::XDMAC_GIM
__I uint32_t XDMAC_GIM
(Xdmac Offset: 0x14) Global Interrupt Mask Register
Definition: component_xdmac.h:66

Xdmac::XDMAC_GIE
__O uint32_t XDMAC_GIE
(Xdmac Offset: 0x0C) Global Interrupt Enable Register
Definition: component_xdmac.h:64

Xdmac::XDMAC_GSWS
__I uint32_t XDMAC_GSWS
(Xdmac Offset: 0x3C) Global Channel Software Request Status Register
Definition: component_xdmac.h:76

Xdmac::XDMAC_GD
__O uint32_t XDMAC_GD
(Xdmac Offset: 0x20) Global Channel Disable Register
Definition: component_xdmac.h:69

Xdmac::XDMAC_GRWS
__O uint32_t XDMAC_GRWS
(Xdmac Offset: 0x30) Global Channel Read Write Suspend Register
Definition: component_xdmac.h:73

Xdmac::XDMAC_GID
__O uint32_t XDMAC_GID
(Xdmac Offset: 0x10) Global Interrupt Disable Register
Definition: component_xdmac.h:65

Xdmac::XDMAC_GE
__O uint32_t XDMAC_GE
(Xdmac Offset: 0x1C) Global Channel Enable Register
Definition: component_xdmac.h:68

Xdmac::XDMAC_GTYPE
__IO uint32_t XDMAC_GTYPE
(Xdmac Offset: 0x00) Global Type Register
Definition: component_xdmac.h:61

Xdmac::XDMAC_GSWR
__O uint32_t XDMAC_GSWR
(Xdmac Offset: 0x38) Global Channel Software Request Register
Definition: component_xdmac.h:75

Xdmac::XDMAC_GRWR
__O uint32_t XDMAC_GRWR
(Xdmac Offset: 0x34) Global Channel Read Write Resume Register
Definition: component_xdmac.h:74

Xdmac::XDMAC_GRS
__IO uint32_t XDMAC_GRS
(Xdmac Offset: 0x28) Global Channel Read Suspend Register
Definition: component_xdmac.h:71

Xdmac::XDMAC_GS
__I uint32_t XDMAC_GS
(Xdmac Offset: 0x24) Global Channel Status Register
Definition: component_xdmac.h:70

Xdmac::XDMAC_GCFG
__I uint32_t XDMAC_GCFG
(Xdmac Offset: 0x04) Global Configuration Register
Definition: component_xdmac.h:62

Xdmac::XDMAC_GIS
__I uint32_t XDMAC_GIS
(Xdmac Offset: 0x18) Global Interrupt Status Register
Definition: component_xdmac.h:67

Xdmac::XDMAC_GWAC
__IO uint32_t XDMAC_GWAC
(Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register
Definition: component_xdmac.h:63