doxygen/5.2/same70_2component_2component__usbhs_8h_source.html

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/*                  Atmel Microcontroller Software Support                      */

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/* Copyright (c) 2015, Atmel Corporation                                        */

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#ifndef _SAME70_USBHS_COMPONENT_

#define _SAME70_USBHS_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __IO uint32_t USBHS_DEVDMANXTDSC;

  __IO uint32_t USBHS_DEVDMAADDRESS;

  __IO uint32_t USBHS_DEVDMACONTROL;

  __IO uint32_t USBHS_DEVDMASTATUS;

} UsbhsDevdma;

typedef struct {

  __IO uint32_t USBHS_HSTDMANXTDSC;

  __IO uint32_t USBHS_HSTDMAADDRESS;

  __IO uint32_t USBHS_HSTDMACONTROL;

  __IO uint32_t USBHS_HSTDMASTATUS;

} UsbhsHstdma;

#define USBHSDEVDMA_NUMBER 7

#define USBHSHSTDMA_NUMBER 7

typedef struct {

  __IO uint32_t    USBHS_DEVCTRL;

  __I  uint32_t    USBHS_DEVISR;

  __O  uint32_t    USBHS_DEVICR;

  __O  uint32_t    USBHS_DEVIFR;

  __I  uint32_t    USBHS_DEVIMR;

  __O  uint32_t    USBHS_DEVIDR;

  __O  uint32_t    USBHS_DEVIER;

  __IO uint32_t    USBHS_DEVEPT;

  __I  uint32_t    USBHS_DEVFNUM;

  __I  uint32_t    Reserved1[55];

  __IO uint32_t    USBHS_DEVEPTCFG[10];

  __I  uint32_t    Reserved2[2];

  __I  uint32_t    USBHS_DEVEPTISR[10];

  __I  uint32_t    Reserved3[2];

  __O  uint32_t    USBHS_DEVEPTICR[10];

  __I  uint32_t    Reserved4[2];

  __O  uint32_t    USBHS_DEVEPTIFR[10];

  __I  uint32_t    Reserved5[2];

  __I  uint32_t    USBHS_DEVEPTIMR[10];

  __I  uint32_t    Reserved6[2];

  __O  uint32_t    USBHS_DEVEPTIER[10];

  __I  uint32_t    Reserved7[2];

  __O  uint32_t    USBHS_DEVEPTIDR[10];

  __I  uint32_t    Reserved8[50];

       UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER];

  __I  uint32_t    Reserved9[32];

  __IO uint32_t    USBHS_HSTCTRL;

  __I  uint32_t    USBHS_HSTISR;

  __O  uint32_t    USBHS_HSTICR;

  __O  uint32_t    USBHS_HSTIFR;

  __I  uint32_t    USBHS_HSTIMR;

  __O  uint32_t    USBHS_HSTIDR;

  __O  uint32_t    USBHS_HSTIER;

  __IO uint32_t    USBHS_HSTPIP;

  __IO uint32_t    USBHS_HSTFNUM;

  __IO uint32_t    USBHS_HSTADDR1;

  __IO uint32_t    USBHS_HSTADDR2;

  __IO uint32_t    USBHS_HSTADDR3;

  __I  uint32_t    Reserved10[52];

  __IO uint32_t    USBHS_HSTPIPCFG[10];

  __I  uint32_t    Reserved11[2];

  __I  uint32_t    USBHS_HSTPIPISR[10];

  __I  uint32_t    Reserved12[2];

  __O  uint32_t    USBHS_HSTPIPICR[10];

  __I  uint32_t    Reserved13[2];

  __O  uint32_t    USBHS_HSTPIPIFR[10];

  __I  uint32_t    Reserved14[2];

  __I  uint32_t    USBHS_HSTPIPIMR[10];

  __I  uint32_t    Reserved15[2];

  __O  uint32_t    USBHS_HSTPIPIER[10];

  __I  uint32_t    Reserved16[2];

  __O  uint32_t    USBHS_HSTPIPIDR[10];

  __I  uint32_t    Reserved17[2];

  __IO uint32_t    USBHS_HSTPIPINRQ[10];

  __I  uint32_t    Reserved18[2];

  __IO uint32_t    USBHS_HSTPIPERR[10];

  __I  uint32_t    Reserved19[26];

       UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER];

  __I  uint32_t    Reserved20[32];

  __IO uint32_t    USBHS_CTRL;

  __I  uint32_t    USBHS_SR;

  __O  uint32_t    USBHS_SCR;

  __O  uint32_t    USBHS_SFR;

} Usbhs;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */

#define USBHS_DEVCTRL_UADD_Pos 0

#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos)

#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)))

#define USBHS_DEVCTRL_ADDEN (0x1u << 7)

#define USBHS_DEVCTRL_DETACH (0x1u << 8)

#define USBHS_DEVCTRL_RMWKUP (0x1u << 9)

#define USBHS_DEVCTRL_SPDCONF_Pos 10

#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos)

#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)))

#define   USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10)

#define   USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10)

#define   USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10)

#define   USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10)

#define USBHS_DEVCTRL_LS (0x1u << 12)

#define USBHS_DEVCTRL_TSTJ (0x1u << 13)

#define USBHS_DEVCTRL_TSTK (0x1u << 14)

#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15)

#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16)

/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */

#define USBHS_DEVISR_SUSP (0x1u << 0)

#define USBHS_DEVISR_MSOF (0x1u << 1)

#define USBHS_DEVISR_SOF (0x1u << 2)

#define USBHS_DEVISR_EORST (0x1u << 3)

#define USBHS_DEVISR_WAKEUP (0x1u << 4)

#define USBHS_DEVISR_EORSM (0x1u << 5)

#define USBHS_DEVISR_UPRSM (0x1u << 6)

#define USBHS_DEVISR_PEP_0 (0x1u << 12)

#define USBHS_DEVISR_PEP_1 (0x1u << 13)

#define USBHS_DEVISR_PEP_2 (0x1u << 14)

#define USBHS_DEVISR_PEP_3 (0x1u << 15)

#define USBHS_DEVISR_PEP_4 (0x1u << 16)

#define USBHS_DEVISR_PEP_5 (0x1u << 17)

#define USBHS_DEVISR_PEP_6 (0x1u << 18)

#define USBHS_DEVISR_PEP_7 (0x1u << 19)

#define USBHS_DEVISR_PEP_8 (0x1u << 20)

#define USBHS_DEVISR_PEP_9 (0x1u << 21)

#define USBHS_DEVISR_PEP_10 (0x1u << 22)

#define USBHS_DEVISR_PEP_11 (0x1u << 23)

#define USBHS_DEVISR_DMA_1 (0x1u << 25)

#define USBHS_DEVISR_DMA_2 (0x1u << 26)

#define USBHS_DEVISR_DMA_3 (0x1u << 27)

#define USBHS_DEVISR_DMA_4 (0x1u << 28)

#define USBHS_DEVISR_DMA_5 (0x1u << 29)

#define USBHS_DEVISR_DMA_6 (0x1u << 30)

#define USBHS_DEVISR_DMA_7 (0x1u << 31)

/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */

#define USBHS_DEVICR_SUSPC (0x1u << 0)

#define USBHS_DEVICR_MSOFC (0x1u << 1)

#define USBHS_DEVICR_SOFC (0x1u << 2)

#define USBHS_DEVICR_EORSTC (0x1u << 3)

#define USBHS_DEVICR_WAKEUPC (0x1u << 4)

#define USBHS_DEVICR_EORSMC (0x1u << 5)

#define USBHS_DEVICR_UPRSMC (0x1u << 6)

/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */

#define USBHS_DEVIFR_SUSPS (0x1u << 0)

#define USBHS_DEVIFR_MSOFS (0x1u << 1)

#define USBHS_DEVIFR_SOFS (0x1u << 2)

#define USBHS_DEVIFR_EORSTS (0x1u << 3)

#define USBHS_DEVIFR_WAKEUPS (0x1u << 4)

#define USBHS_DEVIFR_EORSMS (0x1u << 5)

#define USBHS_DEVIFR_UPRSMS (0x1u << 6)

#define USBHS_DEVIFR_DMA_1 (0x1u << 25)

#define USBHS_DEVIFR_DMA_2 (0x1u << 26)

#define USBHS_DEVIFR_DMA_3 (0x1u << 27)

#define USBHS_DEVIFR_DMA_4 (0x1u << 28)

#define USBHS_DEVIFR_DMA_5 (0x1u << 29)

#define USBHS_DEVIFR_DMA_6 (0x1u << 30)

#define USBHS_DEVIFR_DMA_7 (0x1u << 31)

/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */

#define USBHS_DEVIMR_SUSPE (0x1u << 0)

#define USBHS_DEVIMR_MSOFE (0x1u << 1)

#define USBHS_DEVIMR_SOFE (0x1u << 2)

#define USBHS_DEVIMR_EORSTE (0x1u << 3)

#define USBHS_DEVIMR_WAKEUPE (0x1u << 4)

#define USBHS_DEVIMR_EORSME (0x1u << 5)

#define USBHS_DEVIMR_UPRSME (0x1u << 6)

#define USBHS_DEVIMR_PEP_0 (0x1u << 12)

#define USBHS_DEVIMR_PEP_1 (0x1u << 13)

#define USBHS_DEVIMR_PEP_2 (0x1u << 14)

#define USBHS_DEVIMR_PEP_3 (0x1u << 15)

#define USBHS_DEVIMR_PEP_4 (0x1u << 16)

#define USBHS_DEVIMR_PEP_5 (0x1u << 17)

#define USBHS_DEVIMR_PEP_6 (0x1u << 18)

#define USBHS_DEVIMR_PEP_7 (0x1u << 19)

#define USBHS_DEVIMR_PEP_8 (0x1u << 20)

#define USBHS_DEVIMR_PEP_9 (0x1u << 21)

#define USBHS_DEVIMR_PEP_10 (0x1u << 22)

#define USBHS_DEVIMR_PEP_11 (0x1u << 23)

#define USBHS_DEVIMR_DMA_1 (0x1u << 25)

#define USBHS_DEVIMR_DMA_2 (0x1u << 26)

#define USBHS_DEVIMR_DMA_3 (0x1u << 27)

#define USBHS_DEVIMR_DMA_4 (0x1u << 28)

#define USBHS_DEVIMR_DMA_5 (0x1u << 29)

#define USBHS_DEVIMR_DMA_6 (0x1u << 30)

#define USBHS_DEVIMR_DMA_7 (0x1u << 31)

/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */

#define USBHS_DEVIDR_SUSPEC (0x1u << 0)

#define USBHS_DEVIDR_MSOFEC (0x1u << 1)

#define USBHS_DEVIDR_SOFEC (0x1u << 2)

#define USBHS_DEVIDR_EORSTEC (0x1u << 3)

#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4)

#define USBHS_DEVIDR_EORSMEC (0x1u << 5)

#define USBHS_DEVIDR_UPRSMEC (0x1u << 6)

#define USBHS_DEVIDR_PEP_0 (0x1u << 12)

#define USBHS_DEVIDR_PEP_1 (0x1u << 13)

#define USBHS_DEVIDR_PEP_2 (0x1u << 14)

#define USBHS_DEVIDR_PEP_3 (0x1u << 15)

#define USBHS_DEVIDR_PEP_4 (0x1u << 16)

#define USBHS_DEVIDR_PEP_5 (0x1u << 17)

#define USBHS_DEVIDR_PEP_6 (0x1u << 18)

#define USBHS_DEVIDR_PEP_7 (0x1u << 19)

#define USBHS_DEVIDR_PEP_8 (0x1u << 20)

#define USBHS_DEVIDR_PEP_9 (0x1u << 21)

#define USBHS_DEVIDR_PEP_10 (0x1u << 22)

#define USBHS_DEVIDR_PEP_11 (0x1u << 23)

#define USBHS_DEVIDR_DMA_1 (0x1u << 25)

#define USBHS_DEVIDR_DMA_2 (0x1u << 26)

#define USBHS_DEVIDR_DMA_3 (0x1u << 27)

#define USBHS_DEVIDR_DMA_4 (0x1u << 28)

#define USBHS_DEVIDR_DMA_5 (0x1u << 29)

#define USBHS_DEVIDR_DMA_6 (0x1u << 30)

#define USBHS_DEVIDR_DMA_7 (0x1u << 31)

/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */

#define USBHS_DEVIER_SUSPES (0x1u << 0)

#define USBHS_DEVIER_MSOFES (0x1u << 1)

#define USBHS_DEVIER_SOFES (0x1u << 2)

#define USBHS_DEVIER_EORSTES (0x1u << 3)

#define USBHS_DEVIER_WAKEUPES (0x1u << 4)

#define USBHS_DEVIER_EORSMES (0x1u << 5)

#define USBHS_DEVIER_UPRSMES (0x1u << 6)

#define USBHS_DEVIER_PEP_0 (0x1u << 12)

#define USBHS_DEVIER_PEP_1 (0x1u << 13)

#define USBHS_DEVIER_PEP_2 (0x1u << 14)

#define USBHS_DEVIER_PEP_3 (0x1u << 15)

#define USBHS_DEVIER_PEP_4 (0x1u << 16)

#define USBHS_DEVIER_PEP_5 (0x1u << 17)

#define USBHS_DEVIER_PEP_6 (0x1u << 18)

#define USBHS_DEVIER_PEP_7 (0x1u << 19)

#define USBHS_DEVIER_PEP_8 (0x1u << 20)

#define USBHS_DEVIER_PEP_9 (0x1u << 21)

#define USBHS_DEVIER_PEP_10 (0x1u << 22)

#define USBHS_DEVIER_PEP_11 (0x1u << 23)

#define USBHS_DEVIER_DMA_1 (0x1u << 25)

#define USBHS_DEVIER_DMA_2 (0x1u << 26)

#define USBHS_DEVIER_DMA_3 (0x1u << 27)

#define USBHS_DEVIER_DMA_4 (0x1u << 28)

#define USBHS_DEVIER_DMA_5 (0x1u << 29)

#define USBHS_DEVIER_DMA_6 (0x1u << 30)

#define USBHS_DEVIER_DMA_7 (0x1u << 31)

/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */

#define USBHS_DEVEPT_EPEN0 (0x1u << 0)

#define USBHS_DEVEPT_EPEN1 (0x1u << 1)

#define USBHS_DEVEPT_EPEN2 (0x1u << 2)

#define USBHS_DEVEPT_EPEN3 (0x1u << 3)

#define USBHS_DEVEPT_EPEN4 (0x1u << 4)

#define USBHS_DEVEPT_EPEN5 (0x1u << 5)

#define USBHS_DEVEPT_EPEN6 (0x1u << 6)

#define USBHS_DEVEPT_EPEN7 (0x1u << 7)

#define USBHS_DEVEPT_EPEN8 (0x1u << 8)

#define USBHS_DEVEPT_EPRST0 (0x1u << 16)

#define USBHS_DEVEPT_EPRST1 (0x1u << 17)

#define USBHS_DEVEPT_EPRST2 (0x1u << 18)

#define USBHS_DEVEPT_EPRST3 (0x1u << 19)

#define USBHS_DEVEPT_EPRST4 (0x1u << 20)

#define USBHS_DEVEPT_EPRST5 (0x1u << 21)

#define USBHS_DEVEPT_EPRST6 (0x1u << 22)

#define USBHS_DEVEPT_EPRST7 (0x1u << 23)

#define USBHS_DEVEPT_EPRST8 (0x1u << 24)

/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */

#define USBHS_DEVFNUM_MFNUM_Pos 0

#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos)

#define USBHS_DEVFNUM_FNUM_Pos 3

#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos)

#define USBHS_DEVFNUM_FNCERR (0x1u << 15)

/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */

#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1)

#define USBHS_DEVEPTCFG_EPBK_Pos 2

#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos)

#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)))

#define   USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2)

#define   USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2)

#define   USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2)

#define USBHS_DEVEPTCFG_EPSIZE_Pos 4

#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos)

#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)))

#define   USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4)

#define   USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4)

#define   USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4)

#define   USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4)

#define   USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4)

#define   USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4)

#define   USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4)

#define   USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4)

#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8)

#define   USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8)

#define   USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8)

#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9)

#define USBHS_DEVEPTCFG_EPTYPE_Pos 11

#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos)

#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)))

#define   USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11)

#define   USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11)

#define   USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11)

#define   USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11)

#define USBHS_DEVEPTCFG_NBTRANS_Pos 13

#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos)

#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)))

#define   USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13)

#define   USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13)

#define   USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13)

#define   USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13)

/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */

#define USBHS_DEVEPTISR_TXINI (0x1u << 0)

#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1)

#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2)

#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3)

#define USBHS_DEVEPTISR_NAKINI (0x1u << 4)

#define USBHS_DEVEPTISR_OVERFI (0x1u << 5)

#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6)

#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7)

#define USBHS_DEVEPTISR_DTSEQ_Pos 8

#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos)

#define   USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8)

#define   USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8)

#define   USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8)

#define   USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8)

#define USBHS_DEVEPTISR_NBUSYBK_Pos 12

#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos)

#define   USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12)

#define   USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12)

#define   USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12)

#define   USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12)

#define USBHS_DEVEPTISR_CURRBK_Pos 14

#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos)

#define   USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14)

#define   USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14)

#define   USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14)

#define USBHS_DEVEPTISR_RWALL (0x1u << 16)

#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17)

#define USBHS_DEVEPTISR_CFGOK (0x1u << 18)

#define USBHS_DEVEPTISR_BYCT_Pos 20

#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos)

#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2)

#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3)

#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4)

#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6)

#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10)

/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */

#define USBHS_DEVEPTICR_TXINIC (0x1u << 0)

#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1)

#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2)

#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3)

#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4)

#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5)

#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6)

#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7)

#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2)

#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3)

#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4)

#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6)

/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */

#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0)

#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1)

#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2)

#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3)

#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4)

#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5)

#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6)

#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7)

#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12)

#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2)

#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3)

#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4)

#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6)

/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */

#define USBHS_DEVEPTIMR_TXINE (0x1u << 0)

#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1)

#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2)

#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3)

#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4)

#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5)

#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6)

#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7)

#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12)

#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13)

#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14)

#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16)

#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17)

#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18)

#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19)

#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2)

#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3)

#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4)

#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6)

#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8)

#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9)

#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10)

/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */

#define USBHS_DEVEPTIER_TXINES (0x1u << 0)

#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1)

#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2)

#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3)

#define USBHS_DEVEPTIER_NAKINES (0x1u << 4)

#define USBHS_DEVEPTIER_OVERFES (0x1u << 5)

#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6)

#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7)

#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12)

#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13)

#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14)

#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16)

#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17)

#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18)

#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19)

#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2)

#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3)

#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4)

#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6)

#define USBHS_DEVEPTIER_MDATAES (0x1u << 8)

#define USBHS_DEVEPTIER_DATAXES (0x1u << 9)

#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10)

/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */

#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0)

#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1)

#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2)

#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3)

#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4)

#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5)

#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6)

#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7)

#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12)

#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14)

#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16)

#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17)

#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19)

#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2)

#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3)

#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4)

#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6)

#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8)

#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9)

#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10)

/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */

#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0

#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)

#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))

/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */

#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0

#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)

#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)))

/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */

#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0)

#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1)

#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2)

#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3)

#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4)

#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5)

#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6)

#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7)

#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16

#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)

#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))

/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */

#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0)

#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1)

#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4)

#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5)

#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6)

#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16

#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)

#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)))

/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */

#define USBHS_HSTCTRL_SOFE (0x1u << 8)

#define USBHS_HSTCTRL_RESET (0x1u << 9)

#define USBHS_HSTCTRL_RESUME (0x1u << 10)

#define USBHS_HSTCTRL_SPDCONF_Pos 12

#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos)

#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)))

#define   USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12)

#define   USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12)

#define   USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12)

#define   USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12)

/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */

#define USBHS_HSTISR_DCONNI (0x1u << 0)

#define USBHS_HSTISR_DDISCI (0x1u << 1)

#define USBHS_HSTISR_RSTI (0x1u << 2)

#define USBHS_HSTISR_RSMEDI (0x1u << 3)

#define USBHS_HSTISR_RXRSMI (0x1u << 4)

#define USBHS_HSTISR_HSOFI (0x1u << 5)

#define USBHS_HSTISR_HWUPI (0x1u << 6)

#define USBHS_HSTISR_PEP_0 (0x1u << 8)

#define USBHS_HSTISR_PEP_1 (0x1u << 9)

#define USBHS_HSTISR_PEP_2 (0x1u << 10)

#define USBHS_HSTISR_PEP_3 (0x1u << 11)

#define USBHS_HSTISR_PEP_4 (0x1u << 12)

#define USBHS_HSTISR_PEP_5 (0x1u << 13)

#define USBHS_HSTISR_PEP_6 (0x1u << 14)

#define USBHS_HSTISR_PEP_7 (0x1u << 15)

#define USBHS_HSTISR_PEP_8 (0x1u << 16)

#define USBHS_HSTISR_PEP_9 (0x1u << 17)

#define USBHS_HSTISR_PEP_10 (0x1u << 18)

#define USBHS_HSTISR_PEP_11 (0x1u << 19)

#define USBHS_HSTISR_DMA_1 (0x1u << 25)

#define USBHS_HSTISR_DMA_2 (0x1u << 26)

#define USBHS_HSTISR_DMA_3 (0x1u << 27)

#define USBHS_HSTISR_DMA_4 (0x1u << 28)

#define USBHS_HSTISR_DMA_5 (0x1u << 29)

#define USBHS_HSTISR_DMA_6 (0x1u << 30)

#define USBHS_HSTISR_DMA_7 (0x1u << 31)

/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */

#define USBHS_HSTICR_DCONNIC (0x1u << 0)

#define USBHS_HSTICR_DDISCIC (0x1u << 1)

#define USBHS_HSTICR_RSTIC (0x1u << 2)

#define USBHS_HSTICR_RSMEDIC (0x1u << 3)

#define USBHS_HSTICR_RXRSMIC (0x1u << 4)

#define USBHS_HSTICR_HSOFIC (0x1u << 5)

#define USBHS_HSTICR_HWUPIC (0x1u << 6)

/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */

#define USBHS_HSTIFR_DCONNIS (0x1u << 0)

#define USBHS_HSTIFR_DDISCIS (0x1u << 1)

#define USBHS_HSTIFR_RSTIS (0x1u << 2)

#define USBHS_HSTIFR_RSMEDIS (0x1u << 3)

#define USBHS_HSTIFR_RXRSMIS (0x1u << 4)

#define USBHS_HSTIFR_HSOFIS (0x1u << 5)

#define USBHS_HSTIFR_HWUPIS (0x1u << 6)

#define USBHS_HSTIFR_DMA_1 (0x1u << 25)

#define USBHS_HSTIFR_DMA_2 (0x1u << 26)

#define USBHS_HSTIFR_DMA_3 (0x1u << 27)

#define USBHS_HSTIFR_DMA_4 (0x1u << 28)

#define USBHS_HSTIFR_DMA_5 (0x1u << 29)

#define USBHS_HSTIFR_DMA_6 (0x1u << 30)

#define USBHS_HSTIFR_DMA_7 (0x1u << 31)

/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */

#define USBHS_HSTIMR_DCONNIE (0x1u << 0)

#define USBHS_HSTIMR_DDISCIE (0x1u << 1)

#define USBHS_HSTIMR_RSTIE (0x1u << 2)

#define USBHS_HSTIMR_RSMEDIE (0x1u << 3)

#define USBHS_HSTIMR_RXRSMIE (0x1u << 4)

#define USBHS_HSTIMR_HSOFIE (0x1u << 5)

#define USBHS_HSTIMR_HWUPIE (0x1u << 6)

#define USBHS_HSTIMR_PEP_0 (0x1u << 8)

#define USBHS_HSTIMR_PEP_1 (0x1u << 9)

#define USBHS_HSTIMR_PEP_2 (0x1u << 10)

#define USBHS_HSTIMR_PEP_3 (0x1u << 11)

#define USBHS_HSTIMR_PEP_4 (0x1u << 12)

#define USBHS_HSTIMR_PEP_5 (0x1u << 13)

#define USBHS_HSTIMR_PEP_6 (0x1u << 14)

#define USBHS_HSTIMR_PEP_7 (0x1u << 15)

#define USBHS_HSTIMR_PEP_8 (0x1u << 16)

#define USBHS_HSTIMR_PEP_9 (0x1u << 17)

#define USBHS_HSTIMR_PEP_10 (0x1u << 18)

#define USBHS_HSTIMR_PEP_11 (0x1u << 19)

#define USBHS_HSTIMR_DMA_1 (0x1u << 25)

#define USBHS_HSTIMR_DMA_2 (0x1u << 26)

#define USBHS_HSTIMR_DMA_3 (0x1u << 27)

#define USBHS_HSTIMR_DMA_4 (0x1u << 28)

#define USBHS_HSTIMR_DMA_5 (0x1u << 29)

#define USBHS_HSTIMR_DMA_6 (0x1u << 30)

#define USBHS_HSTIMR_DMA_7 (0x1u << 31)

/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */

#define USBHS_HSTIDR_DCONNIEC (0x1u << 0)

#define USBHS_HSTIDR_DDISCIEC (0x1u << 1)

#define USBHS_HSTIDR_RSTIEC (0x1u << 2)

#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3)

#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4)

#define USBHS_HSTIDR_HSOFIEC (0x1u << 5)

#define USBHS_HSTIDR_HWUPIEC (0x1u << 6)

#define USBHS_HSTIDR_PEP_0 (0x1u << 8)

#define USBHS_HSTIDR_PEP_1 (0x1u << 9)

#define USBHS_HSTIDR_PEP_2 (0x1u << 10)

#define USBHS_HSTIDR_PEP_3 (0x1u << 11)

#define USBHS_HSTIDR_PEP_4 (0x1u << 12)

#define USBHS_HSTIDR_PEP_5 (0x1u << 13)

#define USBHS_HSTIDR_PEP_6 (0x1u << 14)

#define USBHS_HSTIDR_PEP_7 (0x1u << 15)

#define USBHS_HSTIDR_PEP_8 (0x1u << 16)

#define USBHS_HSTIDR_PEP_9 (0x1u << 17)

#define USBHS_HSTIDR_PEP_10 (0x1u << 18)

#define USBHS_HSTIDR_PEP_11 (0x1u << 19)

#define USBHS_HSTIDR_DMA_1 (0x1u << 25)

#define USBHS_HSTIDR_DMA_2 (0x1u << 26)

#define USBHS_HSTIDR_DMA_3 (0x1u << 27)

#define USBHS_HSTIDR_DMA_4 (0x1u << 28)

#define USBHS_HSTIDR_DMA_5 (0x1u << 29)

#define USBHS_HSTIDR_DMA_6 (0x1u << 30)

#define USBHS_HSTIDR_DMA_7 (0x1u << 31)

/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */

#define USBHS_HSTIER_DCONNIES (0x1u << 0)

#define USBHS_HSTIER_DDISCIES (0x1u << 1)

#define USBHS_HSTIER_RSTIES (0x1u << 2)

#define USBHS_HSTIER_RSMEDIES (0x1u << 3)

#define USBHS_HSTIER_RXRSMIES (0x1u << 4)

#define USBHS_HSTIER_HSOFIES (0x1u << 5)

#define USBHS_HSTIER_HWUPIES (0x1u << 6)

#define USBHS_HSTIER_PEP_0 (0x1u << 8)

#define USBHS_HSTIER_PEP_1 (0x1u << 9)

#define USBHS_HSTIER_PEP_2 (0x1u << 10)

#define USBHS_HSTIER_PEP_3 (0x1u << 11)

#define USBHS_HSTIER_PEP_4 (0x1u << 12)

#define USBHS_HSTIER_PEP_5 (0x1u << 13)

#define USBHS_HSTIER_PEP_6 (0x1u << 14)

#define USBHS_HSTIER_PEP_7 (0x1u << 15)

#define USBHS_HSTIER_PEP_8 (0x1u << 16)

#define USBHS_HSTIER_PEP_9 (0x1u << 17)

#define USBHS_HSTIER_PEP_10 (0x1u << 18)

#define USBHS_HSTIER_PEP_11 (0x1u << 19)

#define USBHS_HSTIER_DMA_1 (0x1u << 25)

#define USBHS_HSTIER_DMA_2 (0x1u << 26)

#define USBHS_HSTIER_DMA_3 (0x1u << 27)

#define USBHS_HSTIER_DMA_4 (0x1u << 28)

#define USBHS_HSTIER_DMA_5 (0x1u << 29)

#define USBHS_HSTIER_DMA_6 (0x1u << 30)

#define USBHS_HSTIER_DMA_7 (0x1u << 31)

/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */

#define USBHS_HSTPIP_PEN0 (0x1u << 0)

#define USBHS_HSTPIP_PEN1 (0x1u << 1)

#define USBHS_HSTPIP_PEN2 (0x1u << 2)

#define USBHS_HSTPIP_PEN3 (0x1u << 3)

#define USBHS_HSTPIP_PEN4 (0x1u << 4)

#define USBHS_HSTPIP_PEN5 (0x1u << 5)

#define USBHS_HSTPIP_PEN6 (0x1u << 6)

#define USBHS_HSTPIP_PEN7 (0x1u << 7)

#define USBHS_HSTPIP_PEN8 (0x1u << 8)

#define USBHS_HSTPIP_PRST0 (0x1u << 16)

#define USBHS_HSTPIP_PRST1 (0x1u << 17)

#define USBHS_HSTPIP_PRST2 (0x1u << 18)

#define USBHS_HSTPIP_PRST3 (0x1u << 19)

#define USBHS_HSTPIP_PRST4 (0x1u << 20)

#define USBHS_HSTPIP_PRST5 (0x1u << 21)

#define USBHS_HSTPIP_PRST6 (0x1u << 22)

#define USBHS_HSTPIP_PRST7 (0x1u << 23)

#define USBHS_HSTPIP_PRST8 (0x1u << 24)

/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */

#define USBHS_HSTFNUM_MFNUM_Pos 0

#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos)

#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)))

#define USBHS_HSTFNUM_FNUM_Pos 3

#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos)

#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)))

#define USBHS_HSTFNUM_FLENHIGH_Pos 16

#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos)

#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)))

/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */

#define USBHS_HSTADDR1_HSTADDRP0_Pos 0

#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos)

#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)))

#define USBHS_HSTADDR1_HSTADDRP1_Pos 8

#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos)

#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)))

#define USBHS_HSTADDR1_HSTADDRP2_Pos 16

#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos)

#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)))

#define USBHS_HSTADDR1_HSTADDRP3_Pos 24

#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos)

#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)))

/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */

#define USBHS_HSTADDR2_HSTADDRP4_Pos 0

#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos)

#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)))

#define USBHS_HSTADDR2_HSTADDRP5_Pos 8

#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos)

#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)))

#define USBHS_HSTADDR2_HSTADDRP6_Pos 16

#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos)

#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)))

#define USBHS_HSTADDR2_HSTADDRP7_Pos 24

#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos)

#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)))

/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */

#define USBHS_HSTADDR3_HSTADDRP8_Pos 0

#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos)

#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)))

#define USBHS_HSTADDR3_HSTADDRP9_Pos 8

#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos)

#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)))

/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */

#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1)

#define USBHS_HSTPIPCFG_PBK_Pos 2

#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos)

#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)))

#define   USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2)

#define   USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2)

#define   USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2)

#define USBHS_HSTPIPCFG_PSIZE_Pos 4

#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos)

#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)))

#define   USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4)

#define   USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4)

#define   USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4)

#define   USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4)

#define   USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4)

#define   USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4)

#define   USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4)

#define   USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4)

#define USBHS_HSTPIPCFG_PTOKEN_Pos 8

#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos)

#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)))

#define   USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8)

#define   USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8)

#define   USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8)

#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10)

#define USBHS_HSTPIPCFG_PTYPE_Pos 12

#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos)

#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)))

#define   USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12)

#define   USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12)

#define   USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12)

#define   USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12)

#define USBHS_HSTPIPCFG_PEPNUM_Pos 16

#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos)

#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)))

#define USBHS_HSTPIPCFG_INTFRQ_Pos 24

#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos)

#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)))

#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20)

#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24

#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos)

#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos)))

/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */

#define USBHS_HSTPIPISR_RXINI (0x1u << 0)

#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1)

#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2)

#define USBHS_HSTPIPISR_PERRI (0x1u << 3)

#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4)

#define USBHS_HSTPIPISR_OVERFI (0x1u << 5)

#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6)

#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7)

#define USBHS_HSTPIPISR_DTSEQ_Pos 8

#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos)

#define   USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8)

#define   USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8)

#define USBHS_HSTPIPISR_NBUSYBK_Pos 12

#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos)

#define   USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12)

#define   USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12)

#define   USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12)

#define   USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12)

#define USBHS_HSTPIPISR_CURRBK_Pos 14

#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos)

#define   USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14)

#define   USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14)

#define   USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14)

#define USBHS_HSTPIPISR_RWALL (0x1u << 16)

#define USBHS_HSTPIPISR_CFGOK (0x1u << 18)

#define USBHS_HSTPIPISR_PBYCT_Pos 20

#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos)

#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2)

#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6)

/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */

#define USBHS_HSTPIPICR_RXINIC (0x1u << 0)

#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1)

#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2)

#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4)

#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5)

#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6)

#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7)

#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2)

#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6)

/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */

#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0)

#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1)

#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2)

#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3)

#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4)

#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5)

#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6)

#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7)

#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12)

#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2)

#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6)

/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */

#define USBHS_HSTPIPIMR_RXINE (0x1u << 0)

#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1)

#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2)

#define USBHS_HSTPIPIMR_PERRE (0x1u << 3)

#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4)

#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5)

#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6)

#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7)

#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12)

#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14)

#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16)

#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17)

#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18)

#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2)

#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6)

/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */

#define USBHS_HSTPIPIER_RXINES (0x1u << 0)

#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1)

#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2)

#define USBHS_HSTPIPIER_PERRES (0x1u << 3)

#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4)

#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5)

#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6)

#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7)

#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12)

#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16)

#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17)

#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18)

#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2)

#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6)

/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */

#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0)

#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1)

#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2)

#define USBHS_HSTPIPIDR_PERREC (0x1u << 3)

#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4)

#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5)

#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6)

#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7)

#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12)

#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14)

#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16)

#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17)

#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2)

#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6)

/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */

#define USBHS_HSTPIPINRQ_INRQ_Pos 0

#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos)

#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)))

#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8)

/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */

#define USBHS_HSTPIPERR_DATATGL (0x1u << 0)

#define USBHS_HSTPIPERR_DATAPID (0x1u << 1)

#define USBHS_HSTPIPERR_PID (0x1u << 2)

#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3)

#define USBHS_HSTPIPERR_CRC16 (0x1u << 4)

#define USBHS_HSTPIPERR_COUNTER_Pos 5

#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos)

#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)))

/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */

#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0

#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)

#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))

/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */

#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0

#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)

#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)))

/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */

#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0)

#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1)

#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2)

#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3)

#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4)

#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5)

#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6)

#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7)

#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16

#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)

#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))

/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */

#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0)

#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1)

#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4)

#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5)

#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6)

#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16

#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)

#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)))

/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */

#define USBHS_CTRL_RDERRE (0x1u << 4)

#define USBHS_CTRL_VBUSHWC (0x1u << 8)

#define USBHS_CTRL_FRZCLK (0x1u << 14)

#define USBHS_CTRL_USBE (0x1u << 15)

#define USBHS_CTRL_UIMOD (0x1u << 25)

#define   USBHS_CTRL_UIMOD_HOST (0x0u << 25)

#define   USBHS_CTRL_UIMOD_DEVICE (0x1u << 25)

/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */

#define USBHS_SR_RDERRI (0x1u << 4)

#define USBHS_SR_VBUSRQ (0x1u << 9)

#define USBHS_SR_SPEED_Pos 12

#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos)

#define   USBHS_SR_SPEED_FULL_SPEED (0x0u << 12)

#define   USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12)

#define   USBHS_SR_SPEED_LOW_SPEED (0x2u << 12)

#define USBHS_SR_CLKUSABLE (0x1u << 14)

/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */

#define USBHS_SCR_RDERRIC (0x1u << 4)

#define USBHS_SCR_VBUSRQC (0x1u << 9)

/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */

#define USBHS_SFR_RDERRIS (0x1u << 4)

#define USBHS_SFR_VBUSRQS (0x1u << 9)


#endif /* _SAME70_USBHS_COMPONENT_ */

__O
#define __O
Definition: core_cm7.h:286

__IO
#define __IO
Definition: core_cm7.h:287

__I
#define __I
Definition: core_cm7.h:284

UsbhsDevdma
UsbhsDevdma hardware registers.
Definition: component_usbhs.h:41

UsbhsDevdma::USBHS_DEVDMACONTROL
__IO uint32_t USBHS_DEVDMACONTROL
(UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register
Definition: component_usbhs.h:44

UsbhsDevdma::USBHS_DEVDMAADDRESS
__IO uint32_t USBHS_DEVDMAADDRESS
(UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register
Definition: component_usbhs.h:43

UsbhsDevdma::USBHS_DEVDMANXTDSC
__IO uint32_t USBHS_DEVDMANXTDSC
(UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register
Definition: component_usbhs.h:42

UsbhsDevdma::USBHS_DEVDMASTATUS
__IO uint32_t USBHS_DEVDMASTATUS
(UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register
Definition: component_usbhs.h:45

UsbhsHstdma
UsbhsHstdma hardware registers.
Definition: component_usbhs.h:48

UsbhsHstdma::USBHS_HSTDMASTATUS
__IO uint32_t USBHS_HSTDMASTATUS
(UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register
Definition: component_usbhs.h:52

UsbhsHstdma::USBHS_HSTDMAADDRESS
__IO uint32_t USBHS_HSTDMAADDRESS
(UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register
Definition: component_usbhs.h:50

UsbhsHstdma::USBHS_HSTDMANXTDSC
__IO uint32_t USBHS_HSTDMANXTDSC
(UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register
Definition: component_usbhs.h:49

UsbhsHstdma::USBHS_HSTDMACONTROL
__IO uint32_t USBHS_HSTDMACONTROL
(UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register
Definition: component_usbhs.h:51

Usbhs
Definition: component_usbhs.h:57

Usbhs::USBHS_DEVFNUM
__I uint32_t USBHS_DEVFNUM
(Usbhs Offset: 0x0020) Device Frame Number Register
Definition: component_usbhs.h:66

Usbhs::USBHS_DEVIDR
__O uint32_t USBHS_DEVIDR
(Usbhs Offset: 0x0014) Device Global Interrupt Disable Register
Definition: component_usbhs.h:63

Usbhs::USBHS_HSTCTRL
__IO uint32_t USBHS_HSTCTRL
(Usbhs Offset: 0x0400) Host General Control Register
Definition: component_usbhs.h:84

Usbhs::USBHS_HSTIDR
__O uint32_t USBHS_HSTIDR
(Usbhs Offset: 0x0414) Host Global Interrupt Disable Register
Definition: component_usbhs.h:89

Usbhs::USBHS_DEVIER
__O uint32_t USBHS_DEVIER
(Usbhs Offset: 0x0018) Device Global Interrupt Enable Register
Definition: component_usbhs.h:64

Usbhs::USBHS_DEVISR
__I uint32_t USBHS_DEVISR
(Usbhs Offset: 0x0004) Device Global Interrupt Status Register
Definition: component_usbhs.h:59

Usbhs::USBHS_HSTADDR1
__IO uint32_t USBHS_HSTADDR1
(Usbhs Offset: 0x0424) Host Address 1 Register
Definition: component_usbhs.h:93

Usbhs::USBHS_HSTIER
__O uint32_t USBHS_HSTIER
(Usbhs Offset: 0x0418) Host Global Interrupt Enable Register
Definition: component_usbhs.h:90

Usbhs::USBHS_DEVEPT
__IO uint32_t USBHS_DEVEPT
(Usbhs Offset: 0x001C) Device Endpoint Register
Definition: component_usbhs.h:65

Usbhs::USBHS_HSTIMR
__I uint32_t USBHS_HSTIMR
(Usbhs Offset: 0x0410) Host Global Interrupt Mask Register
Definition: component_usbhs.h:88

Usbhs::USBHS_SR
__I uint32_t USBHS_SR
(Usbhs Offset: 0x0804) General Status Register
Definition: component_usbhs.h:118

Usbhs::USBHS_HSTIFR
__O uint32_t USBHS_HSTIFR
(Usbhs Offset: 0x040C) Host Global Interrupt Set Register
Definition: component_usbhs.h:87

Usbhs::USBHS_DEVIFR
__O uint32_t USBHS_DEVIFR
(Usbhs Offset: 0x000C) Device Global Interrupt Set Register
Definition: component_usbhs.h:61

Usbhs::USBHS_DEVCTRL
__IO uint32_t USBHS_DEVCTRL
(Usbhs Offset: 0x0000) Device General Control Register
Definition: component_usbhs.h:58

Usbhs::USBHS_SCR
__O uint32_t USBHS_SCR
(Usbhs Offset: 0x0808) General Status Clear Register
Definition: component_usbhs.h:119

Usbhs::USBHS_DEVIMR
__I uint32_t USBHS_DEVIMR
(Usbhs Offset: 0x0010) Device Global Interrupt Mask Register
Definition: component_usbhs.h:62

Usbhs::USBHS_HSTPIP
__IO uint32_t USBHS_HSTPIP
(Usbhs Offset: 0x0041C) Host Pipe Register
Definition: component_usbhs.h:91

Usbhs::USBHS_CTRL
__IO uint32_t USBHS_CTRL
(Usbhs Offset: 0x0800) General Control Register
Definition: component_usbhs.h:117

Usbhs::USBHS_SFR
__O uint32_t USBHS_SFR
(Usbhs Offset: 0x080C) General Status Set Register
Definition: component_usbhs.h:120

Usbhs::USBHS_HSTFNUM
__IO uint32_t USBHS_HSTFNUM
(Usbhs Offset: 0x0420) Host Frame Number Register
Definition: component_usbhs.h:92

Usbhs::USBHS_DEVICR
__O uint32_t USBHS_DEVICR
(Usbhs Offset: 0x0008) Device Global Interrupt Clear Register
Definition: component_usbhs.h:60

Usbhs::USBHS_HSTADDR3
__IO uint32_t USBHS_HSTADDR3
(Usbhs Offset: 0x042C) Host Address 3 Register
Definition: component_usbhs.h:95

Usbhs::USBHS_HSTISR
__I uint32_t USBHS_HSTISR
(Usbhs Offset: 0x0404) Host Global Interrupt Status Register
Definition: component_usbhs.h:85

Usbhs::USBHS_HSTICR
__O uint32_t USBHS_HSTICR
(Usbhs Offset: 0x0408) Host Global Interrupt Clear Register
Definition: component_usbhs.h:86

Usbhs::USBHS_HSTADDR2
__IO uint32_t USBHS_HSTADDR2
(Usbhs Offset: 0x0428) Host Address 2 Register
Definition: component_usbhs.h:94