doxygen/5.2/same70_2component_2component__usart_8h_source.html

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/* Copyright (c) 2015, Atmel Corporation                                        */

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#ifndef _SAME70_USART_COMPONENT_

#define _SAME70_USART_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __O  uint32_t US_CR;

  __IO uint32_t US_MR;

  __O  uint32_t US_IER;

  __O  uint32_t US_IDR;

  __I  uint32_t US_IMR;

  __I  uint32_t US_CSR;

  __I  uint32_t US_RHR;

  __O  uint32_t US_THR;

  __IO uint32_t US_BRGR;

  __IO uint32_t US_RTOR;

  __IO uint32_t US_TTGR;

  __I  uint32_t Reserved1[5];

  __IO uint32_t US_FIDI;

  __I  uint32_t US_NER;

  __I  uint32_t Reserved2[1];

  __IO uint32_t US_IF;

  __IO uint32_t US_MAN;

  __IO uint32_t US_LINMR;

  __IO uint32_t US_LINIR;

  __I  uint32_t US_LINBRR;

  __IO uint32_t US_LONMR;

  __IO uint32_t US_LONPR;

  __IO uint32_t US_LONDL;

  __IO uint32_t US_LONL2HDR;

  __I  uint32_t US_LONBL;

  __IO uint32_t US_LONB1TX;

  __IO uint32_t US_LONB1RX;

  __IO uint32_t US_LONPRIO;

  __IO uint32_t US_IDTTX;

  __IO uint32_t US_IDTRX;

  __IO uint32_t US_ICDIFF;

  __I  uint32_t Reserved3[22];

  __IO uint32_t US_WPMR;

  __I  uint32_t US_WPSR;

} Usart;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */

#define US_CR_RSTRX (0x1u << 2)

#define US_CR_RSTTX (0x1u << 3)

#define US_CR_RXEN (0x1u << 4)

#define US_CR_RXDIS (0x1u << 5)

#define US_CR_TXEN (0x1u << 6)

#define US_CR_TXDIS (0x1u << 7)

#define US_CR_RSTSTA (0x1u << 8)

#define US_CR_STTBRK (0x1u << 9)

#define US_CR_STPBRK (0x1u << 10)

#define US_CR_STTTO (0x1u << 11)

#define US_CR_SENDA (0x1u << 12)

#define US_CR_RSTIT (0x1u << 13)

#define US_CR_RSTNACK (0x1u << 14)

#define US_CR_RETTO (0x1u << 15)

#define US_CR_DTREN (0x1u << 16)

#define US_CR_DTRDIS (0x1u << 17)

#define US_CR_RTSEN (0x1u << 18)

#define US_CR_RTSDIS (0x1u << 19)

#define US_CR_LINABT (0x1u << 20)

#define US_CR_LINWKUP (0x1u << 21)

#define US_CR_FCS (0x1u << 18)

#define US_CR_RCS (0x1u << 19)

/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */

#define US_MR_USART_MODE_Pos 0

#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos)

#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)))

#define   US_MR_USART_MODE_NORMAL (0x0u << 0)

#define   US_MR_USART_MODE_RS485 (0x1u << 0)

#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0)

#define   US_MR_USART_MODE_MODEM (0x3u << 0)

#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0)

#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0)

#define   US_MR_USART_MODE_IRDA (0x8u << 0)

#define   US_MR_USART_MODE_LON (0x9u << 0)

#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0)

#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0)

#define US_MR_USCLKS_Pos 4

#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos)

#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)))

#define   US_MR_USCLKS_MCK (0x0u << 4)

#define   US_MR_USCLKS_DIV (0x1u << 4)

#define   US_MR_USCLKS_PCK (0x2u << 4)

#define   US_MR_USCLKS_SCK (0x3u << 4)

#define US_MR_CHRL_Pos 6

#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos)

#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)))

#define   US_MR_CHRL_5_BIT (0x0u << 6)

#define   US_MR_CHRL_6_BIT (0x1u << 6)

#define   US_MR_CHRL_7_BIT (0x2u << 6)

#define   US_MR_CHRL_8_BIT (0x3u << 6)

#define US_MR_SYNC (0x1u << 8)

#define US_MR_PAR_Pos 9

#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos)

#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)))

#define   US_MR_PAR_EVEN (0x0u << 9)

#define   US_MR_PAR_ODD (0x1u << 9)

#define   US_MR_PAR_SPACE (0x2u << 9)

#define   US_MR_PAR_MARK (0x3u << 9)

#define   US_MR_PAR_NO (0x4u << 9)

#define   US_MR_PAR_MULTIDROP (0x6u << 9)

#define US_MR_NBSTOP_Pos 12

#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos)

#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)))

#define   US_MR_NBSTOP_1_BIT (0x0u << 12)

#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12)

#define   US_MR_NBSTOP_2_BIT (0x2u << 12)

#define US_MR_CHMODE_Pos 14

#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos)

#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)))

#define   US_MR_CHMODE_NORMAL (0x0u << 14)

#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14)

#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14)

#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14)

#define US_MR_MSBF (0x1u << 16)

#define US_MR_MODE9 (0x1u << 17)

#define US_MR_CLKO (0x1u << 18)

#define US_MR_OVER (0x1u << 19)

#define US_MR_INACK (0x1u << 20)

#define US_MR_DSNACK (0x1u << 21)

#define US_MR_VAR_SYNC (0x1u << 22)

#define US_MR_INVDATA (0x1u << 23)

#define US_MR_MAX_ITERATION_Pos 24

#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos)

#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))

#define US_MR_FILTER (0x1u << 28)

#define US_MR_MAN (0x1u << 29)

#define US_MR_MODSYNC (0x1u << 30)

#define US_MR_ONEBIT (0x1u << 31)

#define US_MR_CPHA (0x1u << 8)

#define US_MR_CPOL (0x1u << 16)

#define US_MR_WRDBT (0x1u << 20)

/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */

#define US_IER_RXRDY (0x1u << 0)

#define US_IER_TXRDY (0x1u << 1)

#define US_IER_RXBRK (0x1u << 2)

#define US_IER_OVRE (0x1u << 5)

#define US_IER_FRAME (0x1u << 6)

#define US_IER_PARE (0x1u << 7)

#define US_IER_TIMEOUT (0x1u << 8)

#define US_IER_TXEMPTY (0x1u << 9)

#define US_IER_ITER (0x1u << 10)

#define US_IER_NACK (0x1u << 13)

#define US_IER_RIIC (0x1u << 16)

#define US_IER_DSRIC (0x1u << 17)

#define US_IER_DCDIC (0x1u << 18)

#define US_IER_CTSIC (0x1u << 19)

#define US_IER_MANE (0x1u << 24)

#define US_IER_UNRE (0x1u << 10)

#define US_IER_NSSE (0x1u << 19)

#define US_IER_LINBK (0x1u << 13)

#define US_IER_LINID (0x1u << 14)

#define US_IER_LINTC (0x1u << 15)

#define US_IER_LINBE (0x1u << 25)

#define US_IER_LINISFE (0x1u << 26)

#define US_IER_LINIPE (0x1u << 27)

#define US_IER_LINCE (0x1u << 28)

#define US_IER_LINSNRE (0x1u << 29)

#define US_IER_LINSTE (0x1u << 30)

#define US_IER_LINHTE (0x1u << 31)

#define US_IER_LSFE (0x1u << 6)

#define US_IER_LCRCE (0x1u << 7)

#define US_IER_LTXD (0x1u << 24)

#define US_IER_LCOL (0x1u << 25)

#define US_IER_LFET (0x1u << 26)

#define US_IER_LRXD (0x1u << 27)

#define US_IER_LBLOVFE (0x1u << 28)

/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */

#define US_IDR_RXRDY (0x1u << 0)

#define US_IDR_TXRDY (0x1u << 1)

#define US_IDR_RXBRK (0x1u << 2)

#define US_IDR_OVRE (0x1u << 5)

#define US_IDR_FRAME (0x1u << 6)

#define US_IDR_PARE (0x1u << 7)

#define US_IDR_TIMEOUT (0x1u << 8)

#define US_IDR_TXEMPTY (0x1u << 9)

#define US_IDR_ITER (0x1u << 10)

#define US_IDR_NACK (0x1u << 13)

#define US_IDR_RIIC (0x1u << 16)

#define US_IDR_DSRIC (0x1u << 17)

#define US_IDR_DCDIC (0x1u << 18)

#define US_IDR_CTSIC (0x1u << 19)

#define US_IDR_MANE (0x1u << 24)

#define US_IDR_UNRE (0x1u << 10)

#define US_IDR_NSSE (0x1u << 19)

#define US_IDR_LINBK (0x1u << 13)

#define US_IDR_LINID (0x1u << 14)

#define US_IDR_LINTC (0x1u << 15)

#define US_IDR_LINBE (0x1u << 25)

#define US_IDR_LINISFE (0x1u << 26)

#define US_IDR_LINIPE (0x1u << 27)

#define US_IDR_LINCE (0x1u << 28)

#define US_IDR_LINSNRE (0x1u << 29)

#define US_IDR_LINSTE (0x1u << 30)

#define US_IDR_LINHTE (0x1u << 31)

#define US_IDR_LSFE (0x1u << 6)

#define US_IDR_LCRCE (0x1u << 7)

#define US_IDR_LTXD (0x1u << 24)

#define US_IDR_LCOL (0x1u << 25)

#define US_IDR_LFET (0x1u << 26)

#define US_IDR_LRXD (0x1u << 27)

#define US_IDR_LBLOVFE (0x1u << 28)

/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */

#define US_IMR_RXRDY (0x1u << 0)

#define US_IMR_TXRDY (0x1u << 1)

#define US_IMR_RXBRK (0x1u << 2)

#define US_IMR_OVRE (0x1u << 5)

#define US_IMR_FRAME (0x1u << 6)

#define US_IMR_PARE (0x1u << 7)

#define US_IMR_TIMEOUT (0x1u << 8)

#define US_IMR_TXEMPTY (0x1u << 9)

#define US_IMR_ITER (0x1u << 10)

#define US_IMR_NACK (0x1u << 13)

#define US_IMR_RIIC (0x1u << 16)

#define US_IMR_DSRIC (0x1u << 17)

#define US_IMR_DCDIC (0x1u << 18)

#define US_IMR_CTSIC (0x1u << 19)

#define US_IMR_MANE (0x1u << 24)

#define US_IMR_UNRE (0x1u << 10)

#define US_IMR_NSSE (0x1u << 19)

#define US_IMR_LINBK (0x1u << 13)

#define US_IMR_LINID (0x1u << 14)

#define US_IMR_LINTC (0x1u << 15)

#define US_IMR_LINBE (0x1u << 25)

#define US_IMR_LINISFE (0x1u << 26)

#define US_IMR_LINIPE (0x1u << 27)

#define US_IMR_LINCE (0x1u << 28)

#define US_IMR_LINSNRE (0x1u << 29)

#define US_IMR_LINSTE (0x1u << 30)

#define US_IMR_LINHTE (0x1u << 31)

#define US_IMR_LSFE (0x1u << 6)

#define US_IMR_LCRCE (0x1u << 7)

#define US_IMR_LTXD (0x1u << 24)

#define US_IMR_LCOL (0x1u << 25)

#define US_IMR_LFET (0x1u << 26)

#define US_IMR_LRXD (0x1u << 27)

#define US_IMR_LBLOVFE (0x1u << 28)

/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */

#define US_CSR_RXRDY (0x1u << 0)

#define US_CSR_TXRDY (0x1u << 1)

#define US_CSR_RXBRK (0x1u << 2)

#define US_CSR_OVRE (0x1u << 5)

#define US_CSR_FRAME (0x1u << 6)

#define US_CSR_PARE (0x1u << 7)

#define US_CSR_TIMEOUT (0x1u << 8)

#define US_CSR_TXEMPTY (0x1u << 9)

#define US_CSR_ITER (0x1u << 10)

#define US_CSR_NACK (0x1u << 13)

#define US_CSR_RIIC (0x1u << 16)

#define US_CSR_DSRIC (0x1u << 17)

#define US_CSR_DCDIC (0x1u << 18)

#define US_CSR_CTSIC (0x1u << 19)

#define US_CSR_RI (0x1u << 20)

#define US_CSR_DSR (0x1u << 21)

#define US_CSR_DCD (0x1u << 22)

#define US_CSR_CTS (0x1u << 23)

#define US_CSR_MANERR (0x1u << 24)

#define US_CSR_UNRE (0x1u << 10)

#define US_CSR_NSSE (0x1u << 19)

#define US_CSR_NSS (0x1u << 23)

#define US_CSR_LINBK (0x1u << 13)

#define US_CSR_LINID (0x1u << 14)

#define US_CSR_LINTC (0x1u << 15)

#define US_CSR_LINBLS (0x1u << 23)

#define US_CSR_LINBE (0x1u << 25)

#define US_CSR_LINISFE (0x1u << 26)

#define US_CSR_LINIPE (0x1u << 27)

#define US_CSR_LINCE (0x1u << 28)

#define US_CSR_LINSNRE (0x1u << 29)

#define US_CSR_LINSTE (0x1u << 30)

#define US_CSR_LINHTE (0x1u << 31)

#define US_CSR_LSFE (0x1u << 6)

#define US_CSR_LCRCE (0x1u << 7)

#define US_CSR_LTXD (0x1u << 24)

#define US_CSR_LCOL (0x1u << 25)

#define US_CSR_LFET (0x1u << 26)

#define US_CSR_LRXD (0x1u << 27)

#define US_CSR_LBLOVFE (0x1u << 28)

/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */

#define US_RHR_RXCHR_Pos 0

#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos)

#define US_RHR_RXSYNH (0x1u << 15)

/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */

#define US_THR_TXCHR_Pos 0

#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos)

#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))

#define US_THR_TXSYNH (0x1u << 15)

/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */

#define US_BRGR_CD_Pos 0

#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos)

#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))

#define US_BRGR_FP_Pos 16

#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos)

#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))

/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */

#define US_RTOR_TO_Pos 0

#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos)

#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))

/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */

#define US_TTGR_TG_Pos 0

#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos)

#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))

#define US_TTGR_PCYCLE_Pos 0

#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos)

#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos)))

/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */

#define US_FIDI_FI_DI_RATIO_Pos 0

#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos)

#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))

#define US_FIDI_BETA2_Pos 0

#define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos)

#define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos)))

/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */

#define US_NER_NB_ERRORS_Pos 0

#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos)

/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */

#define US_IF_IRDA_FILTER_Pos 0

#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos)

#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))

/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */

#define US_MAN_TX_PL_Pos 0

#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos)

#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))

#define US_MAN_TX_PP_Pos 8

#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos)

#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)))

#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8)

#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8)

#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8)

#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8)

#define US_MAN_TX_MPOL (0x1u << 12)

#define US_MAN_RX_PL_Pos 16

#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos)

#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))

#define US_MAN_RX_PP_Pos 24

#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos)

#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)))

#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24)

#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24)

#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24)

#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24)

#define US_MAN_RX_MPOL (0x1u << 28)

#define US_MAN_ONE (0x1u << 29)

#define US_MAN_DRIFT (0x1u << 30)

#define US_MAN_RXIDLEV (0x1u << 31)

/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */

#define US_LINMR_NACT_Pos 0

#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos)

#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)))

#define   US_LINMR_NACT_PUBLISH (0x0u << 0)

#define   US_LINMR_NACT_SUBSCRIBE (0x1u << 0)

#define   US_LINMR_NACT_IGNORE (0x2u << 0)

#define US_LINMR_PARDIS (0x1u << 2)

#define US_LINMR_CHKDIS (0x1u << 3)

#define US_LINMR_CHKTYP (0x1u << 4)

#define US_LINMR_DLM (0x1u << 5)

#define US_LINMR_FSDIS (0x1u << 6)

#define US_LINMR_WKUPTYP (0x1u << 7)

#define US_LINMR_DLC_Pos 8

#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos)

#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))

#define US_LINMR_PDCM (0x1u << 16)

#define US_LINMR_SYNCDIS (0x1u << 17)

/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */

#define US_LINIR_IDCHR_Pos 0

#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos)

#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))

/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */

#define US_LINBRR_LINCD_Pos 0

#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos)

#define US_LINBRR_LINFP_Pos 16

#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos)

/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */

#define US_LONMR_COMMT (0x1u << 0)

#define US_LONMR_COLDET (0x1u << 1)

#define US_LONMR_TCOL (0x1u << 2)

#define US_LONMR_CDTAIL (0x1u << 3)

#define US_LONMR_DMAM (0x1u << 4)

#define US_LONMR_LCDS (0x1u << 5)

#define US_LONMR_EOFS_Pos 16

#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos)

#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)))

/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */

#define US_LONPR_LONPL_Pos 0

#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos)

#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)))

/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */

#define US_LONDL_LONDL_Pos 0

#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos)

#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)))

/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */

#define US_LONL2HDR_BLI_Pos 0

#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos)

#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)))

#define US_LONL2HDR_ALTP (0x1u << 6)

#define US_LONL2HDR_PB (0x1u << 7)

/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */

#define US_LONBL_LONBL_Pos 0

#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos)

/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */

#define US_LONB1TX_BETA1TX_Pos 0

#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos)

#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)))

/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */

#define US_LONB1RX_BETA1RX_Pos 0

#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos)

#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)))

/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */

#define US_LONPRIO_PSNB_Pos 0

#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos)

#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)))

#define US_LONPRIO_NPS_Pos 8

#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos)

#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)))

/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */

#define US_IDTTX_IDTTX_Pos 0

#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos)

#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)))

/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */

#define US_IDTRX_IDTRX_Pos 0

#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos)

#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)))

/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */

#define US_ICDIFF_ICDIFF_Pos 0

#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos)

#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)))

/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */

#define US_WPMR_WPEN (0x1u << 0)

#define US_WPMR_WPKEY_Pos 8

#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos)

#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))

#define   US_WPMR_WPKEY_PASSWD (0x555341u << 8)

/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */

#define US_WPSR_WPVS (0x1u << 0)

#define US_WPSR_WPVSRC_Pos 8

#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos)


#endif /* _SAME70_USART_COMPONENT_ */

__O
#define __O
Definition: core_cm7.h:286

__IO
#define __IO
Definition: core_cm7.h:287

__I
#define __I
Definition: core_cm7.h:284

Usart
Usart hardware registers.
Definition: component_usart.h:41

Usart::US_MAN
__IO uint32_t US_MAN
(Usart Offset: 0x0050) Manchester Configuration Register
Definition: component_usart.h:58

Usart::US_ICDIFF
__IO uint32_t US_ICDIFF
(Usart Offset: 0x0088) IC DIFF Register
Definition: component_usart.h:72

Usart::US_LONBL
__I uint32_t US_LONBL
(Usart Offset: 0x0070) LON Backlog Register
Definition: component_usart.h:66

Usart::US_WPSR
__I uint32_t US_WPSR
(Usart Offset: 0x00E8) Write Protection Status Register
Definition: component_usart.h:75

Usart::US_IMR
__I uint32_t US_IMR
(Usart Offset: 0x0010) Interrupt Mask Register
Definition: component_usart.h:46

Usart::US_LONPRIO
__IO uint32_t US_LONPRIO
(Usart Offset: 0x007C) LON Priority Register
Definition: component_usart.h:69

Usart::US_IDTTX
__IO uint32_t US_IDTTX
(Usart Offset: 0x0080) LON IDT Tx Register
Definition: component_usart.h:70

Usart::US_LONMR
__IO uint32_t US_LONMR
(Usart Offset: 0x0060) LON Mode Register
Definition: component_usart.h:62

Usart::US_IF
__IO uint32_t US_IF
(Usart Offset: 0x004C) IrDA Filter Register
Definition: component_usart.h:57

Usart::US_FIDI
__IO uint32_t US_FIDI
(Usart Offset: 0x0040) FI DI Ratio Register
Definition: component_usart.h:54

Usart::US_RTOR
__IO uint32_t US_RTOR
(Usart Offset: 0x0024) Receiver Time-out Register
Definition: component_usart.h:51

Usart::US_THR
__O uint32_t US_THR
(Usart Offset: 0x001C) Transmit Holding Register
Definition: component_usart.h:49

Usart::US_LONDL
__IO uint32_t US_LONDL
(Usart Offset: 0x0068) LON Data Length Register
Definition: component_usart.h:64

Usart::US_IDR
__O uint32_t US_IDR
(Usart Offset: 0x000C) Interrupt Disable Register
Definition: component_usart.h:45

Usart::US_IER
__O uint32_t US_IER
(Usart Offset: 0x0008) Interrupt Enable Register
Definition: component_usart.h:44

Usart::US_LONPR
__IO uint32_t US_LONPR
(Usart Offset: 0x0064) LON Preamble Register
Definition: component_usart.h:63

Usart::US_WPMR
__IO uint32_t US_WPMR
(Usart Offset: 0x00E4) Write Protection Mode Register
Definition: component_usart.h:74

Usart::US_TTGR
__IO uint32_t US_TTGR
(Usart Offset: 0x0028) Transmitter Timeguard Register
Definition: component_usart.h:52

Usart::US_MR
__IO uint32_t US_MR
(Usart Offset: 0x0004) Mode Register
Definition: component_usart.h:43

Usart::US_CR
__O uint32_t US_CR
(Usart Offset: 0x0000) Control Register
Definition: component_usart.h:42

Usart::US_CSR
__I uint32_t US_CSR
(Usart Offset: 0x0014) Channel Status Register
Definition: component_usart.h:47

Usart::US_LONB1RX
__IO uint32_t US_LONB1RX
(Usart Offset: 0x0078) LON Beta1 Rx Register
Definition: component_usart.h:68

Usart::US_LINBRR
__I uint32_t US_LINBRR
(Usart Offset: 0x005C) LIN Baud Rate Register
Definition: component_usart.h:61

Usart::US_BRGR
__IO uint32_t US_BRGR
(Usart Offset: 0x0020) Baud Rate Generator Register
Definition: component_usart.h:50

Usart::US_IDTRX
__IO uint32_t US_IDTRX
(Usart Offset: 0x0084) LON IDT Rx Register
Definition: component_usart.h:71

Usart::US_RHR
__I uint32_t US_RHR
(Usart Offset: 0x0018) Receive Holding Register
Definition: component_usart.h:48

Usart::US_LINIR
__IO uint32_t US_LINIR
(Usart Offset: 0x0058) LIN Identifier Register
Definition: component_usart.h:60

Usart::US_LONB1TX
__IO uint32_t US_LONB1TX
(Usart Offset: 0x0074) LON Beta1 Tx Register
Definition: component_usart.h:67

Usart::US_LONL2HDR
__IO uint32_t US_LONL2HDR
(Usart Offset: 0x006C) LON L2HDR Register
Definition: component_usart.h:65

Usart::US_LINMR
__IO uint32_t US_LINMR
(Usart Offset: 0x0054) LIN Mode Register
Definition: component_usart.h:59

Usart::US_NER
__I uint32_t US_NER
(Usart Offset: 0x0044) Number of Errors Register
Definition: component_usart.h:55