30#ifndef _SAME70_RSTC_COMPONENT_
31#define _SAME70_RSTC_COMPONENT_
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
48#define RSTC_CR_PROCRST (0x1u << 0)
49#define RSTC_CR_EXTRST (0x1u << 3)
50#define RSTC_CR_KEY_Pos 24
51#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos)
52#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
53#define RSTC_CR_KEY_PASSWD (0xA5u << 24)
55#define RSTC_SR_URSTS (0x1u << 0)
56#define RSTC_SR_RSTTYP_Pos 8
57#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos)
58#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8)
59#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8)
60#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8)
61#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8)
62#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8)
63#define RSTC_SR_NRSTL (0x1u << 16)
64#define RSTC_SR_SRCMP (0x1u << 17)
66#define RSTC_MR_URSTEN (0x1u << 0)
67#define RSTC_MR_URSTIEN (0x1u << 4)
68#define RSTC_MR_ERSTL_Pos 8
69#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos)
70#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
71#define RSTC_MR_KEY_Pos 24
72#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos)
73#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
74#define RSTC_MR_KEY_PASSWD (0xA5u << 24)
#define __O
Definition: core_cm7.h:286
#define __IO
Definition: core_cm7.h:287
#define __I
Definition: core_cm7.h:284
Rstc hardware registers.
Definition: component_rstc.h:41
__IO uint32_t RSTC_MR
(Rstc Offset: 0x08) Mode Register
Definition: component_rstc.h:44
__I uint32_t RSTC_SR
(Rstc Offset: 0x04) Status Register
Definition: component_rstc.h:43
__O uint32_t RSTC_CR
(Rstc Offset: 0x00) Control Register
Definition: component_rstc.h:42