doxygen/5.2/same70_2component_2component__gmac_8h_source.html

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#ifndef _SAME70_GMAC_COMPONENT_

#define _SAME70_GMAC_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {

  __IO uint32_t GMAC_SAB;

  __IO uint32_t GMAC_SAT;

} GmacSa;


typedef struct {

   __IO uint32_t GMAC_ST2COM0;

   __IO uint32_t GMAC_ST2COM1;

} GmacSt2Compare;


#define GMACSA_NUMBER 4

#define GMACST2COMPARE_NUMBER 24

typedef struct {

  __IO uint32_t GMAC_NCR;

  __IO uint32_t GMAC_NCFGR;

  __I  uint32_t GMAC_NSR;

  __IO uint32_t GMAC_UR;

  __IO uint32_t GMAC_DCFGR;

  __IO uint32_t GMAC_TSR;

  __IO uint32_t GMAC_RBQB;

  __IO uint32_t GMAC_TBQB;

  __IO uint32_t GMAC_RSR;

  __I  uint32_t GMAC_ISR;

  __O  uint32_t GMAC_IER;

  __O  uint32_t GMAC_IDR;

  __IO uint32_t GMAC_IMR;

  __IO uint32_t GMAC_MAN;

  __I  uint32_t GMAC_RPQ;

  __IO uint32_t GMAC_TPQ;

  __IO uint32_t GMAC_TPSF;

  __IO uint32_t GMAC_RPSF;

  __IO uint32_t GMAC_RJFML;

  __I  uint32_t Reserved1[13];

  __IO uint32_t GMAC_HRB;

  __IO uint32_t GMAC_HRT;

       GmacSa   GMAC_SA[GMACSA_NUMBER];

  __IO uint32_t GMAC_TIDM1;

  __IO uint32_t GMAC_TIDM2;

  __IO uint32_t GMAC_TIDM3;

  __IO uint32_t GMAC_TIDM4;

  __IO uint32_t GMAC_WOL;

  __IO uint32_t GMAC_IPGS;

  __IO uint32_t GMAC_SVLAN;

  __IO uint32_t GMAC_TPFCP;

  __IO uint32_t GMAC_SAMB1;

  __IO uint32_t GMAC_SAMT1;

  __I  uint32_t Reserved2[3];

  __IO uint32_t GMAC_NSC;

  __IO uint32_t GMAC_SCL;

  __IO uint32_t GMAC_SCH;

  __I  uint32_t GMAC_EFTSH;

  __I  uint32_t GMAC_EFRSH;

  __I  uint32_t GMAC_PEFTSH;

  __I  uint32_t GMAC_PEFRSH;

  __I  uint32_t Reserved3[2];

  __I  uint32_t GMAC_OTLO;

  __I  uint32_t GMAC_OTHI;

  __I  uint32_t GMAC_FT;

  __I  uint32_t GMAC_BCFT;

  __I  uint32_t GMAC_MFT;

  __I  uint32_t GMAC_PFT;

  __I  uint32_t GMAC_BFT64;

  __I  uint32_t GMAC_TBFT127;

  __I  uint32_t GMAC_TBFT255;

  __I  uint32_t GMAC_TBFT511;

  __I  uint32_t GMAC_TBFT1023;

  __I  uint32_t GMAC_TBFT1518;

  __I  uint32_t GMAC_GTBFT1518;

  __I  uint32_t GMAC_TUR;

  __I  uint32_t GMAC_SCF;

  __I  uint32_t GMAC_MCF;

  __I  uint32_t GMAC_EC;

  __I  uint32_t GMAC_LC;

  __I  uint32_t GMAC_DTF;

  __I  uint32_t GMAC_CSE;

  __I  uint32_t GMAC_ORLO;

  __I  uint32_t GMAC_ORHI;

  __I  uint32_t GMAC_FR;

  __I  uint32_t GMAC_BCFR;

  __I  uint32_t GMAC_MFR;

  __I  uint32_t GMAC_PFR;

  __I  uint32_t GMAC_BFR64;

  __I  uint32_t GMAC_TBFR127;

  __I  uint32_t GMAC_TBFR255;

  __I  uint32_t GMAC_TBFR511;

  __I  uint32_t GMAC_TBFR1023;

  __I  uint32_t GMAC_TBFR1518;

  __I  uint32_t GMAC_TMXBFR;

  __I  uint32_t GMAC_UFR;

  __I  uint32_t GMAC_OFR;

  __I  uint32_t GMAC_JR;

  __I  uint32_t GMAC_FCSE;

  __I  uint32_t GMAC_LFFE;

  __I  uint32_t GMAC_RSE;

  __I  uint32_t GMAC_AE;

  __I  uint32_t GMAC_RRE;

  __I  uint32_t GMAC_ROE;

  __I  uint32_t GMAC_IHCE;

  __I  uint32_t GMAC_TCE;

  __I  uint32_t GMAC_UCE;

  __I  uint32_t Reserved4[2];

  __IO uint32_t GMAC_TISUBN;

  __IO uint32_t GMAC_TSH;

  __I  uint32_t Reserved5[3];

  __IO uint32_t GMAC_TSL;

  __IO uint32_t GMAC_TN;

  __O  uint32_t GMAC_TA;

  __IO uint32_t GMAC_TI;

  __I  uint32_t GMAC_EFTSL;

  __I  uint32_t GMAC_EFTN;

  __I  uint32_t GMAC_EFRSL;

  __I  uint32_t GMAC_EFRN;

  __I  uint32_t GMAC_PEFTSL;

  __I  uint32_t GMAC_PEFTN;

  __I  uint32_t GMAC_PEFRSL;

  __I  uint32_t GMAC_PEFRN;

  __I  uint32_t Reserved6[128];

  __I  uint32_t GMAC_ISRPQ[2];

  __I  uint32_t Reserved7[14];

  __IO uint32_t GMAC_TBQBAPQ[2];

  __I  uint32_t Reserved8[14];

  __IO uint32_t GMAC_RBQBAPQ[2];

  __I  uint32_t Reserved9[6];

  __IO uint32_t GMAC_RBSRPQ[2];

  __I  uint32_t Reserved10[5];

  __IO uint32_t GMAC_CBSCR;

  __IO uint32_t GMAC_CBSISQA;

  __IO uint32_t GMAC_CBSISQB;

  __I  uint32_t Reserved11[14];

  __IO uint32_t GMAC_ST1RPQ[4];

  __I  uint32_t Reserved12[12];

  __IO uint32_t GMAC_ST2RPQ[8];

  __I  uint32_t Reserved13[12];

  __I  uint32_t Reserved14[28];

  __O  uint32_t GMAC_IERPQ[2];

  __I  uint32_t Reserved15[6];

  __O  uint32_t GMAC_IDRPQ[2];

  __I  uint32_t Reserved16[6];

  __IO uint32_t GMAC_IMRPQ[2];

  __I  uint32_t Reserved17[38];

  __IO uint32_t GMAC_ST2ER[4];

  __I  uint32_t Reserved18[4];

  __IO GmacSt2Compare GMAC_ST2COMP[GMACST2COMPARE_NUMBER];

} Gmac;

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */

#define GMAC_NCR_LBL (0x1u << 1)

#define GMAC_NCR_RXEN (0x1u << 2)

#define GMAC_NCR_TXEN (0x1u << 3)

#define GMAC_NCR_MPE (0x1u << 4)

#define GMAC_NCR_CLRSTAT (0x1u << 5)

#define GMAC_NCR_INCSTAT (0x1u << 6)

#define GMAC_NCR_WESTAT (0x1u << 7)

#define GMAC_NCR_BP (0x1u << 8)

#define GMAC_NCR_TSTART (0x1u << 9)

#define GMAC_NCR_THALT (0x1u << 10)

#define GMAC_NCR_TXPF (0x1u << 11)

#define GMAC_NCR_TXZQPF (0x1u << 12)

#define GMAC_NCR_SRTSM (0x1u << 15)

#define GMAC_NCR_ENPBPR (0x1u << 16)

#define GMAC_NCR_TXPBPF (0x1u << 17)

#define GMAC_NCR_FNP (0x1u << 18)

/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */

#define GMAC_NCFGR_SPD (0x1u << 0)

#define GMAC_NCFGR_FD (0x1u << 1)

#define GMAC_NCFGR_DNVLAN (0x1u << 2)

#define GMAC_NCFGR_JFRAME (0x1u << 3)

#define GMAC_NCFGR_CAF (0x1u << 4)

#define GMAC_NCFGR_NBC (0x1u << 5)

#define GMAC_NCFGR_MTIHEN (0x1u << 6)

#define GMAC_NCFGR_UNIHEN (0x1u << 7)

#define GMAC_NCFGR_MAXFS (0x1u << 8)

#define GMAC_NCFGR_RTY (0x1u << 12)

#define GMAC_NCFGR_PEN (0x1u << 13)

#define GMAC_NCFGR_RXBUFO_Pos 14

#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos)

#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)))

#define GMAC_NCFGR_LFERD (0x1u << 16)

#define GMAC_NCFGR_RFCS (0x1u << 17)

#define GMAC_NCFGR_CLK_Pos 18

#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos)

#define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos)))

#define   GMAC_NCFGR_CLK_MCK_8 (0x0u << 18)

#define   GMAC_NCFGR_CLK_MCK_16 (0x1u << 18)

#define   GMAC_NCFGR_CLK_MCK_32 (0x2u << 18)

#define   GMAC_NCFGR_CLK_MCK_48 (0x3u << 18)

#define   GMAC_NCFGR_CLK_MCK_64 (0x4u << 18)

#define   GMAC_NCFGR_CLK_MCK_96 (0x5u << 18)

#define GMAC_NCFGR_DBW_Pos 21

#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos)

#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)))

#define GMAC_NCFGR_DCPF (0x1u << 23)

#define GMAC_NCFGR_RXCOEN (0x1u << 24)

#define GMAC_NCFGR_EFRHD (0x1u << 25)

#define GMAC_NCFGR_IRXFCS (0x1u << 26)

#define GMAC_NCFGR_IPGSEN (0x1u << 28)

#define GMAC_NCFGR_RXBP (0x1u << 29)

#define GMAC_NCFGR_IRXER (0x1u << 30)

/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */

#define GMAC_NSR_MDIO (0x1u << 1)

#define GMAC_NSR_IDLE (0x1u << 2)

/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */

#define GMAC_UR_RMII (0x1u << 0)

/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */

#define GMAC_DCFGR_FBLDO_Pos 0

#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos)

#define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos)))

#define   GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0)

#define   GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0)

#define   GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0)

#define   GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0)

#define GMAC_DCFGR_ESMA (0x1u << 6)

#define GMAC_DCFGR_ESPA (0x1u << 7)

#define GMAC_DCFGR_RXBMS_Pos 8

#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos)

#define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos)))

#define   GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8)

#define   GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8)

#define   GMAC_DCFGR_RXBMS_HALF (0x2u << 8)

#define   GMAC_DCFGR_RXBMS_FULL (0x3u << 8)

#define GMAC_DCFGR_TXPBMS (0x1u << 10)

#define GMAC_DCFGR_TXCOEN (0x1u << 11)

#define GMAC_DCFGR_DRBS_Pos 16

#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos)

#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)))

#define GMAC_DCFGR_DDRP (0x1u << 24)

/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */

#define GMAC_TSR_UBR (0x1u << 0)

#define GMAC_TSR_COL (0x1u << 1)

#define GMAC_TSR_RLE (0x1u << 2)

#define GMAC_TSR_TXGO (0x1u << 3)

#define GMAC_TSR_TFC (0x1u << 4)

#define GMAC_TSR_TXCOMP (0x1u << 5)

#define GMAC_TSR_HRESP (0x1u << 8)

/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */

#define GMAC_RBQB_ADDR_Pos 2

#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos)

#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)))

/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */

#define GMAC_TBQB_ADDR_Pos 2

#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos)

#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)))

/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */

#define GMAC_RSR_BNA (0x1u << 0)

#define GMAC_RSR_REC (0x1u << 1)

#define GMAC_RSR_RXOVR (0x1u << 2)

#define GMAC_RSR_HNO (0x1u << 3)

/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */

#define GMAC_ISR_MFS (0x1u << 0)

#define GMAC_ISR_RCOMP (0x1u << 1)

#define GMAC_ISR_RXUBR (0x1u << 2)

#define GMAC_ISR_TXUBR (0x1u << 3)

#define GMAC_ISR_TUR (0x1u << 4)

#define GMAC_ISR_RLEX (0x1u << 5)

#define GMAC_ISR_TFC (0x1u << 6)

#define GMAC_ISR_TCOMP (0x1u << 7)

#define GMAC_ISR_ROVR (0x1u << 10)

#define GMAC_ISR_HRESP (0x1u << 11)

#define GMAC_ISR_PFNZ (0x1u << 12)

#define GMAC_ISR_PTZ (0x1u << 13)

#define GMAC_ISR_PFTR (0x1u << 14)

#define GMAC_ISR_DRQFR (0x1u << 18)

#define GMAC_ISR_SFR (0x1u << 19)

#define GMAC_ISR_DRQFT (0x1u << 20)

#define GMAC_ISR_SFT (0x1u << 21)

#define GMAC_ISR_PDRQFR (0x1u << 22)

#define GMAC_ISR_PDRSFR (0x1u << 23)

#define GMAC_ISR_PDRQFT (0x1u << 24)

#define GMAC_ISR_PDRSFT (0x1u << 25)

#define GMAC_ISR_SRI (0x1u << 26)

#define GMAC_ISR_WOL (0x1u << 28)

#define GMAC_ISR_TSU (0x1u << 29)

/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */

#define GMAC_IER_MFS (0x1u << 0)

#define GMAC_IER_RCOMP (0x1u << 1)

#define GMAC_IER_RXUBR (0x1u << 2)

#define GMAC_IER_TXUBR (0x1u << 3)

#define GMAC_IER_TUR (0x1u << 4)

#define GMAC_IER_RLEX (0x1u << 5)

#define GMAC_IER_TFC (0x1u << 6)

#define GMAC_IER_TCOMP (0x1u << 7)

#define GMAC_IER_ROVR (0x1u << 10)

#define GMAC_IER_HRESP (0x1u << 11)

#define GMAC_IER_PFNZ (0x1u << 12)

#define GMAC_IER_PTZ (0x1u << 13)

#define GMAC_IER_PFTR (0x1u << 14)

#define GMAC_IER_EXINT (0x1u << 15)

#define GMAC_IER_DRQFR (0x1u << 18)

#define GMAC_IER_SFR (0x1u << 19)

#define GMAC_IER_DRQFT (0x1u << 20)

#define GMAC_IER_SFT (0x1u << 21)

#define GMAC_IER_PDRQFR (0x1u << 22)

#define GMAC_IER_PDRSFR (0x1u << 23)

#define GMAC_IER_PDRQFT (0x1u << 24)

#define GMAC_IER_PDRSFT (0x1u << 25)

#define GMAC_IER_SRI (0x1u << 26)

#define GMAC_IER_WOL (0x1u << 28)

/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */

#define GMAC_IDR_MFS (0x1u << 0)

#define GMAC_IDR_RCOMP (0x1u << 1)

#define GMAC_IDR_RXUBR (0x1u << 2)

#define GMAC_IDR_TXUBR (0x1u << 3)

#define GMAC_IDR_TUR (0x1u << 4)

#define GMAC_IDR_RLEX (0x1u << 5)

#define GMAC_IDR_TFC (0x1u << 6)

#define GMAC_IDR_TCOMP (0x1u << 7)

#define GMAC_IDR_ROVR (0x1u << 10)

#define GMAC_IDR_HRESP (0x1u << 11)

#define GMAC_IDR_PFNZ (0x1u << 12)

#define GMAC_IDR_PTZ (0x1u << 13)

#define GMAC_IDR_PFTR (0x1u << 14)

#define GMAC_IDR_EXINT (0x1u << 15)

#define GMAC_IDR_DRQFR (0x1u << 18)

#define GMAC_IDR_SFR (0x1u << 19)

#define GMAC_IDR_DRQFT (0x1u << 20)

#define GMAC_IDR_SFT (0x1u << 21)

#define GMAC_IDR_PDRQFR (0x1u << 22)

#define GMAC_IDR_PDRSFR (0x1u << 23)

#define GMAC_IDR_PDRQFT (0x1u << 24)

#define GMAC_IDR_PDRSFT (0x1u << 25)

#define GMAC_IDR_SRI (0x1u << 26)

#define GMAC_IDR_WOL (0x1u << 28)

/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */

#define GMAC_IMR_MFS (0x1u << 0)

#define GMAC_IMR_RCOMP (0x1u << 1)

#define GMAC_IMR_RXUBR (0x1u << 2)

#define GMAC_IMR_TXUBR (0x1u << 3)

#define GMAC_IMR_TUR (0x1u << 4)

#define GMAC_IMR_RLEX (0x1u << 5)

#define GMAC_IMR_TFC (0x1u << 6)

#define GMAC_IMR_TCOMP (0x1u << 7)

#define GMAC_IMR_ROVR (0x1u << 10)

#define GMAC_IMR_HRESP (0x1u << 11)

#define GMAC_IMR_PFNZ (0x1u << 12)

#define GMAC_IMR_PTZ (0x1u << 13)

#define GMAC_IMR_PFTR (0x1u << 14)

#define GMAC_IMR_EXINT (0x1u << 15)

#define GMAC_IMR_DRQFR (0x1u << 18)

#define GMAC_IMR_SFR (0x1u << 19)

#define GMAC_IMR_DRQFT (0x1u << 20)

#define GMAC_IMR_SFT (0x1u << 21)

#define GMAC_IMR_PDRQFR (0x1u << 22)

#define GMAC_IMR_PDRSFR (0x1u << 23)

#define GMAC_IMR_PDRQFT (0x1u << 24)

#define GMAC_IMR_PDRSFT (0x1u << 25)

/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */

#define GMAC_MAN_DATA_Pos 0

#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos)

#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)))

#define GMAC_MAN_WTN_Pos 16

#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos)

#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)))

#define GMAC_MAN_REGA_Pos 18

#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos)

#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)))

#define GMAC_MAN_PHYA_Pos 23

#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos)

#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)))

#define GMAC_MAN_OP_Pos 28

#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos)

#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)))

#define GMAC_MAN_CLTTO (0x1u << 30)

#define GMAC_MAN_WZO (0x1u << 31)

/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */

#define GMAC_RPQ_RPQ_Pos 0

#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos)

/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */

#define GMAC_TPQ_TPQ_Pos 0

#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos)

#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)))

/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */

#define GMAC_TPSF_TPB1ADR_Pos 0

#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos)

#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos)))

#define GMAC_TPSF_ENTXP (0x1u << 31)

/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */

#define GMAC_RPSF_RPB1ADR_Pos 0

#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos)

#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos)))

#define GMAC_RPSF_ENRXP (0x1u << 31)

/* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */

#define GMAC_RJFML_FML_Pos 0

#define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos)

#define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos)))

/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */

#define GMAC_HRB_ADDR_Pos 0

#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos)

#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)))

/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */

#define GMAC_HRT_ADDR_Pos 0

#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos)

#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)))

/* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */

#define GMAC_SAB_ADDR_Pos 0

#define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos)

#define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos)))

/* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */

#define GMAC_SAT_ADDR_Pos 0

#define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos)

#define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos)))

/* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */

#define GMAC_TIDM1_TID_Pos 0

#define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos)

#define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos)))

#define GMAC_TIDM1_ENID1 (0x1u << 31)

/* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */

#define GMAC_TIDM2_TID_Pos 0

#define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos)

#define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos)))

#define GMAC_TIDM2_ENID2 (0x1u << 31)

/* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */

#define GMAC_TIDM3_TID_Pos 0

#define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos)

#define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos)))

#define GMAC_TIDM3_ENID3 (0x1u << 31)

/* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */

#define GMAC_TIDM4_TID_Pos 0

#define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos)

#define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos)))

#define GMAC_TIDM4_ENID4 (0x1u << 31)

/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */

#define GMAC_WOL_IP_Pos 0

#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos)

#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)))

#define GMAC_WOL_MAG (0x1u << 16)

#define GMAC_WOL_ARP (0x1u << 17)

#define GMAC_WOL_SA1 (0x1u << 18)

#define GMAC_WOL_MTI (0x1u << 19)

/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */

#define GMAC_IPGS_FL_Pos 0

#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos)

#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)))

/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */

#define GMAC_SVLAN_VLAN_TYPE_Pos 0

#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos)

#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)))

#define GMAC_SVLAN_ESVLAN (0x1u << 31)

/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */

#define GMAC_TPFCP_PEV_Pos 0

#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos)

#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)))

#define GMAC_TPFCP_PQ_Pos 8

#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos)

#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)))

/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */

#define GMAC_SAMB1_ADDR_Pos 0

#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos)

#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)))

/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */

#define GMAC_SAMT1_ADDR_Pos 0

#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos)

#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)))

/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */

#define GMAC_NSC_NANOSEC_Pos 0

#define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos)

#define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos)))

/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */

#define GMAC_SCL_SEC_Pos 0

#define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos)

#define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos)))

/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */

#define GMAC_SCH_SEC_Pos 0

#define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos)

#define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos)))

/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */

#define GMAC_EFTSH_RUD_Pos 0

#define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos)

/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */

#define GMAC_EFRSH_RUD_Pos 0

#define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos)

/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */

#define GMAC_PEFTSH_RUD_Pos 0

#define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos)

/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */

#define GMAC_PEFRSH_RUD_Pos 0

#define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos)

/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */

#define GMAC_OTLO_TXO_Pos 0

#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos)

/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */

#define GMAC_OTHI_TXO_Pos 0

#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos)

/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */

#define GMAC_FT_FTX_Pos 0

#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos)

/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */

#define GMAC_BCFT_BFTX_Pos 0

#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos)

/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */

#define GMAC_MFT_MFTX_Pos 0

#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos)

/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */

#define GMAC_PFT_PFTX_Pos 0

#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos)

/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */

#define GMAC_BFT64_NFTX_Pos 0

#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos)

/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */

#define GMAC_TBFT127_NFTX_Pos 0

#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos)

/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */

#define GMAC_TBFT255_NFTX_Pos 0

#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos)

/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */

#define GMAC_TBFT511_NFTX_Pos 0

#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos)

/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */

#define GMAC_TBFT1023_NFTX_Pos 0

#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos)

/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */

#define GMAC_TBFT1518_NFTX_Pos 0

#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos)

/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */

#define GMAC_GTBFT1518_NFTX_Pos 0

#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos)

/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */

#define GMAC_TUR_TXUNR_Pos 0

#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos)

/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */

#define GMAC_SCF_SCOL_Pos 0

#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos)

/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */

#define GMAC_MCF_MCOL_Pos 0

#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos)

/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */

#define GMAC_EC_XCOL_Pos 0

#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos)

/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */

#define GMAC_LC_LCOL_Pos 0

#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos)

/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */

#define GMAC_DTF_DEFT_Pos 0

#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos)

/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */

#define GMAC_CSE_CSR_Pos 0

#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos)

/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */

#define GMAC_ORLO_RXO_Pos 0

#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos)

/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */

#define GMAC_ORHI_RXO_Pos 0

#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos)

/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */

#define GMAC_FR_FRX_Pos 0

#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos)

/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */

#define GMAC_BCFR_BFRX_Pos 0

#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos)

/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */

#define GMAC_MFR_MFRX_Pos 0

#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos)

/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */

#define GMAC_PFR_PFRX_Pos 0

#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos)

/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */

#define GMAC_BFR64_NFRX_Pos 0

#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos)

/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */

#define GMAC_TBFR127_NFRX_Pos 0

#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos)

/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */

#define GMAC_TBFR255_NFRX_Pos 0

#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos)

/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */

#define GMAC_TBFR511_NFRX_Pos 0

#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos)

/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */

#define GMAC_TBFR1023_NFRX_Pos 0

#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos)

/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */

#define GMAC_TBFR1518_NFRX_Pos 0

#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos)

/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */

#define GMAC_TMXBFR_NFRX_Pos 0

#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos)

/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */

#define GMAC_UFR_UFRX_Pos 0

#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos)

/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */

#define GMAC_OFR_OFRX_Pos 0

#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos)

/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */

#define GMAC_JR_JRX_Pos 0

#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos)

/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */

#define GMAC_FCSE_FCKR_Pos 0

#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos)

/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */

#define GMAC_LFFE_LFER_Pos 0

#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos)

/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */

#define GMAC_RSE_RXSE_Pos 0

#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos)

/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */

#define GMAC_AE_AER_Pos 0

#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos)

/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */

#define GMAC_RRE_RXRER_Pos 0

#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos)

/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */

#define GMAC_ROE_RXOVR_Pos 0

#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos)

/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */

#define GMAC_IHCE_HCKER_Pos 0

#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos)

/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */

#define GMAC_TCE_TCKER_Pos 0

#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos)

/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */

#define GMAC_UCE_UCKER_Pos 0

#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos)

/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */

#define GMAC_TISUBN_LSBTIR_Pos 0

#define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos)

#define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos)))

/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */

#define GMAC_TSH_TCS_Pos 0

#define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos)

#define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos)))

/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */

#define GMAC_TSL_TCS_Pos 0

#define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos)

#define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos)))

/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */

#define GMAC_TN_TNS_Pos 0

#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos)

#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)))

/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */

#define GMAC_TA_ITDT_Pos 0

#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos)

#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)))

#define GMAC_TA_ADJ (0x1u << 31)

/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */

#define GMAC_TI_CNS_Pos 0

#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos)

#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)))

#define GMAC_TI_ACNS_Pos 8

#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos)

#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)))

#define GMAC_TI_NIT_Pos 16

#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos)

#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)))

/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */

#define GMAC_EFTSL_RUD_Pos 0

#define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos)

/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */

#define GMAC_EFTN_RUD_Pos 0

#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos)

/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */

#define GMAC_EFRSL_RUD_Pos 0

#define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos)

/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */

#define GMAC_EFRN_RUD_Pos 0

#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos)

/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */

#define GMAC_PEFTSL_RUD_Pos 0

#define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos)

/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */

#define GMAC_PEFTN_RUD_Pos 0

#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos)

/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */

#define GMAC_PEFRSL_RUD_Pos 0

#define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos)

/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */

#define GMAC_PEFRN_RUD_Pos 0

#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos)

/* -------- GMAC_ISRPQ[2] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue  (index = 1) -------- */

#define GMAC_ISRPQ_RCOMP (0x1u << 1)

#define GMAC_ISRPQ_RXUBR (0x1u << 2)

#define GMAC_ISRPQ_RLEX (0x1u << 5)

#define GMAC_ISRPQ_TFC (0x1u << 6)

#define GMAC_ISRPQ_TCOMP (0x1u << 7)

#define GMAC_ISRPQ_ROVR (0x1u << 10)

#define GMAC_ISRPQ_HRESP (0x1u << 11)

/* -------- GMAC_TBQBAPQ[2] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue  (index = 1) -------- */

#define GMAC_TBQBAPQ_TXBQBA_Pos 2

#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos)

#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)))

/* -------- GMAC_RBQBAPQ[2] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue  (index = 1) -------- */

#define GMAC_RBQBAPQ_RXBQBA_Pos 2

#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos)

#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)))

/* -------- GMAC_RBSRPQ[2] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue  (index = 1) -------- */

#define GMAC_RBSRPQ_RBS_Pos 0

#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos)

#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)))

/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */

#define GMAC_CBSCR_QBE (0x1u << 0)

#define GMAC_CBSCR_QAE (0x1u << 1)

/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */

#define GMAC_CBSISQA_IS_Pos 0

#define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos)

#define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos)))

/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */

#define GMAC_CBSISQB_IS_Pos 0

#define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos)

#define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos)))

/* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue  (index = 0) -------- */

#define GMAC_ST1RPQ_QNB_Pos 0

#define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos)

#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)))

#define GMAC_ST1RPQ_DSTCM_Pos 4

#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos)

#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)))

#define GMAC_ST1RPQ_UDPM_Pos 12

#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos)

#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)))

#define GMAC_ST1RPQ_DSTCE (0x1u << 28)

#define GMAC_ST1RPQ_UDPE (0x1u << 29)

/* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue  (index = 0) -------- */

#define GMAC_ST2RPQ_QNB_Pos 0

#define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos)

#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)))

#define GMAC_ST2RPQ_VLANP_Pos 4

#define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos)

#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)))

#define GMAC_ST2RPQ_VLANE (0x1u << 8)

#define GMAC_ST2RPQ_I2ETH_Pos 9

#define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos)

#define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos)))

#define GMAC_ST2RPQ_ETHE (0x1u << 12)

#define GMAC_ST2RPQ_COMPA_Pos 13

#define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos)

#define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos)))

#define GMAC_ST2RPQ_COMPAE (0x1u << 18)

#define GMAC_ST2RPQ_COMPB_Pos 19

#define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos)

#define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos)))

#define GMAC_ST2RPQ_COMPBE (0x1u << 24)

#define GMAC_ST2RPQ_COMPC_Pos 25

#define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos)

#define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos)))

#define GMAC_ST2RPQ_COMPCE (0x1u << 30)

/* -------- GMAC_IERPQ[2] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue  (index = 1) -------- */

#define GMAC_IERPQ_RCOMP (0x1u << 1)

#define GMAC_IERPQ_RXUBR (0x1u << 2)

#define GMAC_IERPQ_RLEX (0x1u << 5)

#define GMAC_IERPQ_TFC (0x1u << 6)

#define GMAC_IERPQ_TCOMP (0x1u << 7)

#define GMAC_IERPQ_ROVR (0x1u << 10)

#define GMAC_IERPQ_HRESP (0x1u << 11)

/* -------- GMAC_IDRPQ[2] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue  (index = 1) -------- */

#define GMAC_IDRPQ_RCOMP (0x1u << 1)

#define GMAC_IDRPQ_RXUBR (0x1u << 2)

#define GMAC_IDRPQ_RLEX (0x1u << 5)

#define GMAC_IDRPQ_TFC (0x1u << 6)

#define GMAC_IDRPQ_TCOMP (0x1u << 7)

#define GMAC_IDRPQ_ROVR (0x1u << 10)

#define GMAC_IDRPQ_HRESP (0x1u << 11)

/* -------- GMAC_IMRPQ[2] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue  (index = 1) -------- */

#define GMAC_IMRPQ_RCOMP (0x1u << 1)

#define GMAC_IMRPQ_RXUBR (0x1u << 2)

#define GMAC_IMRPQ_RLEX (0x1u << 5)

#define GMAC_IMRPQ_AHB (0x1u << 6)

#define GMAC_IMRPQ_TCOMP (0x1u << 7)

#define GMAC_IMRPQ_ROVR (0x1u << 10)

#define GMAC_IMRPQ_HRESP (0x1u << 11)

/* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register  (index = 0) -------- */

#define GMAC_ST2ER_COMPVAL_Pos 0

#define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos)

#define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos)))

/* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) Screening Type 2 Compare Word 0 Register  (index = 0) -------- */

#define GMAC_ST2CW00_MASKVAL_Pos 0

#define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos)

#define GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos)))

#define GMAC_ST2CW00_COMPVAL_Pos 16

#define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos)

#define GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos)))

/* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) Screening Type 2 Compare Word 1 Register  (index = 0) -------- */

#define GMAC_ST2CW10_OFFSVAL_Pos 0

#define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos)

#define GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos)))

#define GMAC_ST2CW10_OFFSSTRT_Pos 7

#define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos)

#define GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos)))

#define   GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) Screening Type 2 Compare Word 0 Register  (index = 1) -------- */

#define GMAC_ST2CW01_MASKVAL_Pos 0

#define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos)

#define GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos)))

#define GMAC_ST2CW01_COMPVAL_Pos 16

#define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos)

#define GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos)))

/* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70C) Screening Type 2 Compare Word 1 Register  (index = 1) -------- */

#define GMAC_ST2CW11_OFFSVAL_Pos 0

#define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos)

#define GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos)))

#define GMAC_ST2CW11_OFFSSTRT_Pos 7

#define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos)

#define GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos)))

#define   GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) Screening Type 2 Compare Word 0 Register  (index = 2) -------- */

#define GMAC_ST2CW02_MASKVAL_Pos 0

#define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos)

#define GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos)))

#define GMAC_ST2CW02_COMPVAL_Pos 16

#define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos)

#define GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos)))

/* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) Screening Type 2 Compare Word 1 Register  (index = 2) -------- */

#define GMAC_ST2CW12_OFFSVAL_Pos 0

#define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos)

#define GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos)))

#define GMAC_ST2CW12_OFFSSTRT_Pos 7

#define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos)

#define GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos)))

#define   GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) Screening Type 2 Compare Word 0 Register  (index = 3) -------- */

#define GMAC_ST2CW03_MASKVAL_Pos 0

#define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos)

#define GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos)))

#define GMAC_ST2CW03_COMPVAL_Pos 16

#define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos)

#define GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos)))

/* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71C) Screening Type 2 Compare Word 1 Register  (index = 3) -------- */

#define GMAC_ST2CW13_OFFSVAL_Pos 0

#define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos)

#define GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos)))

#define GMAC_ST2CW13_OFFSSTRT_Pos 7

#define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos)

#define GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos)))

#define   GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) Screening Type 2 Compare Word 0 Register  (index = 4) -------- */

#define GMAC_ST2CW04_MASKVAL_Pos 0

#define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos)

#define GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos)))

#define GMAC_ST2CW04_COMPVAL_Pos 16

#define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos)

#define GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos)))

/* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) Screening Type 2 Compare Word 1 Register  (index = 4) -------- */

#define GMAC_ST2CW14_OFFSVAL_Pos 0

#define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos)

#define GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos)))

#define GMAC_ST2CW14_OFFSSTRT_Pos 7

#define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos)

#define GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos)))

#define   GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) Screening Type 2 Compare Word 0 Register  (index = 5) -------- */

#define GMAC_ST2CW05_MASKVAL_Pos 0

#define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos)

#define GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos)))

#define GMAC_ST2CW05_COMPVAL_Pos 16

#define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos)

#define GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos)))

/* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72C) Screening Type 2 Compare Word 1 Register  (index = 5) -------- */

#define GMAC_ST2CW15_OFFSVAL_Pos 0

#define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos)

#define GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos)))

#define GMAC_ST2CW15_OFFSSTRT_Pos 7

#define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos)

#define GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos)))

#define   GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) Screening Type 2 Compare Word 0 Register  (index = 6) -------- */

#define GMAC_ST2CW06_MASKVAL_Pos 0

#define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos)

#define GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos)))

#define GMAC_ST2CW06_COMPVAL_Pos 16

#define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos)

#define GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos)))

/* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) Screening Type 2 Compare Word 1 Register  (index = 6) -------- */

#define GMAC_ST2CW16_OFFSVAL_Pos 0

#define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos)

#define GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos)))

#define GMAC_ST2CW16_OFFSSTRT_Pos 7

#define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos)

#define GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos)))

#define   GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) Screening Type 2 Compare Word 0 Register  (index = 7) -------- */

#define GMAC_ST2CW07_MASKVAL_Pos 0

#define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos)

#define GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos)))

#define GMAC_ST2CW07_COMPVAL_Pos 16

#define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos)

#define GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos)))

/* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73C) Screening Type 2 Compare Word 1 Register  (index = 7) -------- */

#define GMAC_ST2CW17_OFFSVAL_Pos 0

#define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos)

#define GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos)))

#define GMAC_ST2CW17_OFFSSTRT_Pos 7

#define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos)

#define GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos)))

#define   GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) Screening Type 2 Compare Word 0 Register  (index = 8) -------- */

#define GMAC_ST2CW08_MASKVAL_Pos 0

#define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos)

#define GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos)))

#define GMAC_ST2CW08_COMPVAL_Pos 16

#define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos)

#define GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos)))

/* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) Screening Type 2 Compare Word 1 Register  (index = 8) -------- */

#define GMAC_ST2CW18_OFFSVAL_Pos 0

#define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos)

#define GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos)))

#define GMAC_ST2CW18_OFFSSTRT_Pos 7

#define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos)

#define GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos)))

#define   GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) Screening Type 2 Compare Word 0 Register  (index = 9) -------- */

#define GMAC_ST2CW09_MASKVAL_Pos 0

#define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos)

#define GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos)))

#define GMAC_ST2CW09_COMPVAL_Pos 16

#define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos)

#define GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos)))

/* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74C) Screening Type 2 Compare Word 1 Register  (index = 9) -------- */

#define GMAC_ST2CW19_OFFSVAL_Pos 0

#define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos)

#define GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos)))

#define GMAC_ST2CW19_OFFSSTRT_Pos 7

#define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos)

#define GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos)))

#define   GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) Screening Type 2 Compare Word 0 Register  (index = 10) -------- */

#define GMAC_ST2CW010_MASKVAL_Pos 0

#define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos)

#define GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos)))

#define GMAC_ST2CW010_COMPVAL_Pos 16

#define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos)

#define GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos)))

/* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) Screening Type 2 Compare Word 1 Register  (index = 10) -------- */

#define GMAC_ST2CW110_OFFSVAL_Pos 0

#define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos)

#define GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos)))

#define GMAC_ST2CW110_OFFSSTRT_Pos 7

#define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos)

#define GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos)))

#define   GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) Screening Type 2 Compare Word 0 Register  (index = 11) -------- */

#define GMAC_ST2CW011_MASKVAL_Pos 0

#define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos)

#define GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos)))

#define GMAC_ST2CW011_COMPVAL_Pos 16

#define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos)

#define GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos)))

/* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75C) Screening Type 2 Compare Word 1 Register  (index = 11) -------- */

#define GMAC_ST2CW111_OFFSVAL_Pos 0

#define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos)

#define GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos)))

#define GMAC_ST2CW111_OFFSSTRT_Pos 7

#define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos)

#define GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos)))

#define   GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) Screening Type 2 Compare Word 0 Register  (index = 12) -------- */

#define GMAC_ST2CW012_MASKVAL_Pos 0

#define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos)

#define GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos)))

#define GMAC_ST2CW012_COMPVAL_Pos 16

#define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos)

#define GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos)))

/* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) Screening Type 2 Compare Word 1 Register  (index = 12) -------- */

#define GMAC_ST2CW112_OFFSVAL_Pos 0

#define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos)

#define GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos)))

#define GMAC_ST2CW112_OFFSSTRT_Pos 7

#define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos)

#define GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos)))

#define   GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) Screening Type 2 Compare Word 0 Register  (index = 13) -------- */

#define GMAC_ST2CW013_MASKVAL_Pos 0

#define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos)

#define GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos)))

#define GMAC_ST2CW013_COMPVAL_Pos 16

#define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos)

#define GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos)))

/* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76C) Screening Type 2 Compare Word 1 Register  (index = 13) -------- */

#define GMAC_ST2CW113_OFFSVAL_Pos 0

#define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos)

#define GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos)))

#define GMAC_ST2CW113_OFFSSTRT_Pos 7

#define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos)

#define GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos)))

#define   GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) Screening Type 2 Compare Word 0 Register  (index = 14) -------- */

#define GMAC_ST2CW014_MASKVAL_Pos 0

#define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos)

#define GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos)))

#define GMAC_ST2CW014_COMPVAL_Pos 16

#define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos)

#define GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos)))

/* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) Screening Type 2 Compare Word 1 Register  (index = 14) -------- */

#define GMAC_ST2CW114_OFFSVAL_Pos 0

#define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos)

#define GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos)))

#define GMAC_ST2CW114_OFFSSTRT_Pos 7

#define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos)

#define GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos)))

#define   GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) Screening Type 2 Compare Word 0 Register  (index = 15) -------- */

#define GMAC_ST2CW015_MASKVAL_Pos 0

#define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos)

#define GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos)))

#define GMAC_ST2CW015_COMPVAL_Pos 16

#define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos)

#define GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos)))

/* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77C) Screening Type 2 Compare Word 1 Register  (index = 15) -------- */

#define GMAC_ST2CW115_OFFSVAL_Pos 0

#define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos)

#define GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos)))

#define GMAC_ST2CW115_OFFSSTRT_Pos 7

#define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos)

#define GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos)))

#define   GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) Screening Type 2 Compare Word 0 Register  (index = 16) -------- */

#define GMAC_ST2CW016_MASKVAL_Pos 0

#define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos)

#define GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos)))

#define GMAC_ST2CW016_COMPVAL_Pos 16

#define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos)

#define GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos)))

/* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) Screening Type 2 Compare Word 1 Register  (index = 16) -------- */

#define GMAC_ST2CW116_OFFSVAL_Pos 0

#define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos)

#define GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos)))

#define GMAC_ST2CW116_OFFSSTRT_Pos 7

#define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos)

#define GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos)))

#define   GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) Screening Type 2 Compare Word 0 Register  (index = 17) -------- */

#define GMAC_ST2CW017_MASKVAL_Pos 0

#define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos)

#define GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos)))

#define GMAC_ST2CW017_COMPVAL_Pos 16

#define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos)

#define GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos)))

/* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78C) Screening Type 2 Compare Word 1 Register  (index = 17) -------- */

#define GMAC_ST2CW117_OFFSVAL_Pos 0

#define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos)

#define GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos)))

#define GMAC_ST2CW117_OFFSSTRT_Pos 7

#define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos)

#define GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos)))

#define   GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) Screening Type 2 Compare Word 0 Register  (index = 18) -------- */

#define GMAC_ST2CW018_MASKVAL_Pos 0

#define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos)

#define GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos)))

#define GMAC_ST2CW018_COMPVAL_Pos 16

#define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos)

#define GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos)))

/* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) Screening Type 2 Compare Word 1 Register  (index = 18) -------- */

#define GMAC_ST2CW118_OFFSVAL_Pos 0

#define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos)

#define GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos)))

#define GMAC_ST2CW118_OFFSSTRT_Pos 7

#define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos)

#define GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos)))

#define   GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) Screening Type 2 Compare Word 0 Register  (index = 19) -------- */

#define GMAC_ST2CW019_MASKVAL_Pos 0

#define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos)

#define GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos)))

#define GMAC_ST2CW019_COMPVAL_Pos 16

#define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos)

#define GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos)))

/* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79C) Screening Type 2 Compare Word 1 Register  (index = 19) -------- */

#define GMAC_ST2CW119_OFFSVAL_Pos 0

#define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos)

#define GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos)))

#define GMAC_ST2CW119_OFFSSTRT_Pos 7

#define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos)

#define GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos)))

#define   GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7A0) Screening Type 2 Compare Word 0 Register  (index = 20) -------- */

#define GMAC_ST2CW020_MASKVAL_Pos 0

#define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos)

#define GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos)))

#define GMAC_ST2CW020_COMPVAL_Pos 16

#define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos)

#define GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos)))

/* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7A4) Screening Type 2 Compare Word 1 Register  (index = 20) -------- */

#define GMAC_ST2CW120_OFFSVAL_Pos 0

#define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos)

#define GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos)))

#define GMAC_ST2CW120_OFFSSTRT_Pos 7

#define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos)

#define GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos)))

#define   GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7A8) Screening Type 2 Compare Word 0 Register  (index = 21) -------- */

#define GMAC_ST2CW021_MASKVAL_Pos 0

#define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos)

#define GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos)))

#define GMAC_ST2CW021_COMPVAL_Pos 16

#define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos)

#define GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos)))

/* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7AC) Screening Type 2 Compare Word 1 Register  (index = 21) -------- */

#define GMAC_ST2CW121_OFFSVAL_Pos 0

#define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos)

#define GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos)))

#define GMAC_ST2CW121_OFFSSTRT_Pos 7

#define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos)

#define GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos)))

#define   GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7B0) Screening Type 2 Compare Word 0 Register  (index = 22) -------- */

#define GMAC_ST2CW022_MASKVAL_Pos 0

#define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos)

#define GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos)))

#define GMAC_ST2CW022_COMPVAL_Pos 16

#define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos)

#define GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos)))

/* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7B4) Screening Type 2 Compare Word 1 Register  (index = 22) -------- */

#define GMAC_ST2CW122_OFFSVAL_Pos 0

#define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos)

#define GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos)))

#define GMAC_ST2CW122_OFFSSTRT_Pos 7

#define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos)

#define GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos)))

#define   GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7)

/* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7B8) Screening Type 2 Compare Word 0 Register  (index = 23) -------- */

#define GMAC_ST2CW023_MASKVAL_Pos 0

#define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos)

#define GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos)))

#define GMAC_ST2CW023_COMPVAL_Pos 16

#define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos)

#define GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos)))

/* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7BC) Screening Type 2 Compare Word 1 Register  (index = 23) -------- */

#define GMAC_ST2CW123_OFFSVAL_Pos 0

#define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos)

#define GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos)))

#define GMAC_ST2CW123_OFFSSTRT_Pos 7

#define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos)

#define GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos)))

#define   GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7)

#define   GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7)

#define   GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7)

#define   GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7)


#endif /* _SAME70_GMAC_COMPONENT_ */

__O
#define __O
Definition: core_cm7.h:286

__IO
#define __IO
Definition: core_cm7.h:287

__I
#define __I
Definition: core_cm7.h:284

GmacSa
GmacSa hardware registers.
Definition: component_gmac.h:41

GmacSa::GMAC_SAT
__IO uint32_t GMAC_SAT
(GmacSa Offset: 0x4) Specific Address 1 Top Register
Definition: component_gmac.h:43

GmacSa::GMAC_SAB
__IO uint32_t GMAC_SAB
(GmacSa Offset: 0x0) Specific Address 1 Bottom Register
Definition: component_gmac.h:42

GmacSt2Compare
GmacSt2Compare hardware registers.
Definition: component_gmac.h:47

GmacSt2Compare::GMAC_ST2COM0
__IO uint32_t GMAC_ST2COM0
31:16 - Compare Value. 15:0 - Mask Value.
Definition: component_gmac.h:48

GmacSt2Compare::GMAC_ST2COM1
__IO uint32_t GMAC_ST2COM1
31:9 - Reserved; 8:7 - Offset location in frame; 6:0 Offset value in bytes
Definition: component_gmac.h:49

Gmac
Definition: component_gmac.h:55

Gmac::GMAC_SAMT1
__IO uint32_t GMAC_SAMT1
(Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register
Definition: component_gmac.h:88

Gmac::GMAC_NSR
__I uint32_t GMAC_NSR
(Gmac Offset: 0x008) Network Status Register
Definition: component_gmac.h:58

Gmac::GMAC_MCF
__I uint32_t GMAC_MCF
(Gmac Offset: 0x13C) Multiple Collision Frames Register
Definition: component_gmac.h:113

Gmac::GMAC_ORHI
__I uint32_t GMAC_ORHI
(Gmac Offset: 0x154) Octets Received High Received Register
Definition: component_gmac.h:119

Gmac::GMAC_PEFTSL
__I uint32_t GMAC_PEFTSL
(Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register
Definition: component_gmac.h:155

Gmac::GMAC_BCFR
__I uint32_t GMAC_BCFR
(Gmac Offset: 0x15C) Broadcast Frames Received Register
Definition: component_gmac.h:121

Gmac::GMAC_EC
__I uint32_t GMAC_EC
(Gmac Offset: 0x140) Excessive Collisions Register
Definition: component_gmac.h:114

Gmac::GMAC_IPGS
__IO uint32_t GMAC_IPGS
(Gmac Offset: 0x0BC) IPG Stretch Register
Definition: component_gmac.h:84

Gmac::GMAC_TIDM2
__IO uint32_t GMAC_TIDM2
(Gmac Offset: 0x0AC) Type ID Match 2 Register
Definition: component_gmac.h:80

Gmac::GMAC_PFT
__I uint32_t GMAC_PFT
(Gmac Offset: 0x114) Pause Frames Transmitted Register
Definition: component_gmac.h:103

Gmac::GMAC_JR
__I uint32_t GMAC_JR
(Gmac Offset: 0x18C) Jabbers Received Register
Definition: component_gmac.h:133

Gmac::GMAC_CBSISQA
__IO uint32_t GMAC_CBSISQA
(Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A
Definition: component_gmac.h:169

Gmac::GMAC_EFRSL
__I uint32_t GMAC_EFRSL
(Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register
Definition: component_gmac.h:153

Gmac::GMAC_BFR64
__I uint32_t GMAC_BFR64
(Gmac Offset: 0x168) 64 Byte Frames Received Register
Definition: component_gmac.h:124

Gmac::GMAC_TBFT1518
__I uint32_t GMAC_TBFT1518
(Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register
Definition: component_gmac.h:109

Gmac::GMAC_SCL
__IO uint32_t GMAC_SCL
(Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register
Definition: component_gmac.h:91

Gmac::GMAC_EFRSH
__I uint32_t GMAC_EFRSH
(Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register
Definition: component_gmac.h:94

Gmac::GMAC_TBFR127
__I uint32_t GMAC_TBFR127
(Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register
Definition: component_gmac.h:125

Gmac::GMAC_TBFR1023
__I uint32_t GMAC_TBFR1023
(Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register
Definition: component_gmac.h:128

Gmac::GMAC_TBFT127
__I uint32_t GMAC_TBFT127
(Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register
Definition: component_gmac.h:105

Gmac::GMAC_TSL
__IO uint32_t GMAC_TSL
(Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register
Definition: component_gmac.h:147

Gmac::GMAC_TSH
__IO uint32_t GMAC_TSH
(Gmac Offset: 0x1C0) 1588 Timer Seconds High Register
Definition: component_gmac.h:145

Gmac::GMAC_PEFTN
__I uint32_t GMAC_PEFTN
(Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register
Definition: component_gmac.h:156

Gmac::GMAC_IHCE
__I uint32_t GMAC_IHCE
(Gmac Offset: 0x1A8) IP Header Checksum Errors Register
Definition: component_gmac.h:140

Gmac::GMAC_PEFRSH
__I uint32_t GMAC_PEFRSH
(Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register
Definition: component_gmac.h:96

Gmac::GMAC_IER
__O uint32_t GMAC_IER
(Gmac Offset: 0x028) Interrupt Enable Register
Definition: component_gmac.h:66

Gmac::GMAC_WOL
__IO uint32_t GMAC_WOL
(Gmac Offset: 0x0B8) Wake on LAN Register
Definition: component_gmac.h:83

Gmac::GMAC_TBFT511
__I uint32_t GMAC_TBFT511
(Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register
Definition: component_gmac.h:107

Gmac::GMAC_UFR
__I uint32_t GMAC_UFR
(Gmac Offset: 0x184) Undersize Frames Received Register
Definition: component_gmac.h:131

Gmac::GMAC_HRB
__IO uint32_t GMAC_HRB
(Gmac Offset: 0x080) Hash Register Bottom
Definition: component_gmac.h:76

Gmac::GMAC_MAN
__IO uint32_t GMAC_MAN
(Gmac Offset: 0x034) PHY Maintenance Register
Definition: component_gmac.h:69

Gmac::GMAC_UR
__IO uint32_t GMAC_UR
(Gmac Offset: 0x00C) User Register
Definition: component_gmac.h:59

Gmac::GMAC_TMXBFR
__I uint32_t GMAC_TMXBFR
(Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register
Definition: component_gmac.h:130

Gmac::GMAC_TI
__IO uint32_t GMAC_TI
(Gmac Offset: 0x1DC) 1588 Timer Increment Register
Definition: component_gmac.h:150

Gmac::GMAC_CSE
__I uint32_t GMAC_CSE
(Gmac Offset: 0x14C) Carrier Sense Errors Register
Definition: component_gmac.h:117

Gmac::GMAC_BFT64
__I uint32_t GMAC_BFT64
(Gmac Offset: 0x118) 64 Byte Frames Transmitted Register
Definition: component_gmac.h:104

Gmac::GMAC_BCFT
__I uint32_t GMAC_BCFT
(Gmac Offset: 0x10C) Broadcast Frames Transmitted Register
Definition: component_gmac.h:101

Gmac::GMAC_SCH
__IO uint32_t GMAC_SCH
(Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register
Definition: component_gmac.h:92

Gmac::GMAC_RRE
__I uint32_t GMAC_RRE
(Gmac Offset: 0x1A0) Receive Resource Errors Register
Definition: component_gmac.h:138

Gmac::GMAC_MFR
__I uint32_t GMAC_MFR
(Gmac Offset: 0x160) Multicast Frames Received Register
Definition: component_gmac.h:122

Gmac::GMAC_RJFML
__IO uint32_t GMAC_RJFML
(Gmac Offset: 0x048) RX Jumbo Frame Max Length Register
Definition: component_gmac.h:74

Gmac::GMAC_EFTSH
__I uint32_t GMAC_EFTSH
(Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register
Definition: component_gmac.h:93

Gmac::GMAC_TBFR1518
__I uint32_t GMAC_TBFR1518
(Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register
Definition: component_gmac.h:129

Gmac::GMAC_HRT
__IO uint32_t GMAC_HRT
(Gmac Offset: 0x084) Hash Register Top
Definition: component_gmac.h:77

Gmac::GMAC_TCE
__I uint32_t GMAC_TCE
(Gmac Offset: 0x1AC) TCP Checksum Errors Register
Definition: component_gmac.h:141

Gmac::GMAC_NSC
__IO uint32_t GMAC_NSC
(Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register
Definition: component_gmac.h:90

Gmac::GMAC_FR
__I uint32_t GMAC_FR
(Gmac Offset: 0x158) Frames Received Register
Definition: component_gmac.h:120

Gmac::GMAC_TBFT255
__I uint32_t GMAC_TBFT255
(Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register
Definition: component_gmac.h:106

Gmac::GMAC_OTLO
__I uint32_t GMAC_OTLO
(Gmac Offset: 0x100) Octets Transmitted Low Register
Definition: component_gmac.h:98

Gmac::GMAC_PEFRSL
__I uint32_t GMAC_PEFRSL
(Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register
Definition: component_gmac.h:157

Gmac::GMAC_TIDM3
__IO uint32_t GMAC_TIDM3
(Gmac Offset: 0x0B0) Type ID Match 3 Register
Definition: component_gmac.h:81

Gmac::GMAC_SVLAN
__IO uint32_t GMAC_SVLAN
(Gmac Offset: 0x0C0) Stacked VLAN Register
Definition: component_gmac.h:85

Gmac::GMAC_NCFGR
__IO uint32_t GMAC_NCFGR
(Gmac Offset: 0x004) Network Configuration Register
Definition: component_gmac.h:57

Gmac::GMAC_RSE
__I uint32_t GMAC_RSE
(Gmac Offset: 0x198) Receive Symbol Errors Register
Definition: component_gmac.h:136

Gmac::GMAC_TN
__IO uint32_t GMAC_TN
(Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register
Definition: component_gmac.h:148

Gmac::GMAC_TISUBN
__IO uint32_t GMAC_TISUBN
(Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register
Definition: component_gmac.h:144

Gmac::GMAC_EFRN
__I uint32_t GMAC_EFRN
(Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register
Definition: component_gmac.h:154

Gmac::GMAC_TSR
__IO uint32_t GMAC_TSR
(Gmac Offset: 0x014) Transmit Status Register
Definition: component_gmac.h:61

Gmac::GMAC_ISR
__I uint32_t GMAC_ISR
(Gmac Offset: 0x024) Interrupt Status Register
Definition: component_gmac.h:65

Gmac::GMAC_FCSE
__I uint32_t GMAC_FCSE
(Gmac Offset: 0x190) Frame Check Sequence Errors Register
Definition: component_gmac.h:134

Gmac::GMAC_DTF
__I uint32_t GMAC_DTF
(Gmac Offset: 0x148) Deferred Transmission Frames Register
Definition: component_gmac.h:116

Gmac::GMAC_RBQB
__IO uint32_t GMAC_RBQB
(Gmac Offset: 0x018) Receive Buffer Queue Base Address Register
Definition: component_gmac.h:62

Gmac::GMAC_EFTN
__I uint32_t GMAC_EFTN
(Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register
Definition: component_gmac.h:152

Gmac::GMAC_DCFGR
__IO uint32_t GMAC_DCFGR
(Gmac Offset: 0x010) DMA Configuration Register
Definition: component_gmac.h:60

Gmac::GMAC_TPSF
__IO uint32_t GMAC_TPSF
(Gmac Offset: 0x040) TX Partial Store and Forward Register
Definition: component_gmac.h:72

Gmac::GMAC_TBFT1023
__I uint32_t GMAC_TBFT1023
(Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register
Definition: component_gmac.h:108

Gmac::GMAC_TBFR511
__I uint32_t GMAC_TBFR511
(Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register
Definition: component_gmac.h:127

Gmac::GMAC_OFR
__I uint32_t GMAC_OFR
(Gmac Offset: 0x188) Oversize Frames Received Register
Definition: component_gmac.h:132

Gmac::GMAC_ROE
__I uint32_t GMAC_ROE
(Gmac Offset: 0x1A4) Receive Overrun Register
Definition: component_gmac.h:139

Gmac::GMAC_CBSISQB
__IO uint32_t GMAC_CBSISQB
(Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B
Definition: component_gmac.h:170

Gmac::GMAC_FT
__I uint32_t GMAC_FT
(Gmac Offset: 0x108) Frames Transmitted Register
Definition: component_gmac.h:100

Gmac::GMAC_PFR
__I uint32_t GMAC_PFR
(Gmac Offset: 0x164) Pause Frames Received Register
Definition: component_gmac.h:123

Gmac::GMAC_TPFCP
__IO uint32_t GMAC_TPFCP
(Gmac Offset: 0x0C4) Transmit PFC Pause Register
Definition: component_gmac.h:86

Gmac::GMAC_SAMB1
__IO uint32_t GMAC_SAMB1
(Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register
Definition: component_gmac.h:87

Gmac::GMAC_RPSF
__IO uint32_t GMAC_RPSF
(Gmac Offset: 0x044) RX Partial Store and Forward Register
Definition: component_gmac.h:73

Gmac::GMAC_TBFR255
__I uint32_t GMAC_TBFR255
(Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register
Definition: component_gmac.h:126

Gmac::GMAC_OTHI
__I uint32_t GMAC_OTHI
(Gmac Offset: 0x104) Octets Transmitted High Register
Definition: component_gmac.h:99

Gmac::GMAC_CBSCR
__IO uint32_t GMAC_CBSCR
(Gmac Offset: 0x4BC) Credit-Based Shaping Control Register
Definition: component_gmac.h:168

Gmac::GMAC_EFTSL
__I uint32_t GMAC_EFTSL
(Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register
Definition: component_gmac.h:151

Gmac::GMAC_LFFE
__I uint32_t GMAC_LFFE
(Gmac Offset: 0x194) Length Field Frame Errors Register
Definition: component_gmac.h:135

Gmac::GMAC_PEFRN
__I uint32_t GMAC_PEFRN
(Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register
Definition: component_gmac.h:158

Gmac::GMAC_GTBFT1518
__I uint32_t GMAC_GTBFT1518
(Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register
Definition: component_gmac.h:110

Gmac::GMAC_TUR
__I uint32_t GMAC_TUR
(Gmac Offset: 0x134) Transmit Underruns Register
Definition: component_gmac.h:111

Gmac::GMAC_TBQB
__IO uint32_t GMAC_TBQB
(Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register
Definition: component_gmac.h:63

Gmac::GMAC_PEFTSH
__I uint32_t GMAC_PEFTSH
(Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register
Definition: component_gmac.h:95

Gmac::GMAC_RSR
__IO uint32_t GMAC_RSR
(Gmac Offset: 0x020) Receive Status Register
Definition: component_gmac.h:64

Gmac::GMAC_TPQ
__IO uint32_t GMAC_TPQ
(Gmac Offset: 0x03C) Transmit Pause Quantum Register
Definition: component_gmac.h:71

Gmac::GMAC_TIDM4
__IO uint32_t GMAC_TIDM4
(Gmac Offset: 0x0B4) Type ID Match 4 Register
Definition: component_gmac.h:82

Gmac::GMAC_AE
__I uint32_t GMAC_AE
(Gmac Offset: 0x19C) Alignment Errors Register
Definition: component_gmac.h:137

Gmac::GMAC_RPQ
__I uint32_t GMAC_RPQ
(Gmac Offset: 0x038) Received Pause Quantum Register
Definition: component_gmac.h:70

Gmac::GMAC_UCE
__I uint32_t GMAC_UCE
(Gmac Offset: 0x1B0) UDP Checksum Errors Register
Definition: component_gmac.h:142

Gmac::GMAC_SCF
__I uint32_t GMAC_SCF
(Gmac Offset: 0x138) Single Collision Frames Register
Definition: component_gmac.h:112

Gmac::GMAC_TIDM1
__IO uint32_t GMAC_TIDM1
(Gmac Offset: 0x0A8) Type ID Match 1 Register
Definition: component_gmac.h:79

Gmac::GMAC_IMR
__IO uint32_t GMAC_IMR
(Gmac Offset: 0x030) Interrupt Mask Register
Definition: component_gmac.h:68

Gmac::GMAC_TA
__O uint32_t GMAC_TA
(Gmac Offset: 0x1D8) 1588 Timer Adjust Register
Definition: component_gmac.h:149

Gmac::GMAC_IDR
__O uint32_t GMAC_IDR
(Gmac Offset: 0x02C) Interrupt Disable Register
Definition: component_gmac.h:67

Gmac::GMAC_MFT
__I uint32_t GMAC_MFT
(Gmac Offset: 0x110) Multicast Frames Transmitted Register
Definition: component_gmac.h:102

Gmac::GMAC_LC
__I uint32_t GMAC_LC
(Gmac Offset: 0x144) Late Collisions Register
Definition: component_gmac.h:115

Gmac::GMAC_NCR
__IO uint32_t GMAC_NCR
(Gmac Offset: 0x000) Network Control Register
Definition: component_gmac.h:56

Gmac::GMAC_ORLO
__I uint32_t GMAC_ORLO
(Gmac Offset: 0x150) Octets Received Low Received Register
Definition: component_gmac.h:118