component_efc.h

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#ifndef _SAME70_EFC_COMPONENT_
#define _SAME70_EFC_COMPONENT_
 
/* ============================================================================= */
/* ============================================================================= */
 
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
  __IO uint32_t EEFC_FMR;      
  __O  uint32_t EEFC_FCR;      
  __I  uint32_t EEFC_FSR;      
  __I  uint32_t EEFC_FRR;      
  __I  uint32_t Reserved1[53];
  __IO uint32_t EEFC_WPMR;     
} Efc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
#define EEFC_FMR_FRDY (0x1u << 0) 
#define EEFC_FMR_FWS_Pos 8
#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) 
#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
#define EEFC_FMR_SCOD (0x1u << 16) 
#define EEFC_FMR_CLOE (0x1u << 26) 
/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
#define EEFC_FCR_FCMD_Pos 0
#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) 
#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
#define   EEFC_FCR_FCMD_GETD (0x0u << 0) 
#define   EEFC_FCR_FCMD_WP (0x1u << 0) 
#define   EEFC_FCR_FCMD_WPL (0x2u << 0) 
#define   EEFC_FCR_FCMD_EWP (0x3u << 0) 
#define   EEFC_FCR_FCMD_EWPL (0x4u << 0) 
#define   EEFC_FCR_FCMD_EA (0x5u << 0) 
#define   EEFC_FCR_FCMD_EPA (0x7u << 0) 
#define   EEFC_FCR_FCMD_SLB (0x8u << 0) 
#define   EEFC_FCR_FCMD_CLB (0x9u << 0) 
#define   EEFC_FCR_FCMD_GLB (0xAu << 0) 
#define   EEFC_FCR_FCMD_SGPB (0xBu << 0) 
#define   EEFC_FCR_FCMD_CGPB (0xCu << 0) 
#define   EEFC_FCR_FCMD_GGPB (0xDu << 0) 
#define   EEFC_FCR_FCMD_STUI (0xEu << 0) 
#define   EEFC_FCR_FCMD_SPUI (0xFu << 0) 
#define   EEFC_FCR_FCMD_GCALB (0x10u << 0) 
#define   EEFC_FCR_FCMD_ES (0x11u << 0) 
#define   EEFC_FCR_FCMD_WUS (0x12u << 0) 
#define   EEFC_FCR_FCMD_EUS (0x13u << 0) 
#define   EEFC_FCR_FCMD_STUS (0x14u << 0) 
#define   EEFC_FCR_FCMD_SPUS (0x15u << 0) 
#define EEFC_FCR_FARG_Pos 8
#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) 
#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
#define EEFC_FCR_FKEY_Pos 24
#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) 
#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
#define   EEFC_FCR_FKEY_PASSWD (0x5Au << 24) 
/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
#define EEFC_FSR_FRDY (0x1u << 0) 
#define EEFC_FSR_FCMDE (0x1u << 1) 
#define EEFC_FSR_FLOCKE (0x1u << 2) 
#define EEFC_FSR_FLERR (0x1u << 3) 
#define EEFC_FSR_UECCELSB (0x1u << 16) 
#define EEFC_FSR_MECCELSB (0x1u << 17) 
#define EEFC_FSR_UECCEMSB (0x1u << 18) 
#define EEFC_FSR_MECCEMSB (0x1u << 19) 
/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
#define EEFC_FRR_FVALUE_Pos 0
#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) 
/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */
#define EEFC_WPMR_WPEN (0x1u << 0) 
#define EEFC_WPMR_WPKEY_Pos 8
#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) 
#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos)))
#define   EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) 
 
 
#endif /* _SAME70_EFC_COMPONENT_ */