component_dacc.h

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#ifndef _SAME70_DACC_COMPONENT_
#define _SAME70_DACC_COMPONENT_
 
/* ============================================================================= */
/* ============================================================================= */
 
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
  __O  uint32_t DACC_CR;       
  __IO uint32_t DACC_MR;       
  __IO uint32_t DACC_TRIGR;    
  __I  uint32_t Reserved1[1];
  __O  uint32_t DACC_CHER;     
  __O  uint32_t DACC_CHDR;     
  __I  uint32_t DACC_CHSR;     
  __O  uint32_t DACC_CDR[2];   
  __O  uint32_t DACC_IER;      
  __O  uint32_t DACC_IDR;      
  __I  uint32_t DACC_IMR;      
  __I  uint32_t DACC_ISR;      
  __I  uint32_t Reserved2[24];
  __IO uint32_t DACC_ACR;      
  __I  uint32_t Reserved3[19];
  __IO uint32_t DACC_WPMR;     
  __I  uint32_t DACC_WPSR;     
} Dacc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
#define DACC_CR_SWRST (0x1u << 0) 
/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
#define DACC_MR_MAXS0 (0x1u << 0) 
#define   DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) 
#define   DACC_MR_MAXS0_MAXIMUM (0x1u << 0) 
#define DACC_MR_MAXS1 (0x1u << 1) 
#define   DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) 
#define   DACC_MR_MAXS1_MAXIMUM (0x1u << 1) 
#define DACC_MR_WORD (0x1u << 4) 
#define   DACC_MR_WORD_DISABLED (0x0u << 4) 
#define   DACC_MR_WORD_ENABLED (0x1u << 4) 
#define DACC_MR_ZERO (0x1u << 5) 
#define DACC_MR_DIFF (0x1u << 23) 
#define   DACC_MR_DIFF_DISABLED (0x0u << 23) 
#define   DACC_MR_DIFF_ENABLED (0x1u << 23) 
#define DACC_MR_PRESCALER_Pos 24
#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) 
#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)))
/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */
#define DACC_TRIGR_TRGEN0 (0x1u << 0) 
#define   DACC_TRIGR_TRGEN0_DIS (0x0u << 0) 
#define   DACC_TRIGR_TRGEN0_EN (0x1u << 0) 
#define DACC_TRIGR_TRGEN1 (0x1u << 1) 
#define   DACC_TRIGR_TRGEN1_DIS (0x0u << 1) 
#define   DACC_TRIGR_TRGEN1_EN (0x1u << 1) 
#define DACC_TRIGR_TRGSEL0_Pos 4
#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) 
#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos)))
#define   DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) 
#define   DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) 
#define   DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) 
#define   DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) 
#define   DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) 
#define   DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) 
#define   DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) 
#define DACC_TRIGR_TRGSEL1_Pos 8
#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) 
#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos)))
#define   DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) 
#define   DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) 
#define   DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) 
#define   DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) 
#define   DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) 
#define   DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) 
#define   DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) 
#define DACC_TRIGR_OSR0_Pos 16
#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) 
#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos)))
#define   DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) 
#define   DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) 
#define   DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) 
#define   DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) 
#define   DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) 
#define   DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) 
#define DACC_TRIGR_OSR1_Pos 20
#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) 
#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos)))
#define   DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) 
#define   DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) 
#define   DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) 
#define   DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) 
#define   DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) 
#define   DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) 
/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
#define DACC_CHER_CH0 (0x1u << 0) 
#define DACC_CHER_CH1 (0x1u << 1) 
/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
#define DACC_CHDR_CH0 (0x1u << 0) 
#define DACC_CHDR_CH1 (0x1u << 1) 
/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
#define DACC_CHSR_CH0 (0x1u << 0) 
#define DACC_CHSR_CH1 (0x1u << 1) 
#define DACC_CHSR_DACRDY0 (0x1u << 8) 
#define DACC_CHSR_DACRDY1 (0x1u << 9) 
/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */
#define DACC_CDR_DATA0_Pos 0
#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) 
#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)))
#define DACC_CDR_DATA1_Pos 16
#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) 
#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)))
/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
#define DACC_IER_TXRDY0 (0x1u << 0) 
#define DACC_IER_TXRDY1 (0x1u << 1) 
#define DACC_IER_EOC0 (0x1u << 4) 
#define DACC_IER_EOC1 (0x1u << 5) 
/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
#define DACC_IDR_TXRDY0 (0x1u << 0) 
#define DACC_IDR_TXRDY1 (0x1u << 1) 
#define DACC_IDR_EOC0 (0x1u << 4) 
#define DACC_IDR_EOC1 (0x1u << 5) 
/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
#define DACC_IMR_TXRDY0 (0x1u << 0) 
#define DACC_IMR_TXRDY1 (0x1u << 1) 
#define DACC_IMR_EOC0 (0x1u << 4) 
#define DACC_IMR_EOC1 (0x1u << 5) 
/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
#define DACC_ISR_TXRDY0 (0x1u << 0) 
#define DACC_ISR_TXRDY1 (0x1u << 1) 
#define DACC_ISR_EOC0 (0x1u << 4) 
#define DACC_ISR_EOC1 (0x1u << 5) 
/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
#define DACC_ACR_IBCTLCH0_Pos 0
#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) 
#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
#define DACC_ACR_IBCTLCH1_Pos 2
#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) 
#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode Register -------- */
#define DACC_WPMR_WPEN (0x1u << 0) 
#define DACC_WPMR_WPKEY_Pos 8
#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) 
#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
#define   DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) 
/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status Register -------- */
#define DACC_WPSR_WPVS (0x1u << 0) 
#define DACC_WPSR_WPVSRC_Pos 8
#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) 
 
 
#endif /* _SAME70_DACC_COMPONENT_ */