RTEMS 5.2
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reg_stc.h
1/* The header file is generated by make_header.py from STC.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
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38*/
39#ifndef LIBBSP_ARM_TMS570_STC
40#define LIBBSP_ARM_TMS570_STC
41
42#include <bsp/utility.h>
43
44typedef struct{
45 uint32_t STCGCR0; /*STC Global Control Register 0*/
46 uint32_t STCGCR1; /*STCGlobal Control Register 1*/
47 uint32_t STCTPR; /*Self-Test Run Timeout Counter Preload Register*/
48 uint32_t STC_CADDR; /*STC Current ROM Address Register*/
49 uint32_t STCCICR; /*STC Current Interval Count Register*/
50 uint32_t STCGSTAT; /*Self-Test Global Status Register*/
51 uint32_t STCFSTAT; /*Self-Test Fail Status Register*/
52 uint32_t CPU1_CURMISR3; /*CPU1 Current MISR Register 3*/
53 uint32_t CPU1_CURMISR2; /*CPU1 Current MISR Register 2*/
54 uint32_t CPU1_CURMISR1; /*CPU1 Current MISR Register 1*/
55 uint32_t CPU1_CURMISR0; /*CPU1 Current MISR Register 0*/
56 uint32_t CPU2_CURMISR3; /*CPU2 Current MISR Register 3*/
57 uint32_t CPU2_CURMISR2; /*CPU2 Current MISR Register 2*/
58 uint32_t CPU2_CURMISR1; /*CPU2 Current MISR Register 1*/
59 uint32_t CPU2_CURMISR0; /*CPU2 Current MISR Register 0*/
60 uint32_t STCSCSCR; /*Signature Compare Self-Check Register*/
61} tms570_stc_t;
62
63
64/*---------------------TMS570_STC_STCGCR0---------------------*/
65/* field: INTCOUNT - Number of intervals of self-test run */
66#define TMS570_STC_STCGCR0_INTCOUNT(val) BSP_FLD32(val,16, 31)
67#define TMS570_STC_STCGCR0_INTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 31)
68#define TMS570_STC_STCGCR0_INTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
69
70/* field: RS_CNT - Restart or Continue */
71#define TMS570_STC_STCGCR0_RS_CNT BSP_BIT32(0)
72
73
74/*---------------------TMS570_STC_STCGCR1---------------------*/
75/* field: STC_ENA - Self-test run enable key */
76#define TMS570_STC_STCGCR1_STC_ENA(val) BSP_FLD32(val,0, 3)
77#define TMS570_STC_STCGCR1_STC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
78#define TMS570_STC_STCGCR1_STC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
79
80
81/*---------------------TMS570_STC_STCTPR---------------------*/
82/* field: RTOD - Self-test timeout count preload */
83/* Whole 32 bits */
84
85/*--------------------TMS570_STC_STC_CADDR--------------------*/
86/* field: ADDR - Current ROM Address */
87/* Whole 32 bits */
88
89/*---------------------TMS570_STC_STCCICR---------------------*/
90/* field: N - Interval Number */
91#define TMS570_STC_STCCICR_N(val) BSP_FLD32(val,0, 15)
92#define TMS570_STC_STCCICR_N_GET(reg) BSP_FLD32GET(reg,0, 15)
93#define TMS570_STC_STCCICR_N_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
94
95
96/*--------------------TMS570_STC_STCGSTAT--------------------*/
97/* field: TEST_FAIL - Test Fail */
98#define TMS570_STC_STCGSTAT_TEST_FAIL BSP_BIT32(1)
99
100/* field: TEST_DONE - Test Done */
101#define TMS570_STC_STCGSTAT_TEST_DONE BSP_BIT32(0)
102
103
104/*--------------------TMS570_STC_STCFSTAT--------------------*/
105/* field: TO_ERR - Timeout Error */
106#define TMS570_STC_STCFSTAT_TO_ERR BSP_BIT32(2)
107
108/* field: CPU2_FAIL - CPU2 failure info */
109#define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_BIT32(1)
110
111/* field: CPU1_FAIL - CPU1 failure info */
112#define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_BIT32(0)
113
114
115/*------------------TMS570_STC_CPU1_CURMISR3------------------*/
116/* field: MISR - MISR data from CPU1 */
117/* Whole 32 bits */
118
119/*------------------TMS570_STC_CPU1_CURMISR2------------------*/
120/* field: MISR - MISR data from CPU1 */
121/* Whole 32 bits */
122
123/*------------------TMS570_STC_CPU1_CURMISR1------------------*/
124/* field: MISR - MISR data from CPU1 */
125/* Whole 32 bits */
126
127/*------------------TMS570_STC_CPU1_CURMISR0------------------*/
128/* field: MISR - MISR data from CPU1 */
129/* Whole 32 bits */
130
131/*------------------TMS570_STC_CPU2_CURMISR3------------------*/
132/* field: MISR - MISR data from CPU2 */
133/* Whole 32 bits */
134
135/*------------------TMS570_STC_CPU2_CURMISR2------------------*/
136/* field: MISR - MISR data from CPU2 */
137/* Whole 32 bits */
138
139/*------------------TMS570_STC_CPU2_CURMISR1------------------*/
140/* field: MISR - MISR data from CPU2 */
141/* Whole 32 bits */
142
143/*------------------TMS570_STC_CPU2_CURMISR0------------------*/
144/* field: MISR - MISR data from CPU2 */
145/* Whole 32 bits */
146
147/*--------------------TMS570_STC_STCSCSCR--------------------*/
148/* field: FAULT_INS - Enable / Disable fault insertion. */
149#define TMS570_STC_STCSCSCR_FAULT_INS BSP_BIT32(4)
150
151/* field: SELF_CHECK_KEY - Signature compare logic self-check enable key */
152#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY(val) BSP_FLD32(val,0, 3)
153#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
154#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
155
156
157
158#endif /* LIBBSP_ARM_TMS570_STC */
utility.h
Utility macros.
tms570_stc_t
Definition: reg_stc.h:44
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