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reg_dcc.h
1/* The header file is generated by make_header.py from DCC.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 * list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 * this list of conditions and the following disclaimer in the documentation
22 * and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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35 * The views and conclusions contained in the software and documentation are those
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37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_TMS570_DCC
40#define LIBBSP_ARM_TMS570_DCC
41
42#include <bsp/utility.h>
43
44typedef struct{
45 uint32_t GCTRL; /*DCC Global Control Register*/
46 uint32_t REV; /*DCC Revision Id Register*/
47 uint32_t CNT0SEED; /*DCC Counter0 Seed Register*/
48 uint32_t VALID0SEED; /*DCC Valid0 Seed Register*/
49 uint32_t CNT1SEED; /*DCC Counter1 Seed Register*/
50 uint32_t STAT; /*DCC Status Register*/
51 uint32_t CNT0; /*DCC Counter0 Value Register*/
52 uint32_t VALID0; /*DCC Valid0 Value Register*/
53 uint32_t CNT1; /*DCC Counter1 Value Register*/
54 uint32_t CNT1CLKSRC; /*DCC Counter1 Clock Source Selection Register*/
55 uint32_t CNT0CLKSRC; /*DCC Counter0 Clock Source Selection Register*/
56} tms570_dcc_t;
57
58
59/*----------------------TMS570_DCC_GCTRL----------------------*/
60/* field: DONE_INT_ENA - Done Interrupt Enable. */
61#define TMS570_DCC_GCTRL_DONE_INT_ENA(val) BSP_FLD32(val,12, 15)
62#define TMS570_DCC_GCTRL_DONE_INT_ENA_GET(reg) BSP_FLD32GET(reg,12, 15)
63#define TMS570_DCC_GCTRL_DONE_INT_ENA_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
64
65/* field: SINGLE_SHOT - Single-Shot Mode Enable. */
66#define TMS570_DCC_GCTRL_SINGLE_SHOT(val) BSP_FLD32(val,8, 11)
67#define TMS570_DCC_GCTRL_SINGLE_SHOT_GET(reg) BSP_FLD32GET(reg,8, 11)
68#define TMS570_DCC_GCTRL_SINGLE_SHOT_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
69
70/* field: ERR_ENA - Error Interrupt Enable. */
71#define TMS570_DCC_GCTRL_ERR_ENA(val) BSP_FLD32(val,4, 7)
72#define TMS570_DCC_GCTRL_ERR_ENA_GET(reg) BSP_FLD32GET(reg,4, 7)
73#define TMS570_DCC_GCTRL_ERR_ENA_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
74
75/* field: DCC_ENA - DCC Enable. */
76#define TMS570_DCC_GCTRL_DCC_ENA(val) BSP_FLD32(val,0, 3)
77#define TMS570_DCC_GCTRL_DCC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
78#define TMS570_DCC_GCTRL_DCC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
79
80
81/*-----------------------TMS570_DCC_REV-----------------------*/
82/* field: SCHEME - Reads return 01, writes have no effect. */
83#define TMS570_DCC_REV_SCHEME(val) BSP_FLD32(val,30, 31)
84#define TMS570_DCC_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
85#define TMS570_DCC_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31)
86
87/* field: FUNC - Functional release number. Reads return 0x000, writes have no effect. */
88#define TMS570_DCC_REV_FUNC(val) BSP_FLD32(val,16, 27)
89#define TMS570_DCC_REV_FUNC_GET(reg) BSP_FLD32GET(reg,16, 27)
90#define TMS570_DCC_REV_FUNC_SET(reg,val) BSP_FLD32SET(reg, val,16, 27)
91
92/* field: RTL - Design release number. Reads return 0x00, writes have no effect. */
93#define TMS570_DCC_REV_RTL(val) BSP_FLD32(val,11, 15)
94#define TMS570_DCC_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15)
95#define TMS570_DCC_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15)
96
97/* field: MAJOR - Major revision number. Reads return 0x2, writes have no effect. */
98#define TMS570_DCC_REV_MAJOR(val) BSP_FLD32(val,8, 10)
99#define TMS570_DCC_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10)
100#define TMS570_DCC_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
101
102/* field: CUSTOM - Custom version number. Reads return 0x0, writes have no effect. */
103#define TMS570_DCC_REV_CUSTOM(val) BSP_FLD32(val,6, 7)
104#define TMS570_DCC_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7)
105#define TMS570_DCC_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
106
107/* field: MINOR - Minor revision number. Reads return 0x4, writes have no effect. */
108#define TMS570_DCC_REV_MINOR(val) BSP_FLD32(val,0, 5)
109#define TMS570_DCC_REV_MINOR_GET(reg) BSP_FLD32GET(reg,0, 5)
110#define TMS570_DCC_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
111
112
113/*--------------------TMS570_DCC_CNT0SEED--------------------*/
114/* field: COUNT0_SEED - Seed value for DCC Counter0. */
115#define TMS570_DCC_CNT0SEED_COUNT0_SEED(val) BSP_FLD32(val,0, 19)
116#define TMS570_DCC_CNT0SEED_COUNT0_SEED_GET(reg) BSP_FLD32GET(reg,0, 19)
117#define TMS570_DCC_CNT0SEED_COUNT0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
118
119
120/*-------------------TMS570_DCC_VALID0SEED-------------------*/
121/* field: VALID0_SEED - XXX */
122#define TMS570_DCC_VALID0SEED_VALID0_SEED(val) BSP_FLD32(val,0, 15)
123#define TMS570_DCC_VALID0SEED_VALID0_SEED_GET(reg) BSP_FLD32GET(reg,0, 15)
124#define TMS570_DCC_VALID0SEED_VALID0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
125
126
127/*--------------------TMS570_DCC_CNT1SEED--------------------*/
128/* field: COUNT1_SEED - Seed value for DCC Counter1. */
129#define TMS570_DCC_CNT1SEED_COUNT1_SEED(val) BSP_FLD32(val,0, 19)
130#define TMS570_DCC_CNT1SEED_COUNT1_SEED_GET(reg) BSP_FLD32GET(reg,0, 19)
131#define TMS570_DCC_CNT1SEED_COUNT1_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
132
133
134/*----------------------TMS570_DCC_STAT----------------------*/
135/* field: DONE_FLG - Single-Shot Sequence Done flag. */
136#define TMS570_DCC_STAT_DONE_FLG BSP_BIT32(1)
137
138/* field: ERR_FLG - Error flag. Indicates that a DCC error has occurred. */
139#define TMS570_DCC_STAT_ERR_FLG BSP_BIT32(0)
140
141
142/*----------------------TMS570_DCC_CNT0----------------------*/
143/* field: COUNT0 - Current value of DCC Counter0. */
144#define TMS570_DCC_CNT0_COUNT0(val) BSP_FLD32(val,0, 19)
145#define TMS570_DCC_CNT0_COUNT0_GET(reg) BSP_FLD32GET(reg,0, 19)
146#define TMS570_DCC_CNT0_COUNT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
147
148
149/*---------------------TMS570_DCC_VALID0---------------------*/
150/* field: VALID0 - Current value for DCC Valid0. */
151#define TMS570_DCC_VALID0_VALID0(val) BSP_FLD32(val,0, 15)
152#define TMS570_DCC_VALID0_VALID0_GET(reg) BSP_FLD32GET(reg,0, 15)
153#define TMS570_DCC_VALID0_VALID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
154
155
156/*----------------------TMS570_DCC_CNT1----------------------*/
157/* field: COUNT1 - Current value for DCC Counter1. */
158#define TMS570_DCC_CNT1_COUNT1(val) BSP_FLD32(val,0, 19)
159#define TMS570_DCC_CNT1_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19)
160#define TMS570_DCC_CNT1_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
161
162
163/*-------------------TMS570_DCC_CNT1CLKSRC-------------------*/
164/* field: KEY - Key to enable clock source selection for Counter1. */
165#define TMS570_DCC_CNT1CLKSRC_KEY(val) BSP_FLD32(val,12, 15)
166#define TMS570_DCC_CNT1CLKSRC_KEY_GET(reg) BSP_FLD32GET(reg,12, 15)
167#define TMS570_DCC_CNT1CLKSRC_KEY_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
168
169/* field: CNT1_CLKSRC - Clock Source for Counter1 when KEY is programmed to be 0xA. */
170#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC(val) BSP_FLD32(val,0, 3)
171#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
172#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
173
174
175/*-------------------TMS570_DCC_CNT0CLKSRC-------------------*/
176/* field: CNT0_CLKSRC - Clock Source for Counter0 */
177#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC(val) BSP_FLD32(val,0, 3)
178#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
179#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
180
181
182
183#endif /* LIBBSP_ARM_TMS570_DCC */
utility.h
Utility macros.
STAT
Definition: dd.h:66
tms570_dcc_t
Definition: reg_dcc.h:44
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