RTEMS 5.2
regs.h
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1
10/*
11 * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved.
12 *
13 * embedded brains GmbH
14 * Dornierstr. 4
15 * 82178 Puchheim
16 * Germany
17 * <rtems@embedded-brains.de>
18 *
19 * The license and distribution terms for this file may be
20 * found in the file LICENSE in this distribution or at
21 * http://www.rtems.org/license/LICENSE.
22 */
23
24#ifndef LIBCPU_POWERPC_MPC55XX_REGS_H
25#define LIBCPU_POWERPC_MPC55XX_REGS_H
26
27#include <bspopts.h>
28
29#if MPC55XX_CHIP_FAMILY == 551
30 #include <mpc55xx/fsl-mpc551x.h>
31 #define MPC55XX_HAS_EBI
32 #define MPC55XX_HAS_ESCI
33 #define MPC55XX_HAS_EMIOS
34 #define MPC55XX_HAS_FMPLL_ENHANCED
35 #define MPC55XX_HAS_SIU
36#elif MPC55XX_CHIP_FAMILY == 555
37 #include <mpc55xx/fsl-mpc555x.h>
38 #define MPC55XX_HAS_EBI
39 #define MPC55XX_HAS_ESCI
40 #define MPC55XX_HAS_EMIOS
41 #define MPC55XX_HAS_FMPLL
42 #define MPC55XX_HAS_UNIFIED_CACHE
43 #define MPC55XX_HAS_SIU
44#elif MPC55XX_CHIP_FAMILY == 556
45 #include <mpc55xx/fsl-mpc556x.h>
46 #define MPC55XX_HAS_EBI
47 #define MPC55XX_HAS_ESCI
48 #define MPC55XX_HAS_EMIOS
49 #define MPC55XX_HAS_FMPLL
50 #define MPC55XX_HAS_UNIFIED_CACHE
51 #define MPC55XX_HAS_SIU
52#elif MPC55XX_CHIP_FAMILY == 564
53 #include <mpc55xx/fsl-mpc564xL.h>
54 #define MPC55XX_HAS_STM
55 #define MPC55XX_HAS_SWT
56 #define MPC55XX_HAS_MODE_CONTROL
57 #define MPC55XX_HAS_INSTRUCTION_CACHE
58 #define MPC55XX_HAS_LINFLEX
59 #define MPC55XX_HAS_SECOND_INTERNAL_RAM_AREA
60 #define MPC55XX_HAS_SIU_LITE
61#elif MPC55XX_CHIP_FAMILY == 566
62 #include <mpc55xx/fsl-mpc5668.h>
63 #define MPC55XX_HAS_ESCI
64 #define MPC55XX_HAS_EMIOS
65 #define MPC55XX_HAS_FMPLL_ENHANCED
66 #define MPC55XX_HAS_UNIFIED_CACHE
67 #define MPC55XX_HAS_SIU
68 /*
69 * TODO: This e200z650n3e core has a wait instruction, but it did not wake-up
70 * from PIT interrupts.
71 */
72#elif MPC55XX_CHIP_FAMILY == 567
73 #include <mpc55xx/fsl-mpc567x.h>
74 #define MPC55XX_HAS_EBI
75 #define MPC55XX_HAS_ESCI
76 #define MPC55XX_HAS_EMIOS
77 #define MPC55XX_HAS_FMPLL_ENHANCED
78 #define MPC55XX_HAS_INSTRUCTION_CACHE
79 #define MPC55XX_HAS_DATA_CACHE
80 #define MPC55XX_HAS_SIU
81 #define MPC55XX_HAS_WAIT_INSTRUCTION
82#else
83 #error "unsupported chip type"
84#endif
85
86#define MPC55XX_ZERO_FLAGS { .R = 0 }
87
88#endif /* LIBCPU_POWERPC_MPC55XX_REGS_H */