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cpuimpl.h
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1
7/*
8 * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
9 * Canon Centre Recherche France.
10 *
11 * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
12 *
13 * Copyright (c) 2009, 2017 embedded brains GmbH
14 *
15 * The license and distribution terms for this file may be
16 * found in the file LICENSE in this distribution or at
17 * http://www.rtems.org/license/LICENSE.
18 */
19
20#ifndef _RTEMS_SCORE_CPUIMPL_H
21#define _RTEMS_SCORE_CPUIMPL_H
22
23#include <rtems/score/cpu.h>
24
35/* Exception stack frame -> BSP_Exception_frame */
36#ifdef __powerpc64__
37 #define FRAME_LINK_SPACE 32
38#else
39 #define FRAME_LINK_SPACE 8
40#endif
41
42#define SRR0_FRAME_OFFSET FRAME_LINK_SPACE
43#define SRR1_FRAME_OFFSET (SRR0_FRAME_OFFSET + PPC_REG_SIZE)
44#define EXCEPTION_NUMBER_OFFSET (SRR1_FRAME_OFFSET + PPC_REG_SIZE)
45#define PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET (EXCEPTION_NUMBER_OFFSET + 4)
46#define EXC_CR_OFFSET (EXCEPTION_NUMBER_OFFSET + 8)
47#define EXC_XER_OFFSET (EXC_CR_OFFSET + 4)
48#define EXC_CTR_OFFSET (EXC_XER_OFFSET + 4)
49#define EXC_LR_OFFSET (EXC_CTR_OFFSET + PPC_REG_SIZE)
50#define PPC_EXC_INTERRUPT_FRAME_OFFSET (EXC_LR_OFFSET + PPC_REG_SIZE)
51
52#ifndef __SPE__
53 #define PPC_EXC_GPR_OFFSET(gpr) \
54 ((gpr) * PPC_GPR_SIZE + PPC_EXC_INTERRUPT_FRAME_OFFSET + PPC_REG_SIZE)
55 #define PPC_EXC_GPR3_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(3)
56 #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU)
57 #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33)
58 #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28)
59 #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4)
60 #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_VR_OFFSET(32))
61 #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32)
62 #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34)
63 #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12)
64 #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4)
65 #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_MIN_VR_OFFSET(20))
66 #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14)
67 #define CPU_INTERRUPT_FRAME_SIZE \
68 (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE)
69 #elif defined(PPC_MULTILIB_ALTIVEC)
70 #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33)
71 #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28)
72 #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4)
73 #define PPC_EXC_FRAME_SIZE PPC_EXC_VR_OFFSET(32)
74 #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12)
75 #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4)
76 #define CPU_INTERRUPT_FRAME_SIZE \
77 (PPC_EXC_MIN_VR_OFFSET(20) + PPC_STACK_RED_ZONE_SIZE)
78 #elif defined(PPC_MULTILIB_FPU)
79 #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(33))
80 #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32)
81 #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34)
82 #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(13))
83 #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14)
84 #define CPU_INTERRUPT_FRAME_SIZE \
85 (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE)
86 #else
87 #define PPC_EXC_FRAME_SIZE PPC_EXC_GPR_OFFSET(33)
88 #define CPU_INTERRUPT_FRAME_SIZE \
89 (PPC_EXC_GPR_OFFSET(13) + PPC_STACK_RED_ZONE_SIZE)
90 #endif
91#else
92 #define PPC_EXC_SPEFSCR_OFFSET 44
93 #define PPC_EXC_ACC_OFFSET 48
94 #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 56)
95 #define PPC_EXC_GPR3_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(3) + 4)
96 #define CPU_INTERRUPT_FRAME_SIZE (160 + PPC_STACK_RED_ZONE_SIZE)
97 #define PPC_EXC_FRAME_SIZE 320
98#endif
99
100#define GPR0_OFFSET PPC_EXC_GPR_OFFSET(0)
101#define GPR1_OFFSET PPC_EXC_GPR_OFFSET(1)
102#define GPR2_OFFSET PPC_EXC_GPR_OFFSET(2)
103#define GPR3_OFFSET PPC_EXC_GPR_OFFSET(3)
104#define GPR4_OFFSET PPC_EXC_GPR_OFFSET(4)
105#define GPR5_OFFSET PPC_EXC_GPR_OFFSET(5)
106#define GPR6_OFFSET PPC_EXC_GPR_OFFSET(6)
107#define GPR7_OFFSET PPC_EXC_GPR_OFFSET(7)
108#define GPR8_OFFSET PPC_EXC_GPR_OFFSET(8)
109#define GPR9_OFFSET PPC_EXC_GPR_OFFSET(9)
110#define GPR10_OFFSET PPC_EXC_GPR_OFFSET(10)
111#define GPR11_OFFSET PPC_EXC_GPR_OFFSET(11)
112#define GPR12_OFFSET PPC_EXC_GPR_OFFSET(12)
113#define GPR13_OFFSET PPC_EXC_GPR_OFFSET(13)
114#define GPR14_OFFSET PPC_EXC_GPR_OFFSET(14)
115#define GPR15_OFFSET PPC_EXC_GPR_OFFSET(15)
116#define GPR16_OFFSET PPC_EXC_GPR_OFFSET(16)
117#define GPR17_OFFSET PPC_EXC_GPR_OFFSET(17)
118#define GPR18_OFFSET PPC_EXC_GPR_OFFSET(18)
119#define GPR19_OFFSET PPC_EXC_GPR_OFFSET(19)
120#define GPR20_OFFSET PPC_EXC_GPR_OFFSET(20)
121#define GPR21_OFFSET PPC_EXC_GPR_OFFSET(21)
122#define GPR22_OFFSET PPC_EXC_GPR_OFFSET(22)
123#define GPR23_OFFSET PPC_EXC_GPR_OFFSET(23)
124#define GPR24_OFFSET PPC_EXC_GPR_OFFSET(24)
125#define GPR25_OFFSET PPC_EXC_GPR_OFFSET(25)
126#define GPR26_OFFSET PPC_EXC_GPR_OFFSET(26)
127#define GPR27_OFFSET PPC_EXC_GPR_OFFSET(27)
128#define GPR28_OFFSET PPC_EXC_GPR_OFFSET(28)
129#define GPR29_OFFSET PPC_EXC_GPR_OFFSET(29)
130#define GPR30_OFFSET PPC_EXC_GPR_OFFSET(30)
131#define GPR31_OFFSET PPC_EXC_GPR_OFFSET(31)
132
133#define CPU_PER_CPU_CONTROL_SIZE 0
134
135#ifdef RTEMS_SMP
136
137/* Use SPRG0 for the per-CPU control of the current processor */
138#define PPC_PER_CPU_CONTROL_REGISTER 272
139
140#endif /* RTEMS_SMP */
141
142#ifndef ASM
143
144#ifdef __cplusplus
145extern "C" {
146#endif
147
148typedef struct {
149 uintptr_t FRAME_SP;
150 #ifdef __powerpc64__
151 uint32_t FRAME_CR;
152 uint32_t FRAME_RESERVED;
153 #endif
154 uintptr_t FRAME_LR;
155 #ifdef __powerpc64__
156 uintptr_t FRAME_TOC;
157 #endif
158 uintptr_t EXC_SRR0;
159 uintptr_t EXC_SRR1;
160 uint32_t RESERVED_FOR_ALIGNMENT_0;
161 uint32_t EXC_INTERRUPT_ENTRY_INSTANT;
162 uint32_t EXC_CR;
163 uint32_t EXC_XER;
164 uintptr_t EXC_CTR;
165 uintptr_t EXC_LR;
166 uintptr_t EXC_INTERRUPT_FRAME;
167 #ifdef __SPE__
168 uint32_t EXC_SPEFSCR;
169 uint64_t EXC_ACC;
170 #endif
171 PPC_GPR_TYPE GPR0;
172 PPC_GPR_TYPE GPR1;
173 PPC_GPR_TYPE GPR2;
174 PPC_GPR_TYPE GPR3;
175 PPC_GPR_TYPE GPR4;
176 PPC_GPR_TYPE GPR5;
177 PPC_GPR_TYPE GPR6;
178 PPC_GPR_TYPE GPR7;
179 PPC_GPR_TYPE GPR8;
180 PPC_GPR_TYPE GPR9;
181 PPC_GPR_TYPE GPR10;
182 PPC_GPR_TYPE GPR11;
183 PPC_GPR_TYPE GPR12;
184 #ifdef PPC_MULTILIB_ALTIVEC
185 /* This field must take stvewx/lvewx requirements into account */
186 uint32_t RESERVED_FOR_ALIGNMENT_3[3];
187 uint32_t VSCR;
188
189 uint8_t V0[16];
190 uint8_t V1[16];
191 uint8_t V2[16];
192 uint8_t V3[16];
193 uint8_t V4[16];
194 uint8_t V5[16];
195 uint8_t V6[16];
196 uint8_t V7[16];
197 uint8_t V8[16];
198 uint8_t V9[16];
199 uint8_t V10[16];
200 uint8_t V11[16];
201 uint8_t V12[16];
202 uint8_t V13[16];
203 uint8_t V14[16];
204 uint8_t V15[16];
205 uint8_t V16[16];
206 uint8_t V17[16];
207 uint8_t V18[16];
208 uint8_t V19[16];
209 #endif
210 #ifdef PPC_MULTILIB_FPU
211 double F0;
212 double F1;
213 double F2;
214 double F3;
215 double F4;
216 double F5;
217 double F6;
218 double F7;
219 double F8;
220 double F9;
221 double F10;
222 double F11;
223 double F12;
224 double F13;
225 uint64_t FPSCR;
226 uint64_t RESERVED_FOR_ALIGNMENT_4;
227 #endif
228 #if PPC_STACK_RED_ZONE_SIZE > 0
229 uint8_t RED_ZONE[ PPC_STACK_RED_ZONE_SIZE ];
230 #endif
231} CPU_Interrupt_frame;
232
233#ifdef RTEMS_SMP
234
235static inline struct Per_CPU_Control *_PPC_Get_current_per_CPU_control( void )
236{
237 struct Per_CPU_Control *cpu_self;
238
239 __asm__ volatile (
240 "mfspr %0, " RTEMS_XSTRING( PPC_PER_CPU_CONTROL_REGISTER )
241 : "=r" ( cpu_self )
242 );
243
244 return cpu_self;
245}
246
247#define _CPU_Get_current_per_CPU_control() _PPC_Get_current_per_CPU_control()
248
249#endif /* RTEMS_SMP */
250
251void _CPU_Context_volatile_clobber( uintptr_t pattern );
252
253void _CPU_Context_validate( uintptr_t pattern );
254
255RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
256{
257 __asm__ volatile ( ".long 0" );
258}
259
260RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
261{
262 __asm__ volatile ( "nop" );
263}
264
265#ifdef __cplusplus
266}
267#endif
268
269#endif /* ASM */
270
273#endif /* _RTEMS_SCORE_CPUIMPL_H */
RTEMS_INLINE_ROUTINE
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66
RTEMS_XSTRING
#define RTEMS_XSTRING(_x)
Stringifies expansion of _x.
Definition: basedefs.h:549
_CPU_Instruction_illegal
RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal(void)
Emits an illegal instruction.
Definition: cpuimpl.h:122
_CPU_Instruction_no_operation
RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation(void)
Emits a no operation instruction (nop).
Definition: cpuimpl.h:132
__asm__
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
CPU_Interrupt_frame
Interrupt stack frame (ISF).
Definition: cpu.h:191
Per_CPU_Control
Per CPU Core Structure.
Definition: percpu.h:347
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