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mpc8xx.h
1/*
2**************************************************************************
3**************************************************************************
4** **
5** MOTOROLA MPC860/MPC821 PORTABLE SYSTEMS MICROPROCESSOR **
6** **
7** HARDWARE DECLARATIONS **
8** **
9** **
10** Submitted By: **
11** **
12** W. Eric Norum **
13** Saskatchewan Accelerator Laboratory **
14** University of Saskatchewan **
15** 107 North Road **
16** Saskatoon, Saskatchewan, CANADA **
17** S7N 5C6 **
18** **
19** eric@skatter.usask.ca **
20** **
21** Modified for use with the MPC860 (original code was for MC68360) **
22** by **
23** Jay Monkman **
24** Frasca International, Inc. **
25** 906 E. Airport Rd. **
26** Urbana, IL, 61801 **
27** **
28** jmonkman@frasca.com **
29** **
30** Modified further for use with the MPC821 by: **
31** Andrew Bray <andy@chaos.org.uk> **
32** **
33** With some corrections/additions by: **
34** Darlene A. Stewart and **
35** Charles-Antoine Gauthier **
36** Institute for Information Technology **
37** National Research Council of Canada **
38** Ottawa, ON K1A 0R6 **
39** **
40** Darlene.Stewart@iit.nrc.ca **
41** charles.gauthier@iit.nrc.ca **
42** **
43** Corrections/additions: **
44** Copyright (c) 1999, National Research Council of Canada **
45**************************************************************************
46**************************************************************************
47*/
48#ifndef _MPC8XX_H
49#define _MPC8XX_H
50
51#ifndef ASM
52
53#ifdef __cplusplus
54extern "C" {
55#endif
56
57/*
58 * Macros for accessing Special Purpose Registers (SPRs)
59 */
60#define _mtspr(_spr,_reg) __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
61#define _mfspr(_reg,_spr) __asm__ volatile ( "mfspr %0, %1\n" : "=r" ((_reg)) : "i" ((_spr)) )
62
63#define _isync __asm__ volatile ("isync\n"::)
64
65/*
66 * Core Registers (SPRs)
67 */
68#define M8xx_DEC 22 /* Decrementer Register */
69#define M8xx_DER 149 /* Debug Enable Register */
70#define M8xx_ICTRL 158 /* Instruction Support Control Register */
71#define M8xx_TBL_WR 284 /* Timebase Lower Write Register */
72#define M8xx_TBU_WR 285 /* Timebase Upper Write Register */
73#define M8xx_IMMR 638 /* Internal Memory Map Register */
74
75/*
76 * Cache Control Registers (SPRs)
77 */
78#define M8xx_IC_CST 560 /* Instruction Cache Control and Status Register */
79#define M8xx_DC_CST 568 /* Data Cache Control and Status Register */
80#define M8xx_IC_ADR 561 /* Instruction Cache Address Register */
81#define M8xx_DC_ADR 569 /* Data Cache Address Register */
82#define M8xx_IC_DAT 562 /* Instruction Cache Data Port Register */
83#define M8xx_DC_DAT 570 /* Data Cache Data Port Register */
84
85/*
86 * MMU Registers (SPRs)
87 */
88/* Control Registers */
89#define M8xx_MI_CTR 784 /* IMMU Control Register */
90#define M8xx_MD_CTR 792 /* DMMU Control Register */
91/* TLB Source Registers */
92#define M8xx_MI_EPN 787 /* IMMU Effective Page Number Register (EPN) */
93#define M8xx_MD_EPN 795 /* DMMU Effective Page Number Register (EPN) */
94#define M8xx_MI_TWC 789 /* IMMU Tablewalk Control Register (TWC) */
95#define M8xx_MD_TWC 797 /* DMMU Tablewalk Control Register (TWC) */
96#define M8xx_MI_RPN 790 /* IMMU Real (physical) Page Number Register (RPN) */
97#define M8xx_MD_RPN 798 /* DMMU Real (physical) Page Number Register (RPN) */
98/* Tablewalk Assist Registers */
99#define M8xx_M_TWB 796 /* MMU Tablewalk Base Register (TWB) */
100/* Protection Registers */
101#define M8xx_M_CASID 793 /* MMU Current Address Space ID Register */
102#define M8xx_MI_AP 786 /* IMMU Access Protection Register */
103#define M8xx_MD_AP 794 /* DMMU Access Protection Register */
104/* Scratch Register */
105#define M8xx_M_TW 799 /* MMU Tablewalk Special Register */
106/* Debug Registers */
107#define M8xx_MI_CAM 816 /* IMMU CAM Entry Read Register */
108#define M8xx_MI_RAM0 817 /* IMMU RAM Entry Read Register 0 */
109#define M8xx_MI_RAM1 818 /* IMMU RAM Entry Read Register 1 */
110#define M8xx_MD_CAM 824 /* DMMU CAM Entry Read Register */
111#define M8xx_MD_RAM0 825 /* DMMU RAM Entry Read Register 0 */
112#define M8xx_MD_RAM1 826 /* DMMU RAM Entry Read Register 1 */
113
114#define M8xx_MI_CTR_GPM (1<<31)
115#define M8xx_MI_CTR_PPM (1<<30)
116#define M8xx_MI_CTR_CIDEF (1<<29)
117#define M8xx_MI_CTR_RSV4I (1<<27)
118#define M8xx_MI_CTR_PPCS (1<<25)
119#define M8xx_MI_CTR_ITLB_INDX(x) ((x)<<8) /* ITLB index */
120
121#define M8xx_MD_CTR_GPM (1<<31)
122#define M8xx_MD_CTR_PPM (1<<30)
123#define M8xx_MD_CTR_CIDEF (1<<29)
124#define M8xx_MD_CTR_WTDEF (1<<28)
125#define M8xx_MD_CTR_RSV4D (1<<27)
126#define M8xx_MD_CTR_TWAM (1<<26)
127#define M8xx_MD_CTR_PPCS (1<<25)
128#define M8xx_MD_CTR_DTLB_INDX(x) ((x)<<8) /* DTLB index */
129
130#define M8xx_MI_EPN_VALID (1<<9)
131
132#define M8xx_MD_EPN_VALID (1<<9)
133
134#define M8xx_MI_TWC_G (1<<4)
135#define M8xx_MI_TWC_PSS (0<<2)
136#define M8xx_MI_TWC_PS512 (1<<2)
137#define M8xx_MI_TWC_PS8 (3<<2)
138#define M8xx_MI_TWC_VALID (1)
139
140#define M8xx_MD_TWC_G (1<<4)
141#define M8xx_MD_TWC_PSS (0<<2)
142#define M8xx_MD_TWC_PS512 (1<<2)
143#define M8xx_MD_TWC_PS8 (3<<2)
144#define M8xx_MD_TWC_WT (1<<1)
145#define M8xx_MD_TWC_VALID (1)
146
147#define M8xx_MI_RPN_F (0xf<<4)
148#define M8xx_MI_RPN_16K (1<<3)
149#define M8xx_MI_RPN_SHARED (1<<2)
150#define M8xx_MI_RPN_CI (1<<1)
151#define M8xx_MI_RPN_VALID (1)
152
153#define M8xx_MD_RPN_CHANGE (1<<8)
154#define M8xx_MD_RPN_F (0xf<<4)
155#define M8xx_MD_RPN_16K (1<<3)
156#define M8xx_MD_RPN_SHARED (1<<2)
157#define M8xx_MD_RPN_CI (1<<1)
158#define M8xx_MD_RPN_VALID (1)
159
160#define M8xx_MI_AP_Kp (1)
161
162#define M8xx_MD_AP_Kp (1)
163
164#define M8xx_CACHE_CMD_SFWT (0x1<<24)
165#define M8xx_CACHE_CMD_ENABLE (0x2<<24)
166#define M8xx_CACHE_CMD_CFWT (0x3<<24)
167#define M8xx_CACHE_CMD_DISABLE (0x4<<24)
168#define M8xx_CACHE_CMD_STLES (0x5<<24)
169#define M8xx_CACHE_CMD_LLCB (0x6<<24)
170#define M8xx_CACHE_CMD_CLES (0x7<<24)
171#define M8xx_CACHE_CMD_UNLOCK (0x8<<24)
172#define M8xx_CACHE_CMD_UNLOCKALL (0xa<<24)
173#define M8xx_CACHE_CMD_INVALIDATE (0xc<<24)
174#define M8xx_CACHE_CMD_FLUSH (0xe<<24)
175
176/*
177*************************************************************************
178* REGISTER SUBBLOCKS *
179*************************************************************************
180*/
181
182/*
183 * Memory controller registers
184 */
185typedef struct m8xxMEMCRegisters_ {
186 uint32_t _br;
187 uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */
188} m8xxMEMCRegisters_t;
189
190/*
191 * Serial Communications Controller registers
192 */
193typedef struct m8xxSCCRegisters_ {
194 uint32_t gsmr_l;
195 uint32_t gsmr_h;
196 uint16_t psmr;
197 uint16_t _pad0;
198 uint16_t todr;
199 uint16_t dsr;
200 uint16_t scce;
201 uint16_t _pad1;
202 uint16_t sccm;
203 uint8_t _pad2;
204 uint8_t sccs;
205 uint32_t _pad3[2];
206} m8xxSCCRegisters_t;
207
208/*
209 * Serial Management Controller registers
210 */
211typedef struct m8xxSMCRegisters_ {
212 uint16_t _pad0;
213 uint16_t smcmr;
214 uint16_t _pad1;
215 uint8_t smce;
216 uint8_t _pad2;
217 uint16_t _pad3;
218 uint8_t smcm;
219 uint8_t _pad4;
220 uint32_t _pad5;
221} m8xxSMCRegisters_t;
222
223/*
224 * Fast Ethernet Controller registers (Only on MPC8xxT)
225 */
226typedef struct m8xxFECRegisters_ {
227 uint32_t addr_low;
228 uint32_t addr_high;
229 uint32_t hash_table_high;
230 uint32_t hash_table_low;
231 uint32_t r_des_start;
232 uint32_t x_des_start;
233 uint32_t r_buf_size;
234 uint32_t _pad0[9];
235 uint32_t ecntrl;
236 uint32_t ievent;
237 uint32_t imask;
238 uint32_t ivec;
239 uint32_t r_des_active;
240 uint32_t x_des_active;
241 uint32_t _pad1[10];
242 uint32_t mii_data;
243 uint32_t mii_speed;
244 uint32_t _pad2[17];
245 uint32_t r_bound;
246 uint32_t r_fstart;
247 uint32_t _pad3[6];
248 uint32_t x_fstart;
249 uint32_t _pad4[17];
250 uint32_t fun_code;
251 uint32_t _pad5[3];
252 uint32_t r_cntrl;
253 uint32_t r_hash;
254 uint32_t _pad6[14];
255 uint32_t x_cntrl;
256 uint32_t _pad7[30];
257
258} m8xxFECRegisters_t;
259
260#define M8xx_FEC_IEVENT_HBERR (1 << 31)
261#define M8xx_FEC_IEVENT_BABR (1 << 30)
262#define M8xx_FEC_IEVENT_BABT (1 << 29)
263#define M8xx_FEC_IEVENT_GRA (1 << 28)
264#define M8xx_FEC_IEVENT_TFINT (1 << 27)
265#define M8xx_FEC_IEVENT_TXB (1 << 26)
266#define M8xx_FEC_IEVENT_RFINT (1 << 25)
267#define M8xx_FEC_IEVENT_RXB (1 << 24)
268#define M8xx_FEC_IEVENT_MII (1 << 23)
269#define M8xx_FEC_IEVENT_EBERR (1 << 22)
270#define M8xx_FEC_IMASK_HBEEN (1 << 31)
271#define M8xx_FEC_IMASK_BREEN (1 << 30)
272#define M8xx_FEC_IMASK_BTEN (1 << 29)
273#define M8xx_FEC_IMASK_GRAEN (1 << 28)
274#define M8xx_FEC_IMASK_TFIEN (1 << 27)
275#define M8xx_FEC_IMASK_TBIEN (1 << 26)
276#define M8xx_FEC_IMASK_RFIEN (1 << 25)
277#define M8xx_FEC_IMASK_RBIEN (1 << 24)
278#define M8xx_FEC_IMASK_MIIEN (1 << 23)
279#define M8xx_FEC_IMASK_EBERREN (1 << 22)
280
281 /*
282 * access macros to write to mii_data register
283 */
284#define M8xx_FEC_MII_DATA_ST ( 1 << (31- 1))
285#define M8xx_FEC_MII_DATA_OP_RD ( 2 << (31- 3))
286#define M8xx_FEC_MII_DATA_OP_WR ( 1 << (31- 3))
287#define M8xx_FEC_MII_DATA_PHYAD(n) (((n) & 0x3f) << (31- 8))
288#define M8xx_FEC_MII_DATA_PHYRA(n) (((n) & 0x3f) << (31-13))
289#define M8xx_FEC_MII_DATA_TA ( 2 << (31-15))
290#define M8xx_FEC_MII_DATA_WDATA(n) ((n) & 0xffff )
291#define M8xx_FEC_MII_DATA_RDATA(reg) ((reg) & 0xffff )
292 /*
293 * bits for FEC ECNTRL register
294 */
295#define M8xx_FEC_ECNTRL_FEC_PINMUX ( 1 << (31-29))
296#define M8xx_FEC_ECNTRL_ETHER_EN ( 1 << (31-30))
297#define M8xx_FEC_ECNTRL_RESET ( 1 << (31-31))
298
299 /*
300 * bits for FEC R_CNTRL register
301 */
302#define M8xx_FEC_R_CNTRL_BC_REJ ( 1 << (31-27))
303#define M8xx_FEC_R_CNTRL_PROM ( 1 << (31-28))
304#define M8xx_FEC_R_CNTRL_MII_MODE ( 1 << (31-29))
305#define M8xx_FEC_R_CNTRL_DRT ( 1 << (31-30))
306#define M8xx_FEC_R_CNTRL_LOOP ( 1 << (31-31))
307
308 /*
309 * bits for FEC X_CNTRL register
310 */
311#define M8xx_FEC_X_CNTRL_FDEN ( 1 << (31-29))
312#define M8xx_FEC_X_CNTRL_HBC ( 1 << (31-30))
313#define M8xx_FEC_X_CNTRL_GTS ( 1 << (31-31))
314/*
315*************************************************************************
316* Miscellaneous Parameters *
317*************************************************************************
318*/
319typedef struct m8xxMiscParms_ {
320 uint16_t rev_num;
321 uint16_t _res1;
322 uint32_t _res2;
323 uint32_t _res3;
324} m8xxMiscParms_t;
325
326/*
327*************************************************************************
328* RISC Timers *
329*************************************************************************
330*/
331typedef struct m8xxTimerParms_ {
332 uint16_t tm_base;
333 uint16_t _tm_ptr;
334 uint16_t _r_tmr;
335 uint16_t _r_tmv;
336 uint32_t tm_cmd;
337 uint32_t tm_cnt;
338} m8xxTimerParms_t;
339
340/*
341 * RISC Controller Configuration Register (RCCR)
342 * All other bits in this register are reserved.
343 */
344#define M8xx_RCCR_TIME (1<<15) /* Enable timer */
345#define M8xx_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
346#define M8xx_RCCR_DR1M (1<<7) /* IDMA Rqst 1 Mode */
347#define M8xx_RCCR_DR0M (1<<6) /* IDMA Rqst 0 Mode */
348#define M8xx_RCCR_DRQP(x) ((x)<<4) /* IDMA Rqst Priority */
349#define M8xx_RCCR_EIE (1<<3) /* External Interrupt Enable */
350#define M8xx_RCCR_SCD (1<<2) /* Scheduler Configuration */
351#define M8xx_RCCR_ERAM(x) (x) /* Enable RAM Microcode */
352
353/*
354 * Command register
355 * Set up this register before issuing a M8xx_CR_OP_SET_TIMER command.
356 */
357#define M8xx_TM_CMD_V (1<<31) /* Set to enable timer */
358#define M8xx_TM_CMD_R (1<<30) /* Set for automatic restart */
359#define M8xx_TM_CMD_PWM (1<<29) /* Set for PWM operation */
360#define M8xx_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
361#define M8xx_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
362
363/*
364*************************************************************************
365* DMA Controllers *
366*************************************************************************
367*/
368typedef struct m8xxIDMAparms_ {
369 uint16_t ibase;
370 uint16_t dcmr;
371 uint32_t _sapr;
372 uint32_t _dapr;
373 uint16_t ibptr;
374 uint16_t _write_sp;
375 uint32_t _s_byte_c;
376 uint32_t _d_byte_c;
377 uint32_t _s_state;
378 uint32_t _itemp[4];
379 uint32_t _sr_mem;
380 uint16_t _read_sp;
381 uint16_t _res0;
382 uint16_t _res1;
383 uint16_t _res2;
384 uint32_t _d_state;
385} m8xxIDMAparms_t;
386
387
388/*
389*************************************************************************
390* DSP *
391*************************************************************************
392*/
393typedef struct m8xxDSPparms_ {
394 uint32_t fdbase;
395 uint32_t _fd_ptr;
396 uint32_t _dstate;
397 uint32_t _pad0;
398 uint16_t _dstatus;
399 uint16_t _i;
400 uint16_t _tap;
401 uint16_t _cbase;
402 uint16_t _pad1;
403 uint16_t _xptr;
404 uint16_t _pad2;
405 uint16_t _yptr;
406 uint16_t _m;
407 uint16_t _pad3;
408 uint16_t _n;
409 uint16_t _pad4;
410 uint16_t _k;
411 uint16_t _pad5;
412} m8xxDSPparms_t;
413
414/*
415*************************************************************************
416* Serial Communication Controllers *
417*************************************************************************
418*/
419typedef struct m8xxSCCparms_ {
420 uint16_t rbase;
421 uint16_t tbase;
422 uint8_t rfcr;
423 uint8_t tfcr;
424 uint16_t mrblr;
425 uint32_t _rstate;
426 uint32_t _pad0;
427 uint16_t _rbptr;
428 uint16_t _pad1;
429 uint32_t _pad2;
430 uint32_t _tstate;
431 uint32_t _pad3;
432 uint16_t _tbptr;
433 uint16_t _pad4;
434 uint32_t _pad5;
435 uint32_t _rcrc;
436 uint32_t _tcrc;
437 union {
438 struct {
439 uint32_t _res0;
440 uint32_t _res1;
441 uint16_t max_idl;
442 uint16_t _idlc;
443 uint16_t brkcr;
444 uint16_t parec;
445 uint16_t frmec;
446 uint16_t nosec;
447 uint16_t brkec;
448 uint16_t brkln;
449 uint16_t uaddr[2];
450 uint16_t _rtemp;
451 uint16_t toseq;
452 uint16_t character[8];
453 uint16_t rccm;
454 uint16_t rccr;
455 uint16_t rlbc;
456 } uart;
457 } un;
458} m8xxSCCparms_t;
459
460typedef struct m8xxSCCENparms_ {
461 uint16_t rbase;
462 uint16_t tbase;
463 uint8_t rfcr;
464 uint8_t tfcr;
465 uint16_t mrblr;
466 uint32_t _rstate;
467 uint32_t _pad0;
468 uint16_t _rbptr;
469 uint16_t _pad1;
470 uint32_t _pad2;
471 uint32_t _tstate;
472 uint32_t _pad3;
473 uint16_t _tbptr;
474 uint16_t _pad4;
475 uint32_t _pad5;
476 uint32_t _rcrc;
477 uint32_t _tcrc;
478 union {
479 struct {
480 uint32_t _res0;
481 uint32_t _res1;
482 uint16_t max_idl;
483 uint16_t _idlc;
484 uint16_t brkcr;
485 uint16_t parec;
486 uint16_t frmec;
487 uint16_t nosec;
488 uint16_t brkec;
489 uint16_t brkln;
490 uint16_t uaddr[2];
491 uint16_t _rtemp;
492 uint16_t toseq;
493 uint16_t character[8];
494 uint16_t rccm;
495 uint16_t rccr;
496 uint16_t rlbc;
497 } uart;
498 struct {
499 uint32_t c_pres;
500 uint32_t c_mask;
501 uint32_t crcec;
502 uint32_t alec;
503 uint32_t disfc;
504 uint16_t pads;
505 uint16_t ret_lim;
506 uint16_t _ret_cnt;
507 uint16_t mflr;
508 uint16_t minflr;
509 uint16_t maxd1;
510 uint16_t maxd2;
511 uint16_t _maxd;
512 uint16_t dma_cnt;
513 uint16_t _max_b;
514 uint16_t gaddr1;
515 uint16_t gaddr2;
516 uint16_t gaddr3;
517 uint16_t gaddr4;
518 uint32_t _tbuf0data0;
519 uint32_t _tbuf0data1;
520 uint32_t _tbuf0rba0;
521 uint32_t _tbuf0crc;
522 uint16_t _tbuf0bcnt;
523 uint16_t paddr_h;
524 uint16_t paddr_m;
525 uint16_t paddr_l;
526 uint16_t p_per;
527 uint16_t _rfbd_ptr;
528 uint16_t _tfbd_ptr;
529 uint16_t _tlbd_ptr;
530 uint32_t _tbuf1data0;
531 uint32_t _tbuf1data1;
532 uint32_t _tbuf1rba0;
533 uint32_t _tbuf1crc;
534 uint16_t _tbuf1bcnt;
535 uint16_t _tx_len;
536 uint16_t iaddr1;
537 uint16_t iaddr2;
538 uint16_t iaddr3;
539 uint16_t iaddr4;
540 uint16_t _boff_cnt;
541 uint16_t taddr_m;
542 uint16_t taddr_l;
543 uint16_t taddr_h;
544 } ethernet;
545 } un;
546} m8xxSCCENparms_t;
547
548/*
549 * Receive and transmit function code register bits
550 * These apply to the function code registers of all devices, not just SCC.
551 */
552#define M8xx_RFCR_BO(x) ((x)<<3)
553#define M8xx_RFCR_MOT (2<<3)
554#define M8xx_RFCR_DMA_SPACE(x) (x)
555#define M8xx_TFCR_BO(x) ((x)<<3)
556#define M8xx_TFCR_MOT (2<<3)
557#define M8xx_TFCR_DMA_SPACE(x) (x)
558
559/*
560 * Event and mask registers (SCCE, SCCM)
561 */
562#define M8xx_SCCE_BRKE (1<<6)
563#define M8xx_SCCE_BRK (1<<4)
564#define M8xx_SCCE_BSY (1<<2)
565#define M8xx_SCCE_TX (1<<1)
566#define M8xx_SCCE_RX (1<<0)
567
568/*
569*************************************************************************
570* Serial Management Controllers *
571*************************************************************************
572*/
573typedef struct m8xxSMCparms_ {
574 uint16_t rbase;
575 uint16_t tbase;
576 uint8_t rfcr;
577 uint8_t tfcr;
578 uint16_t mrblr;
579 uint32_t _rstate;
580 uint32_t _pad0;
581 uint16_t _rbptr;
582 uint16_t _pad1;
583 uint32_t _pad2;
584 uint32_t _tstate;
585 uint32_t _pad3;
586 uint16_t _tbptr;
587 uint16_t _pad4;
588 uint32_t _pad5;
589 union {
590 struct {
591 uint16_t max_idl;
592 uint16_t _idlc;
593 uint16_t brkln;
594 uint16_t brkec;
595 uint16_t brkcr;
596 uint16_t _r_mask;
597 } uart;
598 struct {
599 uint16_t _pad0[5];
600 } transparent;
601 } un;
602} m8xxSMCparms_t;
603
604/*
605 * Mode register
606 */
607#define M8xx_SMCMR_CLEN(x) ((x)<<11) /* Character length */
608#define M8xx_SMCMR_2STOP (1<<10) /* 2 stop bits */
609#define M8xx_SMCMR_PARITY (1<<9) /* Enable parity */
610#define M8xx_SMCMR_EVEN (1<<8) /* Even parity */
611#define M8xx_SMCMR_SM_GCI (0<<4) /* GCI Mode */
612#define M8xx_SMCMR_SM_UART (2<<4) /* UART Mode */
613#define M8xx_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
614#define M8xx_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
615#define M8xx_SMCMR_DM_ECHO (2<<2) /* Echo mode */
616#define M8xx_SMCMR_TEN (1<<1) /* Enable transmitter */
617#define M8xx_SMCMR_REN (1<<0) /* Enable receiver */
618
619/*
620 * Event and mask registers (SMCE, SMCM)
621 */
622#define M8xx_SMCE_BRKE (1<<6)
623#define M8xx_SMCE_BRK (1<<4)
624#define M8xx_SMCE_BSY (1<<2)
625#define M8xx_SMCE_TX (1<<1)
626#define M8xx_SMCE_RX (1<<0)
627
628/*
629*************************************************************************
630* Serial Peripheral Interface *
631*************************************************************************
632*/
633typedef struct m8xxSPIparms_ {
634 uint16_t rbase;
635 uint16_t tbase;
636 uint8_t rfcr;
637 uint8_t tfcr;
638 uint16_t mrblr;
639 uint32_t _rstate;
640 uint32_t _pad0;
641 uint16_t _rbptr;
642 uint16_t _pad1;
643 uint32_t _pad2;
644 uint32_t _tstate;
645 uint32_t _pad3;
646 uint16_t _tbptr;
647 uint16_t _pad4;
648 uint32_t _pad5;
649} m8xxSPIparms_t;
650
651/*
652 * Mode register (SPMODE)
653 */
654#define M8xx_SPMODE_LOOP (1<<14) /* Local loopback mode */
655#define M8xx_SPMODE_CI (1<<13) /* Clock invert */
656#define M8xx_SPMODE_CP (1<<12) /* Clock phase */
657#define M8xx_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
658#define M8xx_SPMODE_REV (1<<10) /* Reverse data */
659#define M8xx_SPMODE_MASTER (1<<9) /* SPI is master */
660#define M8xx_SPMODE_EN (1<<8) /* Enable SPI */
661#define M8xx_SPMODE_CLEN(x) ((x)<<4) /* Character length */
662#define M8xx_SPMODE_PM(x) (x) /* Prescaler modulus */
663
664/*
665 * Mode register (SPCOM)
666 */
667#define M8xx_SPCOM_STR (1<<7) /* Start transmit */
668
669/*
670 * Event and mask registers (SPIE, SPIM)
671 */
672#define M8xx_SPIE_MME (1<<5) /* Multi-master error */
673#define M8xx_SPIE_TXE (1<<4) /* Tx error */
674#define M8xx_SPIE_BSY (1<<2) /* Busy condition*/
675#define M8xx_SPIE_TXB (1<<1) /* Tx buffer */
676#define M8xx_SPIE_RXB (1<<0) /* Rx buffer */
677
678/*
679*************************************************************************
680* SDMA (SCC, SMC, SPI) Buffer Descriptors *
681*************************************************************************
682*/
683typedef struct m8xxBufferDescriptor_ {
684 volatile uint16_t status;
685 uint16_t length;
686 void *buffer;
687} m8xxBufferDescriptor_t;
688
689/*
690 * Bits in receive buffer descriptor status word
691 */
692#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
693#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
694#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
695#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */
696#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */
697#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
698#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */
699#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
700#define M8xx_BD_MISS (1<<8) /* Ethernet */
701#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */
702#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
703#define M8xx_BD_LONG (1<<5) /* Ethernet */
704#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */
705#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet */
706#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
707#define M8xx_BD_SHORT (1<<3) /* Ethernet */
708#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
709#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet */
710#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
711#define M8xx_BD_COLLISION (1<<0) /* Ethernet */
712#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */
713#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */
714
715/*
716 * Bits in transmit buffer descriptor status word
717 * Many bits have the same meaning as those in receiver buffer descriptors.
718 */
719#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
720#define M8xx_BD_PAD (1<<14) /* Ethernet */
721#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */
722#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */
723#define M8xx_BD_DEFER (1<<9) /* Ethernet */
724#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */
725#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
726#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */
727#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */
728#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */
729#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
730#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
731#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */
732#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART */
733
734/*
735*************************************************************************
736* IDMA Buffer Descriptors *
737*************************************************************************
738*/
739typedef struct m8xxIDMABufferDescriptor_ {
740 uint16_t status;
741 uint8_t dfcr;
742 uint8_t sfcr;
743 uint32_t length;
744 void *source;
745 void *destination;
746} m8xxIDMABufferDescriptor_t;
747
748/*
749*************************************************************************
750* RISC Communication Processor Module Command Register (CR) *
751*************************************************************************
752*/
753#define M8xx_CR_RST (1<<15) /* Reset communication processor */
754#define M8xx_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
755#define M8xx_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
756#define M8xx_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
757#define M8xx_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
758#define M8xx_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
759#define M8xx_CR_OP_GR_STOP_TX (5<<8) /* SCC */
760#define M8xx_CR_OP_INIT_IDMA (5<<8) /* IDMA */
761#define M8xx_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
762#define M8xx_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
763#define M8xx_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
764#define M8xx_CR_OP_SET_TIMER (8<<8) /* Timer */
765#define M8xx_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
766#define M8xx_CR_OP_RESERT_BCS (10<<8) /* SCC */
767#define M8xx_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
768#define M8xx_CR_OP_STOP_IDMA (11<<8) /* IDMA */
769#define M8xx_CR_OP_START_DSP (12<<8) /* DSP */
770#define M8xx_CR_OP_INIT_DSP (13<<8) /* DSP */
771
772#define M8xx_CR_CHAN_SCC1 (0<<4) /* Channel selection */
773#define M8xx_CR_CHAN_I2C (1<<4)
774#define M8xx_CR_CHAN_IDMA1 (1<<4)
775#define M8xx_CR_CHAN_SCC2 (4<<4)
776#define M8xx_CR_CHAN_SPI (5<<4)
777#define M8xx_CR_CHAN_IDMA2 (5<<4)
778#define M8xx_CR_CHAN_TIMER (5<<4)
779#define M8xx_CR_CHAN_SCC3 (8<<4)
780#define M8xx_CR_CHAN_SMC1 (9<<4)
781#define M8xx_CR_CHAN_DSP1 (9<<4)
782#define M8xx_CR_CHAN_SCC4 (12<<4)
783#define M8xx_CR_CHAN_SMC2 (13<<4)
784#define M8xx_CR_CHAN_DSP2 (13<<4)
785#define M8xx_CR_FLG (1<<0) /* Command flag */
786
787/*
788*************************************************************************
789* System Protection Control Register (SYPCR) *
790*************************************************************************
791*/
792#define M8xx_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */
793#define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
794#define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */
795#define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */
796#define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */
797#define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
798#define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */
799
800/*
801*************************************************************************
802* PCMCIA Control Registers
803*************************************************************************
804*/
805#define M8xx_PCMCIA_POR_BSIZE_1B (0x00 << (31-4))
806#define M8xx_PCMCIA_POR_BSIZE_2B (0x01 << (31-4))
807#define M8xx_PCMCIA_POR_BSIZE_4B (0x03 << (31-4))
808#define M8xx_PCMCIA_POR_BSIZE_8B (0x02 << (31-4))
809#define M8xx_PCMCIA_POR_BSIZE_16B (0x06 << (31-4))
810#define M8xx_PCMCIA_POR_BSIZE_32B (0x07 << (31-4))
811#define M8xx_PCMCIA_POR_BSIZE_64B (0x05 << (31-4))
812#define M8xx_PCMCIA_POR_BSIZE_128B (0x04 << (31-4))
813#define M8xx_PCMCIA_POR_BSIZE_256B (0x0C << (31-4))
814#define M8xx_PCMCIA_POR_BSIZE_512B (0x0D << (31-4))
815#define M8xx_PCMCIA_POR_BSIZE_1KB (0x0F << (31-4))
816#define M8xx_PCMCIA_POR_BSIZE_2KB (0x0E << (31-4))
817#define M8xx_PCMCIA_POR_BSIZE_4KB (0x0A << (31-4))
818#define M8xx_PCMCIA_POR_BSIZE_8KB (0x0B << (31-4))
819#define M8xx_PCMCIA_POR_BSIZE_16KB (0x09 << (31-4))
820#define M8xx_PCMCIA_POR_BSIZE_32KB (0x08 << (31-4))
821#define M8xx_PCMCIA_POR_BSIZE_64KB (0x18 << (31-4))
822#define M8xx_PCMCIA_POR_BSIZE_128KB (0x19 << (31-4))
823#define M8xx_PCMCIA_POR_BSIZE_256KB (0x1B << (31-4))
824#define M8xx_PCMCIA_POR_BSIZE_512KB (0x1A << (31-4))
825#define M8xx_PCMCIA_POR_BSIZE_1MB (0x1E << (31-4))
826#define M8xx_PCMCIA_POR_BSIZE_2MB (0x1F << (31-4))
827#define M8xx_PCMCIA_POR_BSIZE_4MB (0x1D << (31-4))
828#define M8xx_PCMCIA_POR_BSIZE_8MB (0x1C << (31-4))
829#define M8xx_PCMCIA_POR_BSIZE_16MB (0x14 << (31-4))
830#define M8xx_PCMCIA_POR_BSIZE_32MB (0x15 << (31-4))
831#define M8xx_PCMCIA_POR_BSIZE_64MB (0x17 << (31-4))
832
833#define M8xx_PCMCIA_POR_PSHT(x) (((x) & 0x0f) << (31-15))
834#define M8xx_PCMCIA_POR_PSST(x) (((x) & 0x0f) << (31-19))
835#define M8xx_PCMCIA_POR_PSL(x) (((x) & 0x1f) << (31-24))
836#define M8xx_PCMCIA_POR_PPS_8 ((0) << (31-19))
837#define M8xx_PCMCIA_POR_PPS_16 ((1) << (31-19))
838
839#define M8xx_PCMCIA_POR_PRS_MEM ((0) << (31-28))
840#define M8xx_PCMCIA_POR_PRS_ATT ((2) << (31-28))
841#define M8xx_PCMCIA_POR_PRS_IO ((3) << (31-28))
842#define M8xx_PCMCIA_POR_PRS_DMA ((4) << (31-28))
843#define M8xx_PCMCIA_POR_PRS_DML ((5) << (31-28))
844
845#define M8xx_PCMCIA_POR_PSLOT_A ((0) << (31-29))
846#define M8xx_PCMCIA_POR_PSLOT_B ((1) << (31-29))
847
848#define M8xx_PCMCIA_POR_WP ((1) << (31-30))
849#define M8xx_PCMCIA_POR_VALID ((1) << (31-31))
850
851#define M8xx_PCMCIA_PGCR_CIRQLVL(x) (((x) & 0xff) << (31- 7))
852#define M8xx_PCMCIA_PGCR_CSCHLVL(x) (((x) & 0xff) << (31-15))
853#define M8xx_PCMCIA_PGCR_CDRQ_OFF ((0) << (31-17))
854#define M8xx_PCMCIA_PGCR_CDRQ_IOIS16 ((2) << (31-17))
855#define M8xx_PCMCIA_PGCR_CDRQ_SPKR ((3) << (31-17))
856#define M8xx_PCMCIA_PGCR_COE ((1) << (31-24))
857#define M8xx_PCMCIA_PGCR_CRESET ((1) << (31-25))
858
859#define M8xx_PCMCIA_PIPR_CAVS1 ((1) << (31- 0))
860#define M8xx_PCMCIA_PIPR_CAVS2 ((1) << (31- 1))
861#define M8xx_PCMCIA_PIPR_CAWP ((1) << (31- 2))
862#define M8xx_PCMCIA_PIPR_CACD2 ((1) << (31- 3))
863#define M8xx_PCMCIA_PIPR_CACD1 ((1) << (31- 4))
864#define M8xx_PCMCIA_PIPR_CABVD2 ((1) << (31- 5))
865#define M8xx_PCMCIA_PIPR_CABVD1 ((1) << (31- 6))
866#define M8xx_PCMCIA_PIPR_CARDY ((1) << (31- 7))
867#define M8xx_PCMCIA_PIPR_CBVS1 ((1) << (31-16))
868#define M8xx_PCMCIA_PIPR_CBVS2 ((1) << (31-17))
869#define M8xx_PCMCIA_PIPR_CBWP ((1) << (31-18))
870#define M8xx_PCMCIA_PIPR_CBCD2 ((1) << (31-19))
871#define M8xx_PCMCIA_PIPR_CBCD1 ((1) << (31-20))
872#define M8xx_PCMCIA_PIPR_CBBVD2 ((1) << (31-21))
873#define M8xx_PCMCIA_PIPR_CBBVD1 ((1) << (31-22))
874#define M8xx_PCMCIA_PIPR_CBRDY ((1) << (31-23))
875
876
877#define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
878#define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */
879#define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */
880#define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */
881#define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
882#define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */
883
884/*
885*************************************************************************
886* Memory Control Registers *
887*************************************************************************
888*/
889#define M8xx_UPM_AMX_8col (0<<20) /* 8 column DRAM */
890#define M8xx_UPM_AMX_9col (1<<20) /* 9 column DRAM */
891#define M8xx_UPM_AMX_10col (2<<20) /* 10 column DRAM */
892#define M8xx_UPM_AMX_11col (3<<20) /* 11 column DRAM */
893#define M8xx_UPM_AMX_12col (4<<20) /* 12 column DRAM */
894#define M8xx_UPM_AMX_13col (5<<20) /* 13 column DRAM */
895#define M8xx_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */
896#define M8xx_MSR_WPER (1<<7) /* Write protection error */
897#define M8xx_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */
898#define M8xx_BR_BA(x) ((x)&0xffff8000) /* Base address */
899#define M8xx_BR_AT(x) ((x)<<12) /* Address type */
900#define M8xx_BR_PS8 (1<<10) /* 8 bit port */
901#define M8xx_BR_PS16 (2<<10) /* 16 bit port */
902#define M8xx_BR_PS32 (0<<10) /* 32 bit port */
903#define M8xx_BR_PARE (1<<9) /* Parity checking enable */
904#define M8xx_BR_WP (1<<8) /* Write protect */
905#define M8xx_BR_MS_GPCM (0<<6) /* GPCM */
906#define M8xx_BR_MS_UPMA (2<<6) /* UPM A */
907#define M8xx_BR_MS_UPMB (3<<6) /* UPM B */
908#define M8xx_MEMC_BR_V (1<<0) /* Base/Option register are valid */
909
910#define M8xx_MEMC_OR_32K 0xffff8000 /* Address range */
911#define M8xx_MEMC_OR_64K 0xffff0000
912#define M8xx_MEMC_OR_128K 0xfffe0000
913#define M8xx_MEMC_OR_256K 0xfffc0000
914#define M8xx_MEMC_OR_512K 0xfff80000
915#define M8xx_MEMC_OR_1M 0xfff00000
916#define M8xx_MEMC_OR_2M 0xffe00000
917#define M8xx_MEMC_OR_4M 0xffc00000
918#define M8xx_MEMC_OR_8M 0xff800000
919#define M8xx_MEMC_OR_16M 0xff000000
920#define M8xx_MEMC_OR_32M 0xfe000000
921#define M8xx_MEMC_OR_64M 0xfc000000
922#define M8xx_MEMC_OR_128 0xf8000000
923#define M8xx_MEMC_OR_256M 0xf0000000
924#define M8xx_MEMC_OR_512M 0xe0000000
925#define M8xx_MEMC_OR_1G 0xc0000000
926#define M8xx_MEMC_OR_2G 0x80000000
927#define M8xx_MEMC_OR_4G 0x00000000
928#define M8xx_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */
929#define M8xx_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */
930#define M8xx_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */
931#define M8xx_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */
932#define M8xx_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */
933#define M8xx_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */
934#define M8xx_MEMC_OR_BI (1<<8) /* Burst inhibit */
935#define M8xx_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */
936#define M8xx_MEMC_OR_SETA (1<<3) /* *TA generated externally */
937#define M8xx_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */
938#define M8xx_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */
939
940/*
941*************************************************************************
942* UPM Registers (MxMR) *
943*************************************************************************
944*/
945#define M8xx_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */
946#define M8xx_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */
947#define M8xx_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */
948#define M8xx_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */
949#define M8xx_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */
950#define M8xx_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */
951#define M8xx_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */
952#define M8xx_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */
953/*
954*************************************************************************
955* Memory Command Register (MCR) *
956*************************************************************************
957*/
958#define M8xx_MEMC_MCR_WRITE (0<<30) /* WRITE command */
959#define M8xx_MEMC_MCR_READ (1<<30) /* READ command */
960#define M8xx_MEMC_MCR_RUN (2<<30) /* RUN command */
961#define M8xx_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */
962#define M8xx_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */
963#define M8xx_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */
964#define M8xx_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */
965#define M8xx_MEMC_MCR_MAD(x) (x) /* Machine address */
966
967
968
969/*
970*************************************************************************
971* SI Mode Register (SIMODE) *
972*************************************************************************
973*/
974#define M8xx_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
975#define M8xx_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
976#define M8xx_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
977#define M8xx_SI_SMC2_BRG2 (1<<28)
978#define M8xx_SI_SMC2_BRG3 (2<<28)
979#define M8xx_SI_SMC2_BRG4 (3<<28)
980#define M8xx_SI_SMC2_CLK5 (0<<28)
981#define M8xx_SI_SMC2_CLK6 (1<<28)
982#define M8xx_SI_SMC2_CLK7 (2<<28)
983#define M8xx_SI_SMC2_CLK8 (3<<28)
984#define M8xx_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
985#define M8xx_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
986#define M8xx_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
987#define M8xx_SI_SMC1_BRG2 (1<<12)
988#define M8xx_SI_SMC1_BRG3 (2<<12)
989#define M8xx_SI_SMC1_BRG4 (3<<12)
990#define M8xx_SI_SMC1_CLK1 (0<<12)
991#define M8xx_SI_SMC1_CLK2 (1<<12)
992#define M8xx_SI_SMC1_CLK3 (2<<12)
993#define M8xx_SI_SMC1_CLK4 (3<<12)
994
995/*
996*************************************************************************
997* SDMA Configuration Register (SDCR) *
998*************************************************************************
999*/
1000#define M8xx_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */
1001#define M8xx_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */
1002
1003/*
1004*************************************************************************
1005* SDMA Status Register (SDSR) *
1006*************************************************************************
1007*/
1008#define M8xx_SDSR_SBER (1<<7) /* SDMA Channel bus error */
1009#define M8xx_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */
1010#define M8xx_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */
1011
1012/*
1013*************************************************************************
1014* Baud (sic) Rate Generators *
1015*************************************************************************
1016*/
1017#define M8xx_BRG_RST (1<<17) /* Reset generator */
1018#define M8xx_BRG_EN (1<<16) /* Enable generator */
1019#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
1020#define M8xx_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
1021#define M8xx_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
1022#define M8xx_BRG_ATB (1<<13) /* Autobaud */
1023#define M8xx_BRG_115200 (21<<1) /* Assume 40 MHz clock */
1024#define M8xx_BRG_57600 (32<<1)
1025#define M8xx_BRG_38400 (64<<1)
1026#define M8xx_BRG_19200 (129<<1)
1027#define M8xx_BRG_9600 (259<<1)
1028#define M8xx_BRG_4800 (520<<1)
1029#define M8xx_BRG_2400 (1040<<1)
1030#define M8xx_BRG_1200 (2082<<1)
1031#define M8xx_BRG_600 ((259<<1) | 1)
1032#define M8xx_BRG_300 ((520<<1) | 1)
1033#define M8xx_BRG_150 ((1040<<1) | 1)
1034#define M8xx_BRG_75 ((2080<<1) | 1)
1035
1036#define M8xx_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */
1037#define M8xx_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */
1038#define M8xx_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */
1039#define M8xx_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */
1040#define M8xx_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */
1041#define M8xx_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */
1042#define M8xx_TGCR_STP1 (1<<1) /* Stop timer */
1043#define M8xx_TGCR_STP2 (1<<5) /* Stop timer */
1044#define M8xx_TGCR_STP3 (1<<9) /* Stop timer */
1045#define M8xx_TGCR_STP4 (1<<13) /* Stop timer */
1046#define M8xx_TGCR_RST1 (1<<0) /* Enable timer */
1047#define M8xx_TGCR_RST2 (1<<4) /* Enable timer */
1048#define M8xx_TGCR_RST3 (1<<8) /* Enable timer */
1049#define M8xx_TGCR_RST4 (1<<12) /* Enable timer */
1050#define M8xx_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */
1051#define M8xx_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */
1052
1053#define M8xx_TMR_PS(x) ((x)<<8) /* Timer prescaler */
1054#define M8xx_TMR_CE_RISE (1<<6) /* Capture on rising edge */
1055#define M8xx_TMR_CE_FALL (2<<6) /* Capture on falling edge */
1056#define M8xx_TMR_CE_ANY (3<<6) /* Capture on any edge */
1057#define M8xx_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */
1058#define M8xx_TMR_ORI (1<<4) /* Interrupt on reaching reference */
1059#define M8xx_TMR_RESTART (1<<3) /* Restart timer after reference */
1060#define M8xx_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */
1061#define M8xx_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */
1062#define M8xx_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */
1063#define M8xx_TMR_TGATE (1<<0) /* TGATE controls timer */
1064
1065#define M8xx_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */
1066#define M8xx_PISCR_PS (1<<7) /* PIT Interrupt state */
1067#define M8xx_PISCR_PIE (1<<2) /* PIT interrupt enable */
1068#define M8xx_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */
1069#define M8xx_PISCR_PTE (1<<0) /* PIT enable */
1070
1071#define M8xx_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */
1072#define M8xx_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */
1073#define M8xx_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */
1074#define M8xx_TBSCR_REFAE (1<<3) /* Enable ints for REFA */
1075#define M8xx_TBSCR_REFBE (1<<2) /* Enable ints for REFB */
1076#define M8xx_TBSCR_TBF (1<<1) /* TB stops on FREEZE */
1077#define M8xx_TBSCR_TBE (1<<0) /* enable TB and decrementer */
1078
1079#define M8xx_SIMASK_IRM0 (1<<31)
1080#define M8xx_SIMASK_LVM0 (1<<30)
1081#define M8xx_SIMASK_IRM1 (1<<29)
1082#define M8xx_SIMASK_LVM1 (1<<28)
1083#define M8xx_SIMASK_IRM2 (1<<27)
1084#define M8xx_SIMASK_LVM2 (1<<26)
1085#define M8xx_SIMASK_IRM3 (1<<25)
1086#define M8xx_SIMASK_LVM3 (1<<24)
1087#define M8xx_SIMASK_IRM4 (1<<23)
1088#define M8xx_SIMASK_LVM4 (1<<22)
1089#define M8xx_SIMASK_IRM5 (1<<21)
1090#define M8xx_SIMASK_LVM5 (1<<20)
1091#define M8xx_SIMASK_IRM6 (1<<19)
1092#define M8xx_SIMASK_LVM6 (1<<18)
1093#define M8xx_SIMASK_IRM7 (1<<17)
1094#define M8xx_SIMASK_LVM7 (1<<16)
1095
1096#define M8xx_SIUMCR_EARB (1<<31)
1097#define M8xx_SIUMCR_EARP0 (0<<28)
1098#define M8xx_SIUMCR_EARP1 (1<<28)
1099#define M8xx_SIUMCR_EARP2 (2<<28)
1100#define M8xx_SIUMCR_EARP3 (3<<28)
1101#define M8xx_SIUMCR_EARP4 (4<<28)
1102#define M8xx_SIUMCR_EARP5 (5<<28)
1103#define M8xx_SIUMCR_EARP6 (6<<28)
1104#define M8xx_SIUMCR_EARP7 (7<<28)
1105#define M8xx_SIUMCR_DSHW (1<<23)
1106#define M8xx_SIUMCR_DBGC0 (0<<21)
1107#define M8xx_SIUMCR_DBGC1 (1<<21)
1108#define M8xx_SIUMCR_DBGC2 (2<<21)
1109#define M8xx_SIUMCR_DBGC3 (3<<21)
1110#define M8xx_SIUMCR_DBPC0 (0<<19)
1111#define M8xx_SIUMCR_DBPC1 (1<<19)
1112#define M8xx_SIUMCR_DBPC2 (2<<19)
1113#define M8xx_SIUMCR_DBPC3 (3<<19)
1114#define M8xx_SIUMCR_FRC (1<<17)
1115#define M8xx_SIUMCR_DLK (1<<16)
1116#define M8xx_SIUMCR_PNCS (1<<15)
1117#define M8xx_SIUMCR_OPAR (1<<14)
1118#define M8xx_SIUMCR_DPC (1<<13)
1119#define M8xx_SIUMCR_MPRE (1<<12)
1120#define M8xx_SIUMCR_MLRC0 (0<<10)
1121#define M8xx_SIUMCR_MLRC1 (1<<10)
1122#define M8xx_SIUMCR_MLRC2 (2<<10)
1123#define M8xx_SIUMCR_MLRC3 (3<<10)
1124#define M8xx_SIUMCR_AEME (1<<9)
1125#define M8xx_SIUMCR_SEME (1<<8)
1126#define M8xx_SIUMCR_BSC (1<<7)
1127#define M8xx_SIUMCR_GB5E (1<<6)
1128#define M8xx_SIUMCR_B2DD (1<<5)
1129#define M8xx_SIUMCR_B3DD (1<<4)
1130
1131/*
1132 * Value to write to a key register to unlock the corresponding SIU register
1133 */
1134#define M8xx_UNLOCK_KEY 0x55CCAA33
1135
1136/*
1137*************************************************************************
1138* MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address) *
1139*************************************************************************
1140*/
1141typedef struct m8xx_ {
1142
1143 /*
1144 * SIU Block
1145 */
1146 uint32_t siumcr;
1147 uint32_t sypcr;
1148#if defined(mpc860)
1149 uint32_t swt;
1150#elif defined(mpc821)
1151 uint32_t _pad70;
1152#endif
1153 uint16_t _pad0;
1154 uint16_t swsr;
1155 uint32_t sipend;
1156 uint32_t simask;
1157 uint32_t siel;
1158 uint32_t sivec;
1159 uint32_t tesr;
1160 uint32_t _pad1[3];
1161 uint32_t sdcr;
1162 uint8_t _pad2[0x80-0x34];
1163
1164 /*
1165 * PCMCIA Block
1166 */
1167 uint32_t pbr0;
1168 uint32_t por0;
1169 uint32_t pbr1;
1170 uint32_t por1;
1171 uint32_t pbr2;
1172 uint32_t por2;
1173 uint32_t pbr3;
1174 uint32_t por3;
1175 uint32_t pbr4;
1176 uint32_t por4;
1177 uint32_t pbr5;
1178 uint32_t por5;
1179 uint32_t pbr6;
1180 uint32_t por6;
1181 uint32_t pbr7;
1182 uint32_t por7;
1183 uint8_t _pad3[0xe0-0xc0];
1184 uint32_t pgcra;
1185 uint32_t pgcrb;
1186 uint32_t pscr;
1187 uint32_t _pad4;
1188 uint32_t pipr;
1189 uint32_t _pad5;
1190 uint32_t per;
1191 uint32_t _pad6;
1192
1193 /*
1194 * MEMC Block
1195 */
1196 m8xxMEMCRegisters_t memc[8];
1197 uint8_t _pad7[0x164-0x140];
1198 uint32_t mar;
1199 uint32_t mcr;
1200 uint32_t _pad8;
1201 uint32_t mamr;
1202 uint32_t mbmr;
1203 uint16_t mstat;
1204 uint16_t mptpr;
1205 uint32_t mdr;
1206 uint8_t _pad9[0x200-0x180];
1207
1208 /*
1209 * System integration timers
1210 */
1211 uint16_t tbscr;
1212 uint16_t _pad10;
1213 uint32_t tbreff0;
1214 uint32_t tbreff1;
1215 uint8_t _pad11[0x220-0x20c];
1216 uint16_t rtcsc;
1217 uint16_t _pad12;
1218 uint32_t rtc;
1219 uint32_t rtsec;
1220 uint32_t rtcal;
1221 uint32_t _pad13[4];
1222 uint16_t piscr;
1223 uint16_t _pad14;
1224 uint16_t pitc;
1225 uint16_t _pad_14_1;
1226 uint16_t pitr;
1227 uint16_t _pad_14_2;
1228 uint8_t _pad15[0x280-0x24c];
1229
1230
1231 /*
1232 * Clocks and Reset
1233 */
1234 uint32_t sccr;
1235 uint32_t plprcr;
1236 uint32_t rsr;
1237 uint8_t _pad16[0x300-0x28c];
1238
1239
1240 /*
1241 * System integration timers keys
1242 */
1243 uint32_t tbscrk;
1244 uint32_t tbreff0k;
1245 uint32_t tbreff1k;
1246 uint32_t tbk;
1247 uint32_t _pad17[4];
1248 uint32_t rtcsk;
1249 uint32_t rtck;
1250 uint32_t rtseck;
1251 uint32_t rtcalk;
1252 uint32_t _pad18[4];
1253 uint32_t piscrk;
1254 uint32_t pitck;
1255 uint8_t _pad19[0x380-0x348];
1256
1257 /*
1258 * Clocks and Reset Keys
1259 */
1260 uint32_t sccrk;
1261 uint32_t plprck;
1262 uint32_t rsrk;
1263 uint8_t _pad20[0x400-0x38c];
1264 uint8_t _pad21[0x800-0x400];
1265 uint8_t _pad22[0x860-0x800];
1266
1267
1268 /*
1269 * I2C
1270 */
1271 uint8_t i2mod;
1272 uint8_t _pad23[3];
1273 uint8_t i2add;
1274 uint8_t _pad24[3];
1275 uint8_t i2brg;
1276 uint8_t _pad25[3];
1277 uint8_t i2com;
1278 uint8_t _pad26[3];
1279 uint8_t i2cer;
1280 uint8_t _pad27[3];
1281 uint8_t i2cmr;
1282 uint8_t _pad28[0x900-0x875];
1283
1284 /*
1285 * DMA Block
1286 */
1287 uint32_t _pad29;
1288 uint32_t sdar;
1289 uint8_t sdsr;
1290 uint8_t _pad30[3];
1291 uint8_t sdmr;
1292 uint8_t _pad31[3];
1293 uint8_t idsr1;
1294 uint8_t _pad32[3];
1295 uint8_t idmr1;
1296 uint8_t _pad33[3];
1297 uint8_t idsr2;
1298 uint8_t _pad34[3];
1299 uint8_t idmr2;
1300 uint8_t _pad35[0x930-0x91d];
1301
1302 /*
1303 * CPM Interrupt Control Block
1304 */
1305 uint16_t civr;
1306 uint8_t _pad36[14];
1307 uint32_t cicr;
1308 uint32_t cipr;
1309 uint32_t cimr;
1310 uint32_t cisr;
1311
1312 /*
1313 * I/O Port Block
1314 */
1315 uint16_t padir;
1316 uint16_t papar;
1317 uint16_t paodr;
1318 uint16_t padat;
1319 uint8_t _pad37[8];
1320 uint16_t pcdir;
1321 uint16_t pcpar;
1322 uint16_t pcso;
1323 uint16_t pcdat;
1324 uint16_t pcint;
1325 uint8_t _pad39[6];
1326 uint16_t pddir;
1327 uint16_t pdpar;
1328 uint16_t _pad40;
1329 uint16_t pddat;
1330 uint8_t _pad41[8];
1331
1332 /*
1333 * CPM Timers Block
1334 */
1335 uint16_t tgcr;
1336 uint8_t _pad42[14];
1337 uint16_t tmr1;
1338 uint16_t tmr2;
1339 uint16_t trr1;
1340 uint16_t trr2;
1341 uint16_t tcr1;
1342 uint16_t tcr2;
1343 uint16_t tcn1;
1344 uint16_t tcn2;
1345 uint16_t tmr3;
1346 uint16_t tmr4;
1347 uint16_t trr3;
1348 uint16_t trr4;
1349 uint16_t tcr3;
1350 uint16_t tcr4;
1351 uint16_t tcn3;
1352 uint16_t tcn4;
1353 uint16_t ter1;
1354 uint16_t ter2;
1355 uint16_t ter3;
1356 uint16_t ter4;
1357 uint8_t _pad43[8];
1358
1359 /*
1360 * CPM Block
1361 */
1362 uint16_t cpcr;
1363 uint16_t _pad44;
1364 uint16_t rccr;
1365 uint8_t _pad45;
1366 uint8_t rmds;
1367 uint32_t rmdr;
1368 uint16_t rctr1;
1369 uint16_t rctr2;
1370 uint16_t rctr3;
1371 uint16_t rctr4;
1372 uint16_t _pad46;
1373 uint16_t rter;
1374 uint16_t _pad47;
1375 uint16_t rtmr;
1376 uint8_t _pad48[0x9f0-0x9dc];
1377
1378 /*
1379 * BRG Block
1380 */
1381 uint32_t brgc1;
1382 uint32_t brgc2;
1383 uint32_t brgc3;
1384 uint32_t brgc4;
1385
1386 /*
1387 * SCC Block
1388 */
1389 m8xxSCCRegisters_t scc1;
1390 m8xxSCCRegisters_t scc2;
1391#if defined(mpc860)
1392 m8xxSCCRegisters_t scc3;
1393 m8xxSCCRegisters_t scc4;
1394#elif defined(mpc821)
1395 uint8_t _pad72[0xa80-0xa40];
1396#endif
1397
1398 /*
1399 * SMC Block
1400 */
1401 m8xxSMCRegisters_t smc1;
1402 m8xxSMCRegisters_t smc2;
1403
1404 /*
1405 * SPI Block
1406 */
1407 uint16_t spmode;
1408 uint16_t _pad49[2];
1409 uint8_t spie;
1410 uint8_t _pad50;
1411 uint16_t _pad51;
1412 uint8_t spim;
1413 uint8_t _pad52[2];
1414 uint8_t spcom;
1415 uint16_t _pad53[2];
1416
1417 /*
1418 * PIP Block
1419 */
1420 uint16_t pipc;
1421 uint16_t _pad54;
1422 uint16_t ptpr;
1423 uint32_t pbdir;
1424 uint32_t pbpar;
1425 uint16_t _pad55;
1426 uint16_t pbodr;
1427 uint32_t pbdat;
1428 uint32_t _pad56[6];
1429
1430 /*
1431 * SI Block
1432 */
1433 uint32_t simode;
1434 uint8_t sigmr;
1435 uint8_t _pad57;
1436 uint8_t sistr;
1437 uint8_t sicmr;
1438 uint32_t _pad58;
1439 uint32_t sicr;
1440 uint16_t sirp[2];
1441 uint32_t _pad59[3];
1442 uint8_t _pad60[0xc00-0xb00];
1443 uint8_t siram[512];
1444#if defined(mpc860)
1445 /*
1446 * This is only used on the MPC8xxT - for the Fast Ethernet Controller (FEC)
1447 */
1448 m8xxFECRegisters_t fec;
1449#elif defined(mpc821)
1450 uint8_t lcdram[512];
1451#endif
1452 uint8_t _pad62[0x2000-0x1000];
1453
1454 /*
1455 * Dual-port RAM
1456 */
1457 uint8_t dpram0[0x200]; /* BD/DATA/UCODE */
1458 uint8_t dpram1[0x200]; /* BD/DATA/UCODE */
1459 uint8_t dpram2[0x400]; /* BD/DATA/UCODE */
1460 uint8_t dpram3[0x600]; /* BD/DATA*/
1461 uint8_t dpram4[0x200]; /* BD/DATA/UCODE */
1462 uint8_t _pad63[0x3c00-0x3000];
1463
1464 /* When using SCC1 for ethernet, we lose the use of I2C since
1465 * their parameters would overlap. Motorola has a microcode
1466 * patch to move parameters around so that both can be used
1467 * together. It is available on their web site somewhere
1468 * under http://www.mot.com/mpc8xx. If ethernet is used on
1469 * one (or more) of the other SCCs, then other CPM features
1470 * will be unavailable:
1471 * SCC2 -> lose SPI
1472 * SCC3 -> lose SMC1
1473 * SCC4 -> lose SMC2
1474 * However, Ethernet only works on SCC1 on the 8xx.
1475 */
1476 m8xxSCCENparms_t scc1p;
1477 uint8_t _rsv1[0xCB0-0xC00-sizeof(m8xxSCCENparms_t)];
1478 m8xxMiscParms_t miscp;
1479 uint8_t _rsv2[0xcc0-0xCB0-sizeof(m8xxMiscParms_t)];
1480 m8xxIDMAparms_t idma1p;
1481 uint8_t _rsv3[0xd00-0xcc0-sizeof(m8xxIDMAparms_t)];
1482
1483 m8xxSCCparms_t scc2p;
1484 uint8_t _rsv4[0xD80-0xD00-sizeof(m8xxSCCparms_t)];
1485 m8xxSPIparms_t spip;
1486 uint8_t _rsv5[0xDB0-0xD80-sizeof(m8xxSPIparms_t)];
1487 m8xxTimerParms_t tmp;
1488 uint8_t _rsv6[0xDC0-0xDB0-sizeof(m8xxTimerParms_t)];
1489 m8xxIDMAparms_t idma2p;
1490 uint8_t _rsv7[0xE00-0xDC0-sizeof(m8xxIDMAparms_t)];
1491
1492 m8xxSCCparms_t scc3p; /* Not available on MPC821 */
1493 uint8_t _rsv8[0xE80-0xE00-sizeof(m8xxSCCparms_t)];
1494 m8xxSMCparms_t smc1p;
1495 uint8_t _rsv9[0xEC0-0xE80-sizeof(m8xxSMCparms_t)];
1496 m8xxDSPparms_t dsp1p;
1497 uint8_t _rsv10[0xF00-0xEC0-sizeof(m8xxDSPparms_t)];
1498
1499 m8xxSCCparms_t scc4p; /* Not available on MPC821 */
1500 uint8_t _rsv11[0xF80-0xF00-sizeof(m8xxSCCparms_t)];
1501 m8xxSMCparms_t smc2p;
1502 uint8_t _rsv12[0xFC0-0xF80-sizeof(m8xxSMCparms_t)];
1503 m8xxDSPparms_t dsp2p;
1504 uint8_t _rsv13[0x1000-0xFC0-sizeof(m8xxDSPparms_t)];
1505} m8xx_t;
1506
1507extern volatile m8xx_t m8xx;
1508
1509#ifdef __cplusplus
1510}
1511#endif
1512
1513#endif /* ASM */
1514
1515#endif /* _MPC8XX_H */
fec
Definition: 8xx_immap.h:340
m8xxBufferDescriptor_
Definition: mpc8xx.h:683
m8xxDSPparms_
Definition: mpc8xx.h:393
m8xxFECRegisters_
Definition: mpc8xx.h:226
m8xxIDMABufferDescriptor_
Definition: mpc8xx.h:739
m8xxIDMAparms_
Definition: mpc8xx.h:368
m8xxMEMCRegisters_
Definition: mpc8xx.h:185
m8xxMiscParms_
Definition: mpc8xx.h:319
m8xxSCCENparms_
Definition: mpc8xx.h:460
m8xxSCCRegisters_
Definition: mpc8xx.h:193
m8xxSCCparms_
Definition: mpc8xx.h:419
m8xxSMCRegisters_
Definition: mpc8xx.h:211
m8xxSMCparms_
Definition: mpc8xx.h:573
m8xxSPIparms_
Definition: mpc8xx.h:633
m8xxTimerParms_
Definition: mpc8xx.h:331
m8xx_
Definition: mpc8xx.h:1141
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