59#include <libcpu/spr.h>
72#define _eieio __asm__ volatile ("eieio\n"::)
73#define _sync __asm__ volatile ("sync\n"::)
74#define _isync __asm__ volatile ("isync\n"::)
81#define IMMR_FLEN (1<<11)
103#define BBCMCR_BE (1<<13)
104#define BBCMCR_ETRE (1<<12)
116#define MI_RA_PP (3 << 10)
117#define MI_RA_PP_SUPV (1 << 10)
118#define MI_RA_PP_USER (2 << 10)
119#define MI_RA_G (1 << 6)
137#define L2U_RA_PP (3 << 10)
138#define L2U_RA_PP_SUPV (1 << 10)
139#define L2U_RA_PP_USER (2 << 10)
140#define L2U_RA_G (1 << 6)
154#define USIU_SYPCR_SWTC(x) ((x)<<16)
155#define USIU_SYPCR_BMT(x) ((x)<<8)
156#define USIU_SYPCR_BME (1<<7)
157#define USIU_SYPCR_SWF (1<<3)
158#define USIU_SYPCR_SWE (1<<2)
159#define USIU_SYPCR_SWRI (1<<1)
160#define USIU_SYPCR_SWP (1<<0)
162#define USIU_SYPCR_BMT(x) ((x)<<8)
163#define USIU_SYPCR_BME (1<<7)
164#define USIU_SYPCR_SWF (1<<3)
165#define USIU_SYPCR_SWE (1<<2)
166#define USIU_SYPCR_SWRI (1<<1)
167#define USIU_SYPCR_SWP (1<<0)
174#define TICKLE_WATCHDOG() \
176 usiu.swsr = 0x556C; \
177 usiu.swsr = 0xAA39; \
185#define USIU_MEMC_BR_BA(x) (((uint32_t)x)&0xffff8000)
187#define USIU_MEMC_BR_AT(x) ((x)<<12)
188#define USIU_MEMC_BR_PS8 (1<<10)
189#define USIU_MEMC_BR_PS16 (2<<10)
190#define USIU_MEMC_BR_PS32 (0<<10)
191#define USIU_MEMC_BR_WP (1<<8)
192#define USIU_MEMC_BR_WEBS (1<<5)
193#define USIU_MEMC_BR_TBDIP (1<<4)
194#define USIU_MEMC_BR_LBDIP (1<<3)
195#define USIU_MEMC_BR_SETA (1<<2)
196#define USIU_MEMC_BR_BI (1<<1)
197#define USIU_MEMC_BR_V (1<<0)
199#define USIU_MEMC_OR_32K 0xffff8000
200#define USIU_MEMC_OR_64K 0xffff0000
201#define USIU_MEMC_OR_128K 0xfffe0000
202#define USIU_MEMC_OR_256K 0xfffc0000
203#define USIU_MEMC_OR_512K 0xfff80000
204#define USIU_MEMC_OR_1M 0xfff00000
205#define USIU_MEMC_OR_2M 0xffe00000
206#define USIU_MEMC_OR_4M 0xffc00000
207#define USIU_MEMC_OR_8M 0xff800000
208#define USIU_MEMC_OR_16M 0xff000000
209#define USIU_MEMC_OR_32M 0xfe000000
210#define USIU_MEMC_OR_64M 0xfc000000
211#define USIU_MEMC_OR_128 0xf8000000
212#define USIU_MEMC_OR_256M 0xf0000000
213#define USIU_MEMC_OR_512M 0xe0000000
214#define USIU_MEMC_OR_1G 0xc0000000
215#define USIU_MEMC_OR_2G 0x80000000
216#define USIU_MEMC_OR_4G 0x00000000
217#define USIU_MEMC_OR_ATM(x) ((x)<<12)
218#define USIU_MEMC_OR_CSNT (1<<11)
219#define USIU_MEMC_OR_ACS_NORM (0<<9)
220#define USIU_MEMC_OR_ACS_QRTR (2<<9)
221#define USIU_MEMC_OR_ACS_HALF (3<<9)
222#define USIU_MEMC_OR_ETHR (1<<8)
223#define USIU_MEMC_OR_SCY(x) ((x)<<4)
224#define USIU_MEMC_OR_BSCY(x) ((x)<<1)
225#define USIU_MEMC_OR_TRLX (1<<0)
233#define USIU_SCCR_DBCT (1<<31)
234#define USIU_SCCR_COM(x) ((x)<<29)
235#define USIU_SCCR_RTDIV (1<<24)
236#define USIU_PRQEN (1<<21)
237#define USIU_SCCR_EBDF(x) ((x)<<17)
238#define USIU_LME (1<<16)
239#define USIU_ENGDIV(x) ((x)<<9)
241#define USIU_PLPRCR_MF(x) (((x)-1)<<20)
242#define USIU_PLPRCR_SPLS (1<<16)
243#define USIU_PLPRCR_TEXPS (1<<14)
250#define USIU_PISCR_PIRQ(x) (1<<(15-x))
251#define USIU_PISCR_PS (1<<7)
252#define USIU_PISCR_PIE (1<<2)
253#define USIU_PISCR_PITF (1<<1)
254#define USIU_PISCR_PTE (1<<0)
261#define USIU_TBSCR_TBIRQ(x) (1<<(15-x))
262#define USIU_TBSCR_REFA (1<<7)
263#define USIU_TBSCR_REFB (1<<6)
264#define USIU_TBSCR_REFAE (1<<3)
265#define USIU_TBSCR_REFBE (1<<2)
266#define USIU_TBSCR_TBF (1<<1)
267#define USIU_TBSCR_TBE (1<<0)
274#define USIU_SIMASK_IRM0 (1<<31)
275#define USIU_SIMASK_LVM0 (1<<30)
276#define USIU_SIMASK_IRM1 (1<<29)
277#define USIU_SIMASK_LVM1 (1<<28)
278#define USIU_SIMASK_IRM2 (1<<27)
279#define USIU_SIMASK_LVM2 (1<<26)
280#define USIU_SIMASK_IRM3 (1<<25)
281#define USIU_SIMASK_LVM3 (1<<24)
282#define USIU_SIMASK_IRM4 (1<<23)
283#define USIU_SIMASK_LVM4 (1<<22)
284#define USIU_SIMASK_IRM5 (1<<21)
285#define USIU_SIMASK_LVM5 (1<<20)
286#define USIU_SIMASK_IRM6 (1<<19)
287#define USIU_SIMASK_LVM6 (1<<18)
288#define USIU_SIMASK_IRM7 (1<<17)
289#define USIU_SIMASK_LVM7 (1<<16)
296#define USIU_SIUMCR_EARB (1<<31)
297#define USIU_SIUMCR_EARP0 (0<<28)
298#define USIU_SIUMCR_EARP1 (1<<28)
299#define USIU_SIUMCR_EARP2 (2<<28)
300#define USIU_SIUMCR_EARP3 (3<<28)
301#define USIU_SIUMCR_EARP4 (4<<28)
302#define USIU_SIUMCR_EARP5 (5<<28)
303#define USIU_SIUMCR_EARP6 (6<<28)
304#define USIU_SIUMCR_EARP7 (7<<28)
305#define USIU_SIUMCR_DSHW (1<<23)
306#define USIU_SIUMCR_DBGC0 (0<<21)
307#define USIU_SIUMCR_DBGC1 (1<<21)
308#define USIU_SIUMCR_DBGC2 (2<<21)
309#define USIU_SIUMCR_DBGC3 (3<<21)
310#define USIU_SIUMCR_DBPC (1<<20)
311#define USIU_SIUMCR_ATWC (1<<19)
312#define USIU_SIUMCR_GPC0 (0<<17)
313#define USIU_SIUMCR_GPC1 (1<<17)
314#define USIU_SIUMCR_GPC2 (2<<17)
315#define USIU_SIUMCR_GPC3 (3<<17)
316#define USIU_SIUMCR_DLK (1<<16)
317#define USIU_SIUMCR_SC0 (0<<13)
318#define USIU_SIUMCR_SC1 (1<<13)
319#define USIU_SIUMCR_SC2 (2<<13)
320#define USIU_SIUMCR_SC3 (3<<13)
321#define USIU_SIUMCR_RCTX (1<<12)
322#define USIU_SIUMCR_MLRC0 (0<<10)
323#define USIU_SIUMCR_MLRC1 (1<<10)
324#define USIU_SIUMCR_MLRC2 (2<<10)
325#define USIU_SIUMCR_MLRC3 (3<<10)
326#define USIU_SIUMCR_MTSC (1<<7)
331#define USIU_UNLOCK_KEY 0x55CCAA33
338#define UIMB_UMCR_STOP (1<<31)
339#define UIMB_UMCR_IRQMUX(x) ((x)<<29)
340#define UIMB_UMCR_HSPEED (1<<28)
349#define QSMCM_ILDSCI(x) ((x)<<8)
351#define QSMCM_SCI_BAUD(x) ((x)&0x1FFF)
353#define QSMCM_SCI_LOOPS (1<<14)
354#define QSMCM_SCI_WOMS (1<<13)
355#define QSMCM_SCI_ILT (1<<12)
356#define QSMCM_SCI_PT (1<<11)
357#define QSMCM_SCI_PE (1<<10)
358#define QSMCM_SCI_M (1<<9)
359#define QSMCM_SCI_WAKE (1<<8)
361#define QSMCM_SCI_TIE (1<<7)
362#define QSMCM_SCI_TCIE (1<<6)
363#define QSMCM_SCI_RIE (1<<5)
364#define QSMCM_SCI_ILIE (1<<4)
365#define QSMCM_SCI_TE (1<<3)
366#define QSMCM_SCI_RE (1<<2)
367#define QSMCM_SCI_RWU (1<<1)
368#define QSMCM_SCI_SBK (1<<0)
370#define QSMCM_SCI_TDRE (1<<8)
371#define QSMCM_SCI_TC (1<<7)
372#define QSMCM_SCI_RDRF (1<<6)
373#define QSMCM_SCI_RAF (1<<5)
374#define QSMCM_SCI_IDLE (1<<4)
375#define QSMCM_SCI_OR (1<<3)
376#define QSMCM_SCI_NF (1<<2)
377#define QSMCM_SCI_FE (1<<1)
378#define QSMCM_SCI_PF (1<<0)
415 uint8_t _pad71[0x03C-0x034];
417 uint8_t _pad2[0x100-0x40];
423 uint8_t _pad7[0x140-0x120];
426 uint8_t _pad8[0x178-0x148];
428 uint8_t _pad9[0x200-0x17A];
437 uint8_t _pad11[0x220-0x20c];
450 uint8_t _pad15[0x280-0x24c];
462 uint8_t _pad16[0x300-0x292];
479 uint8_t _pad19[0x380-0x348];
487 uint8_t _pad20[0x400-0x38c];
490extern volatile usiu_t usiu;
551 uint8_t _pad10[0x14-0x10];
564 uint8_t _pad6C[0x140-0x06C];
566 uint16_t recram[0x20];
567 uint16_t tranram[0x20];
568 uint16_t comdram[0x20];
602 uint8_t _pad5200[0x6000-0x5200];
605 uint8_t _pad7800[0x7F80-0x7800];
609extern volatile imb_t imb;
615void clockOn(
void* unused);
616void clockOff(
void* unused);
617int clockIsOn(
void* unused);
rtems_isr Clock_isr(rtems_vector_number vector)
Clock_isr.
Definition: clockimpl.h:134
ISR_Handler rtems_isr
Return type for interrupt handler.
Definition: intr.h:52
ISR_Vector_number rtems_vector_number
Control block type used to manage the vectors.
Definition: intr.h:47