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mpc55xx.h
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1
9/*
10 * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
11 *
12 * embedded brains GmbH
13 * Obere Lagerstr. 30
14 * 82178 Puchheim
15 * Germany
16 * <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
38#ifndef LIBCPU_POWERPC_MPC55XX_H
39#define LIBCPU_POWERPC_MPC55XX_H
40
41#include <mpc55xx/regs.h>
42#include <mpc55xx/regs-mmu.h>
43
45
46#ifdef __cplusplus
47extern "C" {
48#endif /* __cplusplus */
49
50int mpc55xx_flash_copy(void *dest, const void *src, size_t nbytes);
51int mpc55xx_flash_copy_op(void *rdest, const void *src, size_t nbytes,
52 uint32_t opmask, uint32_t *p_fail_addr);
53int mpc55xx_flash_size(uint32_t *p_size);
54int mpc55xx_flash_writable(void);
55uint32_t mpc55xx_flash_address(void);
56void mpc55xx_flash_set_read_only(void);
57void mpc55xx_flash_set_read_write(void);
58
59int mpc55xx_physical_address(const void *addr, uint32_t *p_result);
60int mpc55xx_mapped_address(const void *addr, uint32_t *p_result);
61
62/* Bits for opmask. */
63#define MPC55XX_FLASH_BLANK_CHECK 0x01
64#define MPC55XX_FLASH_UNLOCK 0x02
65#define MPC55XX_FLASH_ERASE 0x04
66#define MPC55XX_FLASH_PROGRAM 0x08
67#define MPC55XX_FLASH_VERIFY 0x10
68
69/* Error returns. CONFIG or SIZE might mean you just
70 * need to check for new configuration bits.
71 * SIZE and RANGE mean you are outside of a known flash region.
72 * ERASE means the erase failed,
73 * PROGRAM means the program failed,
74 * BLANK means it wasn't blank and BLANK_CHECK was specified,
75 * VERIFY means VERIFY was set and it didn't match the source,
76 * and LOCK means either the locking failed or you needed to
77 * specify MPC55XX_FLASH_UNLOCK and didn't.
78 */
79#define MPC55XX_FLASH_CONFIG_ERR (-1)
80#define MPC55XX_FLASH_SIZE_ERR (-2)
81#define MPC55XX_FLASH_RANGE_ERR (-3)
82#define MPC55XX_FLASH_ERASE_ERR (-4)
83#define MPC55XX_FLASH_PROGRAM_ERR (-5)
84#define MPC55XX_FLASH_NOT_BLANK_ERR (-6)
85#define MPC55XX_FLASH_VERIFY_ERR (-7)
86#define MPC55XX_FLASH_LOCK_ERR (-8)
87
88#define MPC55XX_CACHE_ALIGNED_MASK ((uintptr_t) 0x1f)
89
90#define MPC55XX_CACHE_LINE_SIZE 32
91
95static inline int mpc55xx_is_cache_aligned( const void *s, size_t n)
96{
97 return !(((uintptr_t) s & MPC55XX_CACHE_ALIGNED_MASK) || (n & MPC55XX_CACHE_ALIGNED_MASK));
98}
99
100static inline uintptr_t mpc55xx_cache_aligned_start( const void *s)
101{
102 return ((uintptr_t) s & MPC55XX_CACHE_ALIGNED_MASK) ? (((uintptr_t) s & ~MPC55XX_CACHE_ALIGNED_MASK) + MPC55XX_CACHE_LINE_SIZE) : (uintptr_t)s;
103}
104
105static inline size_t mpc55xx_non_cache_aligned_size( const void *s)
106{
107 return (uintptr_t) mpc55xx_cache_aligned_start( s) - (uintptr_t) s;
108}
109
110static inline size_t mpc55xx_cache_aligned_size( const void *s, size_t n)
111{
112 return (n - mpc55xx_non_cache_aligned_size( s)) & ~MPC55XX_CACHE_ALIGNED_MASK;
113}
114
118static inline uint32_t mpc55xx_count_leading_zeros( uint32_t value)
119{
120 uint32_t count;
121 __asm__ (
122 "cntlzw %0, %1;"
123 : "=r" (count)
124 : "r" (value)
125 );
126 return count;
127}
128
129static inline void mpc55xx_wait_for_interrupt(void)
130{
131 #ifdef MPC55XX_HAS_WAIT_INSTRUCTION
132 __asm__ volatile ("wait");
133 #else
134 __asm__ volatile ("");
135 #endif
136}
137
138static inline void mpc55xx_mmu_apply_config(const struct MMU_tag *config)
139{
140 PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS0, config->MAS0.R);
141 PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1, config->MAS1.R);
142 PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS2, config->MAS2.R);
143 PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS3, config->MAS3.R);
144 __asm__ volatile ("tlbwe");
145}
146
147#ifdef __cplusplus
148}
149#endif /* __cplusplus */
150
151#endif /* LIBCPU_POWERPC_MPC55XX_H */
#define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val)
Sets the Special Purpose Register with number spr to the value in val.
Definition: powerpc-utility.h:576
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
General purpose assembler macros, linker command file support and some inline functions for direct re...
Register definitions for the MPC55xx and MPC56xx microcontroller family.
Definition: regs-mmu.h:66
Definition: deflate.c:115