RTEMS 5.2
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cpuimpl.h
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1
7/*
8 * Copyright (c) 2013 embedded brains GmbH
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifndef _RTEMS_SCORE_CPUIMPL_H
16#define _RTEMS_SCORE_CPUIMPL_H
17
18#include <rtems/score/cpu.h>
19
30#define CPU_PER_CPU_CONTROL_SIZE 0
31
32#ifndef ASM
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
39{
40 /* TODO */
41}
42
43RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
44{
45 while (1) {
46 /* TODO */
47 }
48}
49
51{
52 __asm__ volatile ( "illegal" );
53}
54
56{
57 __asm__ volatile ( "nop" );
58}
59
60#ifdef __cplusplus
61}
62#endif
63
64#endif /* ASM */
65
68#endif /* _RTEMS_SCORE_CPUIMPL_H */
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66
RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal(void)
Emits an illegal instruction.
Definition: cpuimpl.h:122
RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation(void)
Emits a no operation instruction (nop).
Definition: cpuimpl.h:132
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.