RTEMS 5.2
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l2c.h
1/*
2 * GRLIB L2CACHE Driver
3 *
4 * COPYRIGHT (c) 2017
5 * Cobham Gaisler AB
6 *
7 * The license and distribution terms for this file may be
8 * found in the file LICENSE in this distribution or at
9 * http://www.rtems.org/license/LICENSE.
10 *
11 * OVERVIEW
12 * ========
13 * This driver controls the L2CACHE device located
14 * at an on-chip AMBA.
15 */
16
17#ifndef __L2CACHE_H__
18#define __L2CACHE_H__
19
20#include <stdint.h>
21#include <stdio.h>
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27extern void l2cache_register_drv(void);
28
29#define L2CACHE_ERR_OK 0
30#define L2CACHE_ERR_NOINIT -1
31#define L2CACHE_ERR_EINVAL -2
32#define L2CACHE_ERR_TOOMANY -3
33#define L2CACHE_ERR_ERROR -4
34
35/* L2C Flush options */
36#define L2CACHE_OPTIONS_FLUSH_WAIT (0x1 << 2)
37#define L2CACHE_OPTIONS_FLUSH_INVALIDATE (0x3 << 0)
38#define L2CACHE_OPTIONS_FLUSH_WRITEBACK (0x2 << 0)
39#define L2CACHE_OPTIONS_FLUSH_INV_WBACK (0x1 << 0)
40#define L2CACHE_OPTIONS_FLUSH_NONE (0 << 0)
41
42/* L2C Status */
43#define L2CACHE_STATUS_ENABLED 1
44#define L2CACHE_STATUS_SPLIT_ENABLED (0x1 << 1)
45#define L2CACHE_STATUS_EDAC_ENABLED (0x1 << 2)
46#define L2CACHE_STATUS_REPL (0x3 << L2CACHE_STATUS_REPL_BIT)
47#define L2CACHE_STATUS_REPL_BIT 3
48#define L2CACHE_STATUS_WRITETHROUGH (0x1 << 5)
49#define L2CACHE_STATUS_LOCK (0xf << L2CACHE_STATUS_LOCK_BIT)
50#define L2CACHE_STATUS_LOCK_BIT 6
51#define L2CACHE_STATUS_SCRUB_ENABLED (0x1 << 10)
52#define L2CACHE_STATUS_INT (0xf << L2CACHE_STATUS_INT_BIT)
53#define L2CACHE_STATUS_INT_BIT 11
54#define L2CACHE_STATUS_INT_BCKEND (0x1 << 11)
55#define L2CACHE_STATUS_INT_WPHIT (0x1 << 12)
56#define L2CACHE_STATUS_INT_UEE (0x1 << 13)
57#define L2CACHE_STATUS_INT_CEE (0x1 << 14)
58#define L2CACHE_STATUS_SCRUB_DELAY (0xffff << L2CACHE_STATUS_SCRUB_DELAY_BIT)
59#define L2CACHE_STATUS_SCRUB_DELAY_BIT 15
60#define L2CACHE_STATUS_SIGN_BIT 31
61
62/* status helper macros */
63#define L2CACHE_ENABLED(status) (status & L2CACHE_STATUS_ENABLED)
64#define L2CACHE_DISABLED(status) (!(status & L2CACHE_STATUS_ENABLED))
65#define L2CACHE_SPLIT_ENABLED(status) (status & L2CACHE_STATUS_SPLIT_ENABLED)
66#define L2CACHE_SPLIT_DISABLED(status) \
67 (!(status & L2CACHE_STATUS_SPLIT_ENABLED))
68#define L2CACHE_EDAC_ENABLED(status) (status & L2CACHE_STATUS_EDAC_ENABLED)
69#define L2CACHE_EDAC_DISABLED(status) (!(status & L2CACHE_STATUS_EDAC_ENABLED))
70#define L2CACHE_REPL(status) \
71 ((status & L2CACHE_STATUS_REPL) >> L2CACHE_STATUS_REPL_BIT)
72#define L2CACHE_WRITETHROUGH(status) (status & L2CACHE_STATUS_WRITETHROUGH)
73#define L2CACHE_WRITEBACK(status) (!(status & L2CACHE_STATUS_WRITETHROUGH))
74#define L2CACHE_LOCKED_WAYS(status) \
75 ((status & L2CACHE_STATUS_LOCK) >> L2CACHE_STATUS_LOCK_BIT)
76#define L2CACHE_SCRUB_ENABLED(status) (status & L2CACHE_STATUS_SCRUB_ENABLED)
77#define L2CACHE_SCRUB_DISABLED(status) \
78 (!(status & L2CACHE_STATUS_SCRUB_ENABLED))
79#define L2CACHE_SCRUB_DELAY(status) \
80 ((status & L2CACHE_STATUS_SCRUB_DELAY) >> L2CACHE_STATUS_SCRUB_DELAY_BIT)
81#define L2CACHE_INT_ENABLED(status) (status & L2CACHE_STATUS_INT)
82#define L2CACHE_INT_DISABLED(status) (!(status & L2CACHE_STATUS_INT))
83extern int l2cache_status(void);
84
85/* L2C Setup */
86extern int l2cache_enable(int flush);
87extern int l2cache_disable(int flush);
88
89extern int l2cache_split_enable(void);
90extern int l2cache_split_disable(void);
91
92extern int l2cache_edac_enable(int flush);
93extern int l2cache_edac_disable(int flush);
94
95extern int l2cache_scrub_enable(int delay);
96extern int l2cache_scrub_disable(void);
97extern int l2cache_scrub_line(int way, int index);
98
99extern int l2cache_writethrough(int flush);
100extern int l2cache_writeback(int flush);
101
102#define L2CACHE_OPTIONS_REPL_INDEX_WAY_BIT (2)
103#define L2CACHE_OPTIONS_REPL_MASTERIDX_MOD (3 << 0)
104#define L2CACHE_OPTIONS_REPL_MASTERIDX_IDX (2 << 0)
105#define L2CACHE_OPTIONS_REPL_RANDOM (1 << 0)
106#define L2CACHE_OPTIONS_REPL_LRU (0 << 0)
107extern int l2cache_replacement(int options, int flush);
108
109/* L2C Flush */
110extern int l2cache_flush(int flush);
111extern int l2cache_flush_address(uint32_t addr, int size, int flush);
112extern int l2cache_flush_line(int way, int index, int flush);
113extern int l2cache_flush_way(int way, int flush);
114
115/* L2C Lock way */
116#define L2CACHE_OPTIONS_DIRTY (0x1 << 2)
117#define L2CACHE_OPTIONS_VALID (0x1 << 1)
118#define L2CACHE_OPTIONS_FETCH (0x1 << 0)
119#define L2CACHE_OPTIONS_DISABLE 2
120#define L2CACHE_OPTIONS_ENABLE 1
121#define L2CACHE_OPTIONS_NONE 0
122extern int l2cache_lock_way(uint32_t tag, int options, int flush, int enable);
123extern int l2cache_unlock(void);
124
125/* L2C Fill a way */
126extern int l2cache_fill_way(int way, uint32_t tag, int options, int flush);
127
128/* L2C MTRR */
129#define L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH (0x1 << 2)
130#define L2CACHE_OPTIONS_MTRR_ACCESS_UNCACHED (0x0 << 2)
131#define L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE (0x1 << 1)
132#define L2CACHE_OPTIONS_MTRR_WRITEPROT_DISABLE (0x0 << 1)
133extern int l2cache_mtrr_enable(int id, uint32_t addr, uint32_t mask,
134 int options, int flush);
135extern int l2cache_mtrr_disable(int id);
136
137/* L2C Debug print */
138extern int l2cache_print(void);
139
140/* L2C Interrupts */
141/* Function Interrupt-Code ISR callback prototype.
142 * arg - Custom arg provided by user
143 * addr - Cacheline addr that generated the error
144 * status - Error status register of the L2CACHE core
145 */
146typedef void (*l2cache_isr_t)(void *arg, uint32_t addr, uint32_t status);
147#define L2CACHE_INTERRUPT_ALL (0xf << 0)
148#define L2CACHE_INTERRUPT_BACKENDERROR (0x1 << 3)
149#define L2CACHE_INTERRUPT_WPROTHIT (0x1 << 2)
150#define L2CACHE_INTERRUPT_UNCORRERROR (0x1 << 1)
151#define L2CACHE_INTERRUPT_CORRERROR (0x1 << 0)
152extern int l2cache_isr_register( l2cache_isr_t isr, void * arg, int options);
153extern int l2cache_isr_unregister(void);
154extern int l2cache_interrupt_mask(int options);
155extern int l2cache_interrupt_unmask(int options);
156
157/* L2C error interface */
158#define L2CACHE_STATUS_MULTIPLEERRORS 2
159#define L2CACHE_STATUS_NEWERROR 1
160#define L2CACHE_STATUS_NOERROR 0
161extern int l2cache_error_status(uint32_t * addr, uint32_t * status);
162
163/*#define TEST_L2CACHE*/
164#ifdef TEST_L2CACHE
165/* Used for internal testing */
166/*
167 * L2CACHE Tag private data struture
168 */
169struct l2cache_tag {
170 uint32_t tag;
171 int valid;
172 int dirty;
173 int lru;
174};
175
176/*
177 * L2CACHE Line private data struture
178 */
179struct l2cache_dataline {
180 uint32_t data[16];
181 int words;
182};
183extern int l2cache_get_index( uint32_t addr);
184extern uint32_t l2cache_get_tag( uint32_t addr);
185
186extern int l2cache_diag_tag( int way, int index, struct l2cache_tag * tag);
187extern int l2cache_diag_line( int way, int index,
188 struct l2cache_dataline * dataline);
189
190#define L2CACHE_HIT 1
191#define L2CACHE_MISS 0
192extern int l2cache_lookup(uint32_t addr, int * way);
193
194extern int l2cache_error_inject_address( uint32_t addr, uint32_t mask);
195#endif /* TEST_L2CACHE */
196
197#ifdef __cplusplus
198}
199#endif
200
201#endif /* __L2CACHE_H__ */
size
unsigned size
Definition: tte.h:1
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