RTEMS 5.2
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imx_gpcreg.h
1/*
2 * Copyright (c) 2017 embedded brains GmbH. All rights reserved.
3 *
4 * embedded brains GmbH
5 * Dornierstr. 4
6 * 82178 Puchheim
7 * Germany
8 * <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifndef IMX_GPCREG_H
16#define IMX_GPCREG_H
17
18#include <bsp/utility.h>
19
20typedef struct {
21 uint32_t lpcr_a7_bsc;
22 uint32_t lpcr_a7_ad;
23 uint32_t lpcr_m4;
24 uint32_t reserved_0c[2];
25 uint32_t slpcr;
26 uint32_t reserved_18[2];
27 uint32_t mlpcr;
28 uint32_t pgc_ack_sel_a7;
29 uint32_t pgc_ack_sel_m4;
30 uint32_t misc;
31 uint32_t imr1_core0_a7;
32 uint32_t imr2_core0_a7;
33 uint32_t imr3_core0_a7;
34 uint32_t imr4_core0_a7;
35 uint32_t imr1_core1_a7;
36 uint32_t imr2_core1_a7;
37 uint32_t imr3_core1_a7;
38 uint32_t imr4_core1_a7;
39 uint32_t imr1_m4;
40 uint32_t imr2_m4;
41 uint32_t imr3_m4;
42 uint32_t imr4_m4;
43 uint32_t reserved_60[4];
44 uint32_t isr1_a7;
45 uint32_t isr2_a7;
46 uint32_t isr3_a7;
47 uint32_t isr4_a7;
48 uint32_t isr1_m4;
49 uint32_t isr2_m4;
50 uint32_t isr3_m4;
51 uint32_t isr4_m4;
52 uint32_t reserved_90[8];
53 uint32_t slt0_cfg;
54 uint32_t slt1_cfg;
55 uint32_t slt2_cfg;
56 uint32_t slt3_cfg;
57 uint32_t slt4_cfg;
58 uint32_t slt5_cfg;
59 uint32_t slt6_cfg;
60 uint32_t slt7_cfg;
61 uint32_t slt8_cfg;
62 uint32_t slt9_cfg;
63 uint32_t reserved_d8[5];
64 uint32_t pgc_cpu_mapping;
65#define IMX_GPC_CPU_PGC_SCU_A7 BSP_BIT32(2)
66#define IMX_GPC_CPU_PGC_CORE1_A7 BSP_BIT32(1)
67#define IMX_GPC_CPU_PGC_CORE0_A7 BSP_BIT32(0)
68#define IMX_GPC_PU_PGC_USB_HSIC_PHY BSP_BIT32(4)
69#define IMX_GPC_PU_PGC_USB_OTG2_PHY BSP_BIT32(3)
70#define IMX_GPC_PU_PGC_USB_OTG1_PHY BSP_BIT32(2)
71#define IMX_GPC_PU_PGC_PCIE_PHY BSP_BIT32(1)
72#define IMX_GPC_PU_PGC_MIPI_PHY BSP_BIT32(0)
73 uint32_t cpu_pgc_sw_pup_req;
74 uint32_t reserved_f4;
75 uint32_t pu_pgc_sw_pup_req;
76 uint32_t cpu_pgc_sw_pdn_req;
77 uint32_t reserved_100;
78 uint32_t pu_pgc_sw_pdn_req;
79 uint32_t reserved_108[10];
80 uint32_t cpu_pgc_pup_status1;
81 uint32_t a7_mix_pgc_pup_status0;
82 uint32_t a7_mix_pgc_pup_status1;
83 uint32_t a7_mix_pgc_pup_status2;
84 uint32_t m4_mix_pgc_pup_status0;
85 uint32_t m4_mix_pgc_pup_status1;
86 uint32_t m4_mix_pgc_pup_status2;
87 uint32_t a7_pu_pgc_pup_status0;
88 uint32_t a7_pu_pgc_pup_status1;
89 uint32_t a7_pu_pgc_pup_status2;
90 uint32_t m4_pu_pgc_pup_status0;
91 uint32_t m4_pu_pgc_pup_status1;
92 uint32_t m4_pu_pgc_pup_status2;
93 uint32_t reserved_164[3];
94 uint32_t cpu_pgc_pdn_status1;
95 uint32_t reserved_174[6];
96 uint32_t a7_pu_pgc_pdn_status0;
97 uint32_t a7_pu_pgc_pdn_status1;
98 uint32_t a7_pu_pgc_pdn_status2;
99 uint32_t m4_pu_pgc_pdn_status0;
100 uint32_t m4_pu_pgc_pdn_status1;
101 uint32_t m4_pu_pgc_pdn_status2;
102 uint32_t reserved_1a4[3];
103 uint32_t a7_mix_pdn_flg;
104 uint32_t a7_pu_pdn_flg;
105 uint32_t m4_mix_pdn_flg;
106 uint32_t m4_pu_pdn_flg;
107#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(val) BSP_FLD32(val, 24, 29)
108#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_GET(reg) BSP_FLD32GET(reg, 24, 29)
109#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29)
110#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR(val) BSP_FLD32(val, 16, 21)
111#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_GET(reg) BSP_FLD32GET(reg, 16, 21)
112#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21)
113#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1(val) BSP_FLD32(val, 8, 13)
114#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_GET(reg) BSP_FLD32GET(reg, 8, 13)
115#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
116#define IMX_GPC_PGC_CTRL_L2RSTDIS(val) BSP_FLD32(val, 1, 6)
117#define IMX_GPC_PGC_CTRL_L2RSTDIS_GET(reg) BSP_FLD32GET(reg, 1, 6)
118#define IMX_GPC_PGC_CTRL_L2RSTDIS_SET(reg, val) BSP_FLD32SET(reg, val, 1, 6)
119#define IMX_GPC_PGC_CTRL_PCR BSP_BIT32(0)
120 uint32_t reserved_1c0[400];
121 uint32_t pgc_a7core0_ctrl;
122 uint32_t pgc_a7core0_pupscr;
123 uint32_t pgc_a7core0_pdnscr;
124 uint32_t pgc_a7core0_sr;
125 uint32_t reserved_810[12];
126 uint32_t pgc_a7core1_ctrl;
127 uint32_t pgc_a7core1_pupscr;
128 uint32_t pgc_a7core1_pdnscr;
129 uint32_t pgc_a7core1_sr;
130 uint32_t reserved_850[12];
131 uint32_t pgc_a7scu_ctrl;
132 uint32_t pgc_a7scu_pupscr;
133 uint32_t pgc_a7scu_pdnscr;
134 uint32_t pgc_a7scu_sr;
135 uint32_t pgc_scu_auxsw;
136 uint32_t reserved_894[11];
137 uint32_t pgc_mix_ctrl;
138 uint32_t pgc_mix_pupscr;
139 uint32_t pgc_mix_pdnscr;
140 uint32_t pgc_mix_sr;
141 uint32_t reserved_8d0[12];
142 uint32_t pgc_mipi_ctrl;
143 uint32_t pgc_mipi_pupscr;
144 uint32_t pgc_mipi_pdnscr;
145 uint32_t pgc_mipi_sr;
146 uint32_t reserved_910[12];
147 uint32_t pgc_pcie_ctrl;
148 uint32_t pgc_pcie_pupscr;
149 uint32_t pgc_pcie_pdnscr;
150 uint32_t pgc_pcie_sr;
151 uint32_t reserved_950[176];
152 uint32_t pgc_mipi_auxsw;
153 uint32_t reserved_c14[15];
154 uint32_t pgc_pcie_auxsw;
155 uint32_t reserved_c54[43];
156 uint32_t pgc_hsic_ctrl;
157 uint32_t pgc_hsic_pupscr;
158 uint32_t pgc_hsic_pdnscr;
159 uint32_t pgc_hsic_sr;
160} imx_gpc;
161
162#endif /* IMX_GPCREG_H */
utility.h
Utility macros.
imx_gpc
Definition: imx_gpcreg.h:20
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