RTEMS
5.2
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bsps
powerpc
beatnik
net
if_em
rtemscompat_defs.h
1
#ifndef RTEMS_COMPAT_DEFS_H
2
#define RTEMS_COMPAT_DEFS_H
3
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/* Number of device instances the driver should support
5
* - may be limited to 1 depending on IRQ API
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* (braindamaged PC586 and powerpc)
7
*/
8
#define NETDRIVER_SLOTS 1
9
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/* String name to print with error messages */
11
#define NETDRIVER "em"
12
/* Name snippet used to make global symbols unique to this driver */
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#define NETDRIVER_PREFIX em
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#define adapter em_softc
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#define interface_data arpcom
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/* Define according to endianness of the *ethernet*chip*
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* (not the CPU - most probably are LE)
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* This must be either NET_CHIP_LE or NET_CHIP_BE
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*/
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#define NET_CHIP_LE
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#undef NET_CHIP_BE
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/* Define either NET_CHIP_MEM_IO or NET_CHIP_PORT_IO,
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* depending whether the CPU sees it in memory address space
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* or (e.g. x86) uses special I/O instructions.
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*/
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#define NET_CHIP_MEM_IO
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#undef NET_CHIP_PORT_IO
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/* The name of the hijacked 'bus handle' field in the softc
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* structure. We use this field to store the chip's base address.
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*/
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#define NET_SOFTC_BHANDLE_FIELD osdep.mem_bus_space_handle
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/* define the names of the 'if_XXXreg.h' and 'if_XXXvar.h' headers
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* (only if present, i.e., if the BSDNET driver has no respective
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* header, leave this undefined).
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*
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*/
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#define IF_REG_HEADER "../if_em/if_em.h"
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#undef IF_VAR_HEADER
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/* define if a pci device */
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#define NETDRIVER_PCI <bsp/pci.h>
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/* Macros to disable and enable interrupts, respectively.
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* The 'disable' macro is expanded in the ISR, the 'enable'
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* macro is expanded in the driver task.
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* The global network semaphore usually provides mutex
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* protection of the device registers.
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* Special care must be taken when coding the 'disable' macro,
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* however to MAKE SURE THERE ARE NO OTHER SIDE EFFECTS such
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* as:
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* - macro must not clear any status flags
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* - macro must save/restore any context information
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* (e.g., a address register pointer or a bank switch register)
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*
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* ARGUMENT: the macro arg is a pointer to the driver's 'softc' structure
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*/
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#define NET_ENABLE_IRQS(sc) do { \
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E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); \
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} while (0)
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#define NET_DISABLE_IRQS(sc) do { \
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E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); \
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} while (0)
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#define KASSERT(a...) do {} while (0)
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/* dmamap stuff; these are defined just to work with the current version
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* of this driver and the implementation must be carefully checked if
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* a newer version is merged.!
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*
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* The more cumbersome routines have been commented in the source, the
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* simpler ones are defined to be NOOPs here so the source gets less
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* cluttered...
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*
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* ASSUMPTIONS:
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*
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* -> dmamap_sync cannot sync caches; assume we have HW snooping
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*
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*/
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typedef
unsigned
bus_size_t;
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typedef
unsigned
bus_addr_t;
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91
typedef
struct
{
92
unsigned
ds_addr;
93
unsigned
ds_len;
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}
bus_dma_segment_t
;
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#define bus_dma_tag_destroy(args...) do {} while(0)
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#define bus_dmamap_destroy(args...) do {} while(0)
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#define bus_dmamap_unload(args...) do {} while (0)
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#ifdef __PPC__
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#define bus_dmamap_sync(args...) do { __asm__ volatile("sync"
:::"memory"); } while (0)
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#else
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#define bus_dmamap_sync(args...) do {} while (0)
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#endif
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#define BUS_DMA_NOWAIT 0xdeadbeef
/* unused */
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#define em_adapter_list _bsd_em_adapter_list
111
#define em_arc_subsystem_valid _bsd_em_arc_subsystem_valid
112
#define em_check_downshift _bsd_em_check_downshift
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#define em_check_for_link _bsd_em_check_for_link
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#define em_check_mng_mode _bsd_em_check_mng_mode
115
#define em_check_phy_reset_block _bsd_em_check_phy_reset_block
116
#define em_check_polarity _bsd_em_check_polarity
117
#define em_cleanup_led _bsd_em_cleanup_led
118
#define em_clear_hw_cntrs _bsd_em_clear_hw_cntrs
119
#define em_clear_vfta _bsd_em_clear_vfta
120
#define em_commit_shadow_ram _bsd_em_commit_shadow_ram
121
#define em_config_collision_dist _bsd_em_config_collision_dist
122
#define em_config_dsp_after_link_change _bsd_em_config_dsp_after_link_change
123
#define em_config_fc_after_link_up _bsd_em_config_fc_after_link_up
124
#define em_dbg_config _bsd_em_dbg_config
125
#define em_detect_gig_phy _bsd_em_detect_gig_phy
126
#define em_disable_pciex_master _bsd_em_disable_pciex_master
127
#define em_display_debug_stats _bsd_em_display_debug_stats
128
#define em_driver_version _bsd_em_driver_version
129
#define em_enable_mng_pass_thru _bsd_em_enable_mng_pass_thru
130
#define em_enable_pciex_master _bsd_em_enable_pciex_master
131
#define em_enable_tx_pkt_filtering _bsd_em_enable_tx_pkt_filtering
132
#define em_force_mac_fc _bsd_em_force_mac_fc
133
#define em_get_auto_rd_done _bsd_em_get_auto_rd_done
134
#define em_get_bus_info _bsd_em_get_bus_info
135
#define em_get_cable_length _bsd_em_get_cable_length
136
#define em_get_hw_eeprom_semaphore _bsd_em_get_hw_eeprom_semaphore
137
#define em_get_phy_cfg_done _bsd_em_get_phy_cfg_done
138
#define em_get_speed_and_duplex _bsd_em_get_speed_and_duplex
139
#define em_hash_mc_addr _bsd_em_hash_mc_addr
140
#define em_hw_early_init _bsd_em_hw_early_init
141
#define em_id_led_init _bsd_em_id_led_init
142
#define em_init_eeprom_params _bsd_em_init_eeprom_params
143
#define em_init_hw _bsd_em_init_hw
144
#define em_init_rx_addrs _bsd_em_init_rx_addrs
145
#define em_io_read _bsd_em_io_read
146
#define em_io_write _bsd_em_io_write
147
#define em_is_onboard_nvm_eeprom _bsd_em_is_onboard_nvm_eeprom
148
#define em_led_off _bsd_em_led_off
149
#define em_led_on _bsd_em_led_on
150
#define em_mc_addr_list_update _bsd_em_mc_addr_list_update
151
#define em_mng_enable_host_if _bsd_em_mng_enable_host_if
152
#define em_mng_host_if_write _bsd_em_mng_host_if_write
153
#define em_mng_write_cmd_header _bsd_em_mng_write_cmd_header
154
#define em_mng_write_commit _bsd_em_mng_write_commit
155
#define em_mng_write_dhcp_info _bsd_em_mng_write_dhcp_info
156
#define em_mta_set _bsd_em_mta_set
157
#define em_pci_clear_mwi _bsd_em_pci_clear_mwi
158
#define em_pci_set_mwi _bsd_em_pci_set_mwi
159
#define em_phy_get_info _bsd_em_phy_get_info
160
#define em_phy_hw_reset _bsd_em_phy_hw_reset
161
#define em_phy_igp_get_info _bsd_em_phy_igp_get_info
162
#define em_phy_m88_get_info _bsd_em_phy_m88_get_info
163
#define em_phy_reset _bsd_em_phy_reset
164
#define em_phy_setup_autoneg _bsd_em_phy_setup_autoneg
165
#define em_poll_eerd_eewr_done _bsd_em_poll_eerd_eewr_done
166
#define em_put_hw_eeprom_semaphore _bsd_em_put_hw_eeprom_semaphore
167
#define em_rar_set _bsd_em_rar_set
168
#define em_read_eeprom _bsd_em_read_eeprom
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#define em_read_eeprom_eerd _bsd_em_read_eeprom_eerd
170
#define em_read_mac_addr _bsd_em_read_mac_addr
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#define em_read_part_num _bsd_em_read_part_num
172
#define em_read_pci_cfg _bsd_em_read_pci_cfg
173
#define em_read_phy_reg _bsd_em_read_phy_reg
174
#define em_read_reg_io _bsd_em_read_reg_io
175
#define em_reset_adaptive _bsd_em_reset_adaptive
176
#define em_reset_hw _bsd_em_reset_hw
177
#define em_set_d0_lplu_state _bsd_em_set_d0_lplu_state
178
#define em_set_d3_lplu_state _bsd_em_set_d3_lplu_state
179
#define em_set_mac_type _bsd_em_set_mac_type
180
#define em_set_media_type _bsd_em_set_media_type
181
#define em_set_pci_express_master_disable _bsd_em_set_pci_express_master_disable
182
#define em_setup_led _bsd_em_setup_led
183
#define em_setup_link _bsd_em_setup_link
184
#define em_tbi_adjust_stats _bsd_em_tbi_adjust_stats
185
#define em_update_adaptive _bsd_em_update_adaptive
186
#define em_update_eeprom_checksum _bsd_em_update_eeprom_checksum
187
#define em_validate_eeprom_checksum _bsd_em_validate_eeprom_checksum
188
#define em_validate_mdi_setting _bsd_em_validate_mdi_setting
189
#define em_wait_autoneg _bsd_em_wait_autoneg
190
#define em_write_eeprom _bsd_em_write_eeprom
191
#define em_write_eeprom_eewr _bsd_em_write_eeprom_eewr
192
#define em_write_pci_cfg _bsd_em_write_pci_cfg
193
#define em_write_phy_reg _bsd_em_write_phy_reg
194
#define em_write_reg_io _bsd_em_write_reg_io
195
#define em_write_vfta _bsd_em_write_vfta
196
#define the_em_devs _bsd_the_em_devs
197
198
#endif
bus_dma_segment_t
Definition:
rtemscompat_defs.h:91
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