RTEMS 5.2
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sc16is752.h
1/*
2 * Copyright (c) 2016 embedded brains GmbH. All rights reserved.
3 *
4 * embedded brains GmbH
5 * Dornierstr. 4
6 * 82178 Puchheim
7 * Germany
8 * <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifndef _DEV_SERIAL_SC16IS752_H
16#define _DEV_SERIAL_SC16IS752_H
17
18#include <sys/ioccom.h>
19
20#include <rtems/termiostypes.h>
21
22#ifdef __cplusplus
23extern "C" {
24#endif /* __cplusplus */
25
32typedef enum {
33 SC16IS752_MODE_RS232,
34
35 /* Enable RS485 mode */
36 SC16IS752_MODE_RS485,
37
38 /* Enable RS485 mode, enable the transmitter to control the #RTS pin */
39 SC16IS752_MODE_RS485_RTS,
40
41 /*
42 * Enable RS485 mode, enable the transmitter to control the #RTS pin, invert
43 * RTS signal (#RTS = 1 during transmission and #RTS = 0 during reception)
44 */
45 SC16IS752_MODE_RS485_RTS_INV
46} sc16is752_mode;
47
49
55
61 int (*write_reg)(
63 uint8_t addr,
64 const uint8_t *data,
65 size_t len
66 );
67
73 int (*read_reg)(
75 uint8_t addr,
76 uint8_t *data,
77 size_t len
78 );
79
85 int (*read_2_reg)(
87 uint8_t addr_0,
88 uint8_t addr_1,
89 uint8_t data[2]
90 );
91
98
105
112
119
125 sc16is752_mode mode;
126
134
141
147 uint8_t ier;
148
155
162
168 uint8_t lcr;
169
175 uint8_t efcr;
176};
177
181typedef struct {
183
189 int fd;
190
196 uint8_t cs;
197
203 uint32_t speed_hz;
204
210 const char *spi_path;
212
216typedef struct {
218
224 int fd;
225
231 const char *bus_path;
233
234const rtems_termios_device_handler sc16is752_termios_handler;
235
241void sc16is752_interrupt_handler(void *arg);
242
252rtems_status_code sc16is752_spi_create(
254 const char *device_path
255);
256
262#define SC16IS752_SET_SLEEP_MODE _IOW('d', 0, int)
263
270#define SC16IS752_SET_IOCONTROL _IOW('d', 1, uint8_t)
271
275#define SC16IS752_SET_IODIR _IOW('d', 2, uint8_t)
276
280#define SC16IS752_SET_IOSTATE _IOW('d', 3, uint8_t)
281
285#define SC16IS752_SET_EFCR _IOW('d', 4, uint8_t)
286
290#define SC16IS752_GET_SLEEP_MODE _IOR('d', 0, int)
291
295#define SC16IS752_GET_IOCONTROL _IOR('d', 1, uint8_t)
296
300#define SC16IS752_GET_IODIR _IOR('d', 2, uint8_t)
301
305#define SC16IS752_GET_IOSTATE _IOR('d', 3, uint8_t)
306
310#define SC16IS752_GET_EFCR _IOR('d', 4, uint8_t)
311
316#define SC16IS752_IOCONTROL_SRESET (1u << 3)
317#define SC16IS752_IOCONTROL_GPIO_3_0_OR_MODEM (1u << 2)
318#define SC16IS752_IOCONTROL_GPIO_7_4_OR_MODEM (1u << 1)
319#define SC16IS752_IOCONTROL_IOLATCH (1u << 0)
324#ifdef __cplusplus
325}
326#endif /* __cplusplus */
327
328#endif /* _DEV_SERIAL_SC16IS752_H */
rtems_status_code
Classic API Status.
Definition: status.h:43
Termios device context.
Definition: termiostypes.h:75
Termios device handler.
Definition: termiostypes.h:141
Definition: termiostypes.h:283
SC16IS752 device context.
Definition: sc16is752.h:53
uint8_t ier
Shadow Interrupt Enable Register (IER).
Definition: sc16is752.h:147
uint32_t input_frequency
Input frequency in Hertz (dependent on crystal, see XTAL1 and XTAL2 pins).
Definition: sc16is752.h:133
rtems_termios_tty * tty
Corresponding Termios structure.
Definition: sc16is752.h:140
uint8_t tx_fifo_free
Count of free characters in the transmit FIFO.
Definition: sc16is752.h:161
void(* last_close)(sc16is752_context *ctx)
Last close.
Definition: sc16is752.h:104
int(* write_reg)(sc16is752_context *ctx, uint8_t addr, const uint8_t *data, size_t len)
Writes a register.
Definition: sc16is752.h:61
int(* read_2_reg)(sc16is752_context *ctx, uint8_t addr_0, uint8_t addr_1, uint8_t data[2])
Reads two registers.
Definition: sc16is752.h:85
int(* read_reg)(sc16is752_context *ctx, uint8_t addr, uint8_t *data, size_t len)
Reads a register.
Definition: sc16is752.h:73
uint8_t tx_in_progress
Characters placed into transmit FIFO.
Definition: sc16is752.h:154
void(* remove_irq)(sc16is752_context *ctx)
Shall remove the interrupt handler.
Definition: sc16is752.h:118
bool(* install_irq)(sc16is752_context *ctx)
Shall install the interrupt handler.
Definition: sc16is752.h:111
sc16is752_mode mode
Device mode.
Definition: sc16is752.h:125
bool(* first_open)(sc16is752_context *ctx)
First open.
Definition: sc16is752.h:97
uint8_t lcr
Shadow Line Control Register (LCR).
Definition: sc16is752.h:168
uint8_t efcr
Shadow Extra Features Control Register (EFCR).
Definition: sc16is752.h:175
SC16IS752 I2C context.
Definition: sc16is752.h:216
const char * bus_path
The I2C bus device path.
Definition: sc16is752.h:231
int fd
The I2C bus device file descriptor.
Definition: sc16is752.h:224
SC16IS752 SPI context.
Definition: sc16is752.h:181
const char * spi_path
The SPI bus device path.
Definition: sc16is752.h:210
uint32_t speed_hz
The SPI bus speed in Hertz.
Definition: sc16is752.h:203
uint8_t cs
The SPI device chip select.
Definition: sc16is752.h:196
int fd
The SPI bus device file descriptor.
Definition: sc16is752.h:189