alt_qspi.h

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/******************************************************************************
*
* Copyright 2013 Altera Corporation. All Rights Reserved.
* 
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
* 
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
* 
******************************************************************************/
 
/******************************************************************************
* 
* !!!! Customer Be Aware, Exception!!!
*
* 1. Qspi Direct Access Mode is not working!
*
*    This is because the qspi flash memory installed on our DevKit board, Micro 
*    part N25Q00xx, 8 Gb, is not completely compatible with our embedded Synopsis 
*    QSPI controller IP. Therefore there is no viable direct access code offered
*    in the lib.  All the memory rea/write functionality is offered with indirect
*    access only.   
*
*    Should you install a different flash memory part in your custom board, and 
*    wondering wether direct access mode works, please contact with us.
* 
******************************************************************************/
 
#ifndef __ALT_QSPI_H__
#define __ALT_QSPI_H__
 
#include <bsp/hwlib.h>
 
#ifdef __cplusplus
extern "C"
{
#endif  /* __cplusplus */
 
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_init(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_uninit(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_disable(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_enable(void);
 
/******************************************************************************/
typedef enum ALT_QSPI_INT_STATUS_e
{
    ALT_QSPI_INT_STATUS_MODE_FAIL         = (0x1 << 0),
 
    ALT_QSPI_INT_STATUS_UFL               = (0x1 << 1),
 
    ALT_QSPI_INT_STATUS_IDAC_OP_COMPLETE  = (0x1 << 2),
 
    ALT_QSPI_INT_STATUS_IDAC_OP_REJECT    = (0x1 << 3),
 
    ALT_QSPI_INT_STATUS_WR_PROT_VIOL      = (0x1 << 4),
 
    ALT_QSPI_INT_STATUS_ILL_AHB_ACCESS    = (0x1 << 5),
 
    ALT_QSPI_INT_STATUS_IDAC_WTRMK_TRIG   = (0x1 << 6),
 
    ALT_QSPI_INT_STATUS_RX_OVF            = (0x1 << 7),
 
    ALT_QSPI_INT_STATUS_TX_FIFO_NOT_FULL  = (0x1 << 8),
 
    ALT_QSPI_INT_STATUS_TX_FIFO_FULL      = (0x1 << 9),
 
    ALT_QSPI_INT_STATUS_RX_FIFO_NOT_EMPTY = (0x1 << 10),
 
    ALT_QSPI_INT_STATUS_RX_FIFO_FULL      = (0x1 << 11),
 
    ALT_QSPI_INT_STATUS_IDAC_RD_FULL      = (0x1 << 12)
 
} ALT_QSPI_INT_STATUS_t;
 
/******************************************************************************/
uint32_t alt_qspi_int_status_get(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_int_clear(const uint32_t mask);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_int_disable(const uint32_t mask);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_int_enable(const uint32_t mask);
 
/******************************************************************************/
bool alt_qspi_is_idle(void);
 
/******************************************************************************/
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_read(void * dest, uint32_t src, size_t size);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_write(uint32_t dest, const void * src, size_t size);
 
/******************************************************************************/
/******************************************************************************/
typedef enum ALT_QSPI_MODE_e
{
  ALT_QSPI_MODE_SINGLE = 0,     
  ALT_QSPI_MODE_DUAL   = 1,     
  ALT_QSPI_MODE_QUAD   = 2      
} ALT_QSPI_MODE_t;
 
/******************************************************************************/
typedef enum ALT_QSPI_CS_MODE_e
{
  ALT_QSPI_CS_MODE_SINGLE_SELECT = 0,   
  ALT_QSPI_CS_MODE_DECODE        = 1    
} ALT_QSPI_CS_MODE_t;
 
/******************************************************************************/
typedef enum ALT_QSPI_BAUD_DIV_e
{
  ALT_QSPI_BAUD_DIV_2            = 0x0, 
  ALT_QSPI_BAUD_DIV_4            = 0x1, 
  ALT_QSPI_BAUD_DIV_6            = 0x2, 
  ALT_QSPI_BAUD_DIV_8            = 0x3, 
  ALT_QSPI_BAUD_DIV_10           = 0x4, 
  ALT_QSPI_BAUD_DIV_12           = 0x5, 
  ALT_QSPI_BAUD_DIV_14           = 0x6, 
  ALT_QSPI_BAUD_DIV_16           = 0x7, 
  ALT_QSPI_BAUD_DIV_18           = 0x8, 
  ALT_QSPI_BAUD_DIV_20           = 0x9, 
  ALT_QSPI_BAUD_DIV_22           = 0xA, 
  ALT_QSPI_BAUD_DIV_24           = 0xB, 
  ALT_QSPI_BAUD_DIV_26           = 0xC, 
  ALT_QSPI_BAUD_DIV_28           = 0xD, 
  ALT_QSPI_BAUD_DIV_30           = 0xE, 
  ALT_QSPI_BAUD_DIV_32           = 0xF  
} ALT_QSPI_BAUD_DIV_t;
 
/******************************************************************************/
typedef struct ALT_QSPI_DEV_SIZE_CONFIG_s
{
  uint32_t      block_size;         
  uint32_t      page_size;          
  uint32_t      addr_size;          
  uint32_t      lower_wrprot_block; 
  uint32_t      upper_wrprot_block; 
  bool          wrprot_enable;      
} ALT_QSPI_DEV_SIZE_CONFIG_t;
 
/******************************************************************************/
typedef enum ALT_QSPI_CLK_PHASE_e
{
  ALT_QSPI_CLK_PHASE_ACTIVE     = 0,    
  ALT_QSPI_CLK_PHASE_INACTIVE   = 1     
} ALT_QSPI_CLK_PHASE_t;
 
/******************************************************************************/
typedef enum ALT_QSPI_CLK_POLARITY_e
{
  ALT_QSPI_CLK_POLARITY_LOW     = 0,    
  ALT_QSPI_CLK_POLARITY_HIGH    = 1     
} ALT_QSPI_CLK_POLARITY_t;
 
/******************************************************************************/
typedef struct ALT_QSPI_TIMING_CONFIG_s
{
  ALT_QSPI_CLK_PHASE_t      clk_phase;  
  ALT_QSPI_CLK_POLARITY_t   clk_pol;    
  uint32_t                  cs_da;      
  uint32_t                  cs_dads;    
  uint32_t                  cs_eot;     
  uint32_t                  cs_sot;     
  uint32_t                  rd_datacap; 
} ALT_QSPI_TIMING_CONFIG_t;
 
/******************************************************************************/
typedef struct ALT_QSPI_DEV_INST_CONFIG_s
{
  uint32_t              op_code;            
  ALT_QSPI_MODE_t       inst_type;          
  ALT_QSPI_MODE_t       addr_xfer_type;     
  ALT_QSPI_MODE_t       data_xfer_type;     
  uint32_t              dummy_cycles;       
} ALT_QSPI_DEV_INST_CONFIG_t;
 
/******************************************************************************/
ALT_QSPI_BAUD_DIV_t alt_qspi_baud_rate_div_get(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_baud_rate_div_set(const ALT_QSPI_BAUD_DIV_t baud_rate_div);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_chip_select_config_get(uint32_t* cs, ALT_QSPI_CS_MODE_t* cs_mode);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_chip_select_config_set(const uint32_t cs,
                                                const ALT_QSPI_CS_MODE_t cs_mode);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_mode_bit_disable(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_mode_bit_enable(void);
 
/******************************************************************************/
uint32_t alt_qspi_mode_bit_config_get(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_mode_bit_config_set(const uint32_t mode_bits);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_device_size_config_get(ALT_QSPI_DEV_SIZE_CONFIG_t * cfg);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_device_size_config_set(const ALT_QSPI_DEV_SIZE_CONFIG_t * cfg);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_device_read_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_device_read_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_device_write_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_device_write_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_timing_config_get(ALT_QSPI_TIMING_CONFIG_t * cfg);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_timing_config_set(const ALT_QSPI_TIMING_CONFIG_t * cfg);
 
/******************************************************************************/
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_direct_disable(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_direct_enable(void);
 
/******************************************************************************/
uint32_t alt_qspi_ahb_remap_address_get(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_ahb_remap_address_set(const uint32_t ahb_remap_addr);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_ahb_address_remap_disable(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_ahb_address_remap_enable(void);
 
/******************************************************************************/
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_indirect_read_start(const uint32_t flash_addr,
                                             const size_t num_bytes);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_indirect_read_finish(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_indirect_read_cancel(void);
 
/******************************************************************************/
uint32_t alt_qspi_indirect_read_fill_level(void);
 
/******************************************************************************/
uint32_t alt_qspi_indirect_read_watermark_get(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_indirect_read_watermark_set(const uint32_t watermark);
 
/******************************************************************************/
bool alt_qspi_indirect_read_is_complete(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_indirect_write_start(const uint32_t flash_addr,
                                              const size_t num_bytes);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_indirect_write_finish(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_indirect_write_cancel(void);
 
/******************************************************************************/
uint32_t alt_qspi_indirect_write_fill_level(void);
 
/******************************************************************************/
uint32_t alt_qspi_indirect_write_watermark_get(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_indirect_write_watermark_set(const uint32_t watermark);
 
/******************************************************************************/
bool alt_qspi_indirect_write_is_complete(void);
 
/******************************************************************************/
#define ALT_QSPI_SRAM_FIFO_SIZE           (512)
 
/*
 * The size of the onboard SRAM in entries. Each entry is word (32-bit) sized.
 */
#define ALT_QSPI_SRAM_FIFO_ENTRY_COUNT    (512 / sizeof(uint32_t))
 
/******************************************************************************/
uint32_t alt_qspi_sram_partition_get(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_sram_partition_set(const uint32_t read_part_size);
 
/******************************************************************************/
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_erase_subsector(const uint32_t addr);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_erase_sector(const uint32_t addr);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_erase_chip(void);
 
/******************************************************************************/
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_dma_disable(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_dma_enable(void);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_dma_config_get(uint32_t * single_type_sz,
                                        uint32_t * burst_type_sz);
 
/******************************************************************************/
ALT_STATUS_CODE alt_qspi_dma_config_set(const uint32_t single_type_sz,
                                        const uint32_t burst_type_sz);
 
 
#ifdef __cplusplus
}
#endif  /* __cplusplus */
#endif  /* __ALT_QSPI_H__ */