RTEMS 5.2
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bsp.h
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1
9/*
10 * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 * http://www.rtems.org/license/LICENSE.
15 *
16 * (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
17 */
18
19#ifndef LIBBSP_POWERPC_MVME5500_BSP_H
20#define LIBBSP_POWERPC_MVME5500_BSP_H
21
32#ifndef ASM
33
34#include <bspopts.h>
36
37#include <rtems.h>
38#include <libcpu/io.h>
39#include <bsp/vectors.h>
40
41/* Board type */
42typedef enum {
43 undefined = 0,
44 MVME5500,
45 MVME6100
46} BSP_BoardTypes;
47
48BSP_BoardTypes BSP_getBoardType(void);
49
50/* Board type */
51typedef enum {
52 Undefined,
53 UNIVERSE2,
54 TSI148,
55} BSP_VMEchipTypes;
56
57BSP_VMEchipTypes BSP_getVMEchipType(void);
58
59/* The version of Discovery system controller */
60
61typedef enum {
62 notdefined,
63 GT64260A,
64 GT64260B,
65 MV64360,
66} DiscoveryChipVersion;
67
68DiscoveryChipVersion BSP_getDiscoveryChipVersion(void);
69
70#define _256M 0x10000000
71#define _512M 0x20000000
72
73#define GT64x60_REG_BASE 0xf1000000 /* Base of GT64260 Reg Space */
74#define GT64x60_REG_SPACE_SIZE 0x10000 /* 64Kb Internal Reg Space */
75
76#define GT64x60_DEV1_BASE 0xf1100000 /* Device bank1(chip select 1) base
77 */
78#define GT64260_DEV1_SIZE 0x00100000 /* Device bank size */
79
80/* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */
81#define _IO_BASE GT64x60_REG_BASE
82
83#define BSP_NVRAM_BASE_ADDR 0xf1110000
84
85#define BSP_RTC_INTA_REG 0x7ff0
86#define BSP_RTC_SECOND 0x7ff2
87#define BSP_RTC_MINUTE 0x7ff3
88#define BSP_RTC_HOUR 0x7ff4
89#define BSP_RTC_DATE 0x7ff5
90#define BSP_RTC_INTERRUPTS 0x7ff6
91#define BSP_RTC_WATCHDOG 0x7ff7
92
93/* PCI0 Domain I/O space */
94#define PCI0_IO_BASE 0xf0000000
95#define PCI1_IO_BASE 0xf0800000
96
97/* PCI 0 memory space as seen from the CPU */
98#define PCI0_MEM_BASE 0x80000000
99#define PCI_MEM_BASE 0 /* glue for vmeUniverse */
100#define PCI_MEM_BASE_ADJUSTMENT 0
101
102/* address of our ram on the PCI bus */
103#define PCI_DRAM_OFFSET 0
104
105/* PCI 1 memory space as seen from the CPU */
106#define PCI1_MEM_BASE 0xe0000000
107#define PCI1_MEM_SIZE 0x10000000
108
109/* Needed for hot adding via PMCspan on the PCI0 local bus.
110 * This is board dependent, only because mvme5500
111 * supports hot adding and has more than one local PCI
112 * bus.
113 */
114#define BSP_MAX_PCI_BUS_ON_PCI0 8
115#define BSP_MAX_PCI_BUS_ON_PCI1 2
116#define BSP_MAX_PCI_BUS (BSP_MAX_PCI_BUS_ON_PCI0+BSP_MAX_PCI_BUS_ON_PCI1)
117
118
119/* The glues to Till's vmeUniverse, although the name does not
120 * actually reflect the relevant architect of the MVME5500.
121 */
122#define BSP_PCI_IRQ0 BSP_GPP_IRQ_LOWEST_OFFSET
123
124/*
125 * confdefs.h overrides for this BSP:
126 * - Interrupt stack space is not minimum if defined.
127 */
128#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) /* <skf> 2/09 wants it to be adjustable by BSP */
129
130/* uart.c uses out_8 instead of outb */
131#define BSP_UART_IOBASE_COM1 GT64x60_DEV1_BASE + 0x20000
132#define BSP_UART_IOBASE_COM2 GT64x60_DEV1_BASE + 0x21000
133
134#define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */
135#define BSP_UART_BAUD_BASE 115200
136
137/*
138 * Total memory using RESIDUAL DATA
139 */
140extern unsigned int BSP_mem_size;
141/*
142 * PCI Bus Frequency
143 */
144extern unsigned int BSP_bus_frequency;
145/*
146 * processor clock frequency
147 */
148extern unsigned int BSP_processor_frequency;
149/*
150 * Time base divisior (how many tick for 1 second).
151 */
152extern unsigned int BSP_time_base_divisor;
153
154#define BSP_Convert_decrementer( _value ) \
155 ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
156
157extern void bsp_reset(void);
158/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */
159extern int BSP_disconnect_clock_handler(void);
160extern int BSP_connect_clock_handler(void);
161
162unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
163
164/*
165 * Prototypes for methods called only from .S for dependency tracking
166 */
167char *save_boot_params(
168 void *r3,
169 void *r4,
170 void *r5,
171 char *cmdline_start,
172 char *cmdline_end
173);
174void zero_bss(void);
175
176/*
177 * Prototypes for methods in the BSP that cross file boundaries
178 */
179uint32_t probeMemoryEnd(void);
180void pci_interface(void);
181void BSP_printPicIsrTbl(void);
182int I2Cread_eeprom(
183 unsigned char I2cBusAddr,
184 uint32_t devA2A1A0,
185 uint32_t AddrBytes,
186 unsigned char *pBuff,
187 uint32_t numBytes
188);
189
190#if 0
191#define RTEMS_BSP_NETWORK_DRIVER_NAME "gt1"
192#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_GT64260eth_driver_attach
193#else
194#define RTEMS_BSP_NETWORK_DRIVER_NAME "wmG1"
195#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_i82544EI_driver_attach
196#endif
197
198struct rtems_bsdnet_ifconfig;
199
200extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH(struct rtems_bsdnet_ifconfig *, int);
201
202#define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER()
203
204static inline void lwmemBar(void)
205{
206 __asm__ volatile("lwsync":::"memory");
207}
208
209static inline void io_flush(void)
210{
211 __asm__ volatile("isync":::"memory");
212}
213
214static inline void memBar(void)
215{
216 __asm__ volatile("sync":::"memory");
217}
218
219static inline void ioBar(void)
220{
221 __asm__ volatile("eieio":::"memory");
222}
223
224#endif
225
228#endif /* !ASM */
PowerPC Exceptions API.
DEFAULT_INITIAL_EXTENSION Support.
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH
Standard network driver attach and detach function.
Definition: bsp.h:77
int BSP_connect_clock_handler(void)
Clock Tick Device Driver.
Definition: p_clock.c:37
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.