RTEMS 5.2
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irq.h
1/* irq.h
2 *
3 * This include file describe the data structure and the functions implemented
4 * by rtems to write interrupt handlers.
5 *
6 * CopyRight (C) 1999 valette@crf.canon.fr
7 *
8 * This code is heavilly inspired by the public specification of STREAM V2
9 * that can be found at :
10 *
11 * <http://www.chorus.com/Documentation/index.html> by following
12 * the STREAM API Specification Document link.
13 *
14 * The license and distribution terms for this file may be
15 * found in the file LICENSE in this distribution or at
16 * http://www.rtems.org/license/LICENSE.
17 *
18 * Copyright 2004, 2005 Brookhaven National Laboratory and
19 * Shuchen Kate Feng <feng1@bnl.gov>
20 *
21 * - modified shared/irq/irq.h for Mvme5500 (no ISA devices/PIC)
22 * - Discovery GT64260 interrupt controller instead of 8259.
23 * - Added support for software IRQ priority levels.
24 * - modified to optimize the IRQ latency and handling
25 */
26
27#ifndef LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H
28#define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H
29
30#define BSP_SHARED_HANDLER_SUPPORT 1
31#include <rtems/irq.h>
32
33#ifndef ASM
34
35#include <bsp/irq-default.h>
36
37#define OneTierIrqPrioTbl 1
38
39/*
40 * Symbolic IRQ names and related definitions.
41 */
42
43/* leave the ISA symbols in there, so we can reuse shared/irq.c
44 * Also, we start numbering PCI irqs at 16 because the OPENPIC
45 * driver relies on this when mapping irq number <-> vectors
46 * (OPENPIC_VEC_SOURCE in openpic.h)
47 */
48
49 /* See section 25.2 , Table 734 of GT64260 controller
50 * Main Interrupt Cause Low register
51 */
52#define BSP_MICL_IRQ_NUMBER (32)
53#define BSP_MICL_IRQ_LOWEST_OFFSET (0)
54#define BSP_MICL_IRQ_MAX_OFFSET (BSP_MICL_IRQ_LOWEST_OFFSET + BSP_MICL_IRQ_NUMBER -1)
55 /*
56 * Main Interrupt Cause High register
57 */
58#define BSP_MICH_IRQ_NUMBER (32)
59#define BSP_MICH_IRQ_LOWEST_OFFSET (BSP_MICL_IRQ_MAX_OFFSET+1)
60#define BSP_MICH_IRQ_MAX_OFFSET (BSP_MICH_IRQ_LOWEST_OFFSET + BSP_MICH_IRQ_NUMBER -1)
61 /* External GPP Interrupt assignements
62 */
63#define BSP_GPP_IRQ_NUMBER (32)
64#define BSP_GPP_IRQ_LOWEST_OFFSET (BSP_MICH_IRQ_MAX_OFFSET+1)
65#define BSP_GPP_IRQ_MAX_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET + BSP_GPP_IRQ_NUMBER - 1)
66
67 /*
68 * PowerPc exceptions handled as interrupt where a rtems managed interrupt
69 * handler might be connected
70 */
71#define BSP_PROCESSOR_IRQ_NUMBER (1)
72#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_MAX_OFFSET + 1)
73#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
74
75 /* allow a couple of vectors for VME and counter/timer irq sources etc.
76 * This is probably not needed any more.
77 */
78#define BSP_MISC_IRQ_NUMBER (30)
79#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
80#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
81
82 /*
83 * Summary
84 */
85#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
86#define BSP_MAIN_IRQ_NUMBER (64)
87#define BSP_PIC_IRQ_NUMBER (96)
88#define BSP_LOWEST_OFFSET (BSP_MICL_IRQ_LOWEST_OFFSET)
89#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
90
91 /* Main CPU interrupt cause (Low) */
92#define BSP_MAIN_TIMER0_1_IRQ (BSP_MICL_IRQ_LOWEST_OFFSET+8)
93#define BSP_MAIN_PCI0_7_0 (BSP_MICL_IRQ_LOWEST_OFFSET+12)
94#define BSP_MAIN_PCI0_15_8 (BSP_MICL_IRQ_LOWEST_OFFSET+13)
95#define BSP_MAIN_PCI0_23_16 (BSP_MICL_IRQ_LOWEST_OFFSET+14)
96#define BSP_MAIN_PCI0_31_24 (BSP_MICL_IRQ_LOWEST_OFFSET+15)
97#define BSP_MAIN_PCI1_7_0 (BSP_MICL_IRQ_LOWEST_OFFSET+16)
98#define BSP_MAIN_PCI1_15_8 (BSP_MICL_IRQ_LOWEST_OFFSET+18)
99#define BSP_MAIN_PCI1_23_16 (BSP_MICL_IRQ_LOWEST_OFFSET+19)
100#define BSP_MAIN_PCI1_31_24 (BSP_MICL_IRQ_LOWEST_OFFSET+20)
101
102
103 /* Main CPU interrupt cause (High) */
104#define BSP_MAIN_ETH0_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET)
105#define BSP_MAIN_ETH1_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+1)
106#define BSP_MAIN_ETH2_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+2)
107#define BSP_MAIN_GPP7_0_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+24)
108#define BSP_MAIN_GPP15_8_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+25)
109#define BSP_MAIN_GPP23_16_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+26)
110#define BSP_MAIN_GPP31_24_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+27)
111
112 /* on the MVME5500, these are the GT64260B external GPP0 interrupt */
113#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET)
114#define BSP_UART_COM2_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET)
115#define BSP_UART_COM1_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET)
116#define BSP_GPP8_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+8)
117#define BSP_GPP_PMC1_INTA (BSP_GPP8_IRQ_OFFSET)
118#define BSP_GPP16_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+16)
119#define BSP_GPP24_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+24)
120#define BSP_GPP_VME_VLINT0 (BSP_GPP_IRQ_LOWEST_OFFSET+12)
121#define BSP_GPP_VME_VLINT1 (BSP_GPP_IRQ_LOWEST_OFFSET+13)
122#define BSP_GPP_VME_VLINT2 (BSP_GPP_IRQ_LOWEST_OFFSET+14)
123#define BSP_GPP_VME_VLINT3 (BSP_GPP_IRQ_LOWEST_OFFSET+15)
124#define BSP_GPP_PMC2_INTA (BSP_GPP_IRQ_LOWEST_OFFSET+16)
125#define BSP_GPP_82544_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+20)
126#define BSP_GPP_WDT_NMI_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+24)
127#define BSP_GPP_WDT_EXP_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+25)
128
129 /*
130 * Some Processor execption handled as rtems IRQ symbolic name definition
131 */
132#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
133
134extern void BSP_rtems_irq_mng_init(unsigned cpuId);
135
136#include <bsp/irq_supp.h>
137
138#endif
139#endif
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