40#ifndef _DEV_GTPCIREG_H
41#define _DEV_GTPCIREG_H
43#define PCI__BIT(bit) (1U << (bit))
44#define PCI__MASK(bit) (PCI__BIT(bit) - 1)
45#define PCI__GEN(bus, off, num) (((off)^((bus) << 7))+((num) << 4))
46#define PCI__EXT(data, bit, len) (((data) >> (bit)) & PCI__MASK(len))
47#define PCI__CLR(data, bit, len) ((data) &= ~(PCI__MASK(len) << (bit)))
48#define PCI__INS(bit, new) ((new) << (bit))
50#define PCI_SYNC_REG(bus) (0xc0 | ((bus) << 3))
55#define PCI_SCS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0c08, 0)
56#define PCI_SCS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0c0c, 0)
57#define PCI_CS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0c10, 0)
58#define PCI_CS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0c14, 0)
59#define PCI_SCS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d08, 0)
60#define PCI_SCS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0d0c, 0)
61#define PCI_CS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d10, 0)
62#define PCI_BOOTCS_BAR_SIZE(bus) PCI__GEN(bus, 0x0d14, 0)
63#define PCI_CS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0d18, 0)
64#define PCI_P2P_MEM0_BAR_SIZE(bus) PCI__GEN(bus, 0x0d1c, 0)
65#define PCI_P2P_MEM1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d20, 0)
66#define PCI_P2P_IO_BAR_SIZE(bus) PCI__GEN(bus, 0x0d24, 0)
67#define PCI_CPU_BAR_SIZE(bus) PCI__GEN(bus, 0x0d28, 0)
68#define PCI_EXPANSION_ROM_BAR_SIZE(bus) PCI__GEN(bus, 0x0d2c, 0)
69#define PCI_DAC_SCS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e00, 0)
70#define PCI_DAC_SCS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e04, 0)
71#define PCI_DAC_SCS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0e08, 0)
72#define PCI_DAC_SCS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0e0c, 0)
73#define PCI_DAC_CS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e10, 0)
74#define PCI_DAC_CS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e14, 0)
75#define PCI_DAC_CS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0e18, 0)
76#define PCI_DAC_CS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0e1c, 0)
77#define PCI_DAC_BOOTCS_BAR_SIZE(bus) PCI__GEN(bus, 0x0e20, 0)
78#define PCI_DAC_P2P_MEM0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e24, 0)
79#define PCI_DAC_P2P_MEM1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e28, 0)
80#define PCI_DAC_CPU_BAR_SIZE(bus) PCI__GEN(bus, 0x0e2c, 0)
81#define PCI_BASE_ADDR_REGISTERS_ENABLE(bus) PCI__GEN(bus, 0x0c3c, 0)
82#define PCI_SCS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c48, 0)
83#define PCI_SCS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d48, 0)
84#define PCI_SCS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c4c, 0)
85#define PCI_SCS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d4c, 0)
86#define PCI_CS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c50, 0)
87#define PCI_CS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d50, 0)
88#define PCI_CS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d58, 0)
89#define PCI_CS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c54, 0)
90#define PCI_ADDR_DECODE_CONTROL(bus) PCI__GEN(bus, 0x0d3c, 0)
91#define PCI_BOOTCS_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d54, 0)
92#define PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0d5c, 0)
93#define PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0d60, 0)
94#define PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0d64, 0)
95#define PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0d68, 0)
96#define PCI_P2P_IO_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d6c, 0)
97#define PCI_CPU_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d70, 0)
98#define PCI_DAC_SCS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f00, 0)
99#define PCI_DAC_SCS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f04, 0)
100#define PCI_DAC_SCS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f08, 0)
101#define PCI_DAC_SCS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f0c, 0)
102#define PCI_DAC_CS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f10, 0)
103#define PCI_DAC_CS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f14, 0)
104#define PCI_DAC_CS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f18, 0)
105#define PCI_DAC_CS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f1c, 0)
106#define PCI_DAC_BOOTCS_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f20, 0)
107#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0f24, 0)
108#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0f28, 0)
109#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0f2c, 0)
110#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0f30, 0)
111#define PCI_DAC_CPU_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f34, 0)
112#define PCI_EXPANSION_ROM_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f38, 0)
117#define PCI_COMMAND(bus) PCI__GEN(bus, 0x0c00, 0)
118#define PCI_MODE(bus) PCI__GEN(bus, 0x0d00, 0)
119#define PCI_TIMEOUT_RETRY(bus) PCI__GEN(bus, 0x0c04, 0)
120#define PCI_READ_BUFFER_DISCARD_TIMER(bus) PCI__GEN(bus, 0x0d04, 0)
121#define PCI_MSI_TRIGGER_TIMER(bus) PCI__GEN(bus, 0x0c38, 0)
122#define PCI_ARBITER_CONTROL(bus) PCI__GEN(bus, 0x1d00, 0)
123#define PCI_INTERFACE_XBAR_CONTROL_LOW(bus) PCI__GEN(bus, 0x1d08, 0)
124#define PCI_INTERFACE_XBAR_CONTROL_HIGH(bus) PCI__GEN(bus, 0x1d0c, 0)
125#define PCI_INTERFACE_XBAR_TIMEOUT(bus) PCI__GEN(bus, 0x1d04, 0)
126#define PCI_READ_RESPONSE_XBAR_CONTROL_LOW(bus) PCI__GEN(bus, 0x1d18, 0)
127#define PCI_READ_RESPONSE_XBAR_CONTROL_HIGH(bus) PCI__GEN(bus, 0x1d1c, 0)
128#define PCI_SYNC_BARRIER(bus) PCI__GEN(bus, 0x1d10, 0)
129#define PCI_P2P_CONFIGURATION(bus) PCI__GEN(bus, 0x1d14, 0)
130#define PCI_P2P_SWAP_CONTROL(bus) PCI__GEN(bus, 0x1d54, 0)
131#define PCI_ACCESS_CONTROL_BASE_LOW(bus, n) PCI__GEN(bus, 0x1e00, n)
132#define PCI_ACCESS_CONTROL_BASE_HIGH(bus, n) PCI__GEN(bus, 0x1e04, n)
133#define PCI_ACCESS_CONTROL_TOP(bus, n) PCI__GEN(bus, 0x1e08, n)
139#define PCI_SNOOP_CONTROL_BASE_LOW(bus, n) PCI__GEN(bus, 0x1f00, n)
140#define PCI_SNOOP_CONTROL_BASE_HIGH(bus, n) PCI__GEN(bus, 0x1f04, n)
141#define PCI_SNOOP_CONTROL_TOP(bus, n) PCI__GEN(bus, 0x1f08, n)
146#define PCI_CONFIG_ADDR(bus) PCI__GEN(bus, 0x0cf8, 0)
147#define PCI_CONFIG_DATA(bus) PCI__GEN(bus, 0x0cfc, 0)
148#define PCI_INTR_ACK(bus) PCI__GEN(bus, 0x0c34, 0)
153#define PCI_SERR_MASK(bus) PCI__GEN(bus, 0x0c28, 0)
154#define PCI_ERROR_ADDRESS_LOW(bus) PCI__GEN(bus, 0x1d40, 0)
155#define PCI_ERROR_ADDRESS_HIGH(bus) PCI__GEN(bus, 0x1d44, 0)
156#define PCI_ERROR_DATA_LOW(bus) PCI__GEN(bus, 0x1d48, 0)
157#define PCI_ERROR_DATA_HIGH(bus) PCI__GEN(bus, 0x1d4c, 0)
158#define PCI_ERROR_COMMAND(bus) PCI__GEN(bus, 0x1d50, 0)
159#define PCI_ERROR_CAUSE(bus) PCI__GEN(bus, 0x1d58, 0)
160#define PCI_ERROR_MASK(bus) PCI__GEN(bus, 0x1d5c, 0)
170#define PCI_BARE_SCS0En PCI__BIT(0)
171#define PCI_BARE_SCS1En PCI__BIT(1)
172#define PCI_BARE_SCS2En PCI__BIT(2)
173#define PCI_BARE_SCS3En PCI__BIT(3)
174#define PCI_BARE_CS0En PCI__BIT(4)
175#define PCI_BARE_CS1En PCI__BIT(5)
176#define PCI_BARE_CS2En PCI__BIT(6)
177#define PCI_BARE_CS3En PCI__BIT(7)
178#define PCI_BARE_BootCSEn PCI__BIT(8)
179#define PCI_BARE_IntMemEn PCI__BIT(9)
181#define PCI_BARE_IntIOEn PCI__BIT(10)
183#define PCI_BARE_P2PMem0En PCI__BIT(11)
184#define PCI_BARE_P2PMem1En PCI__BIT(12)
185#define PCI_BARE_P2PIOEn PCI__BIT(13)
186#define PCI_BARE_CPUEn PCI__BIT(14)
187#define PCI_BARE_DSCS0En PCI__BIT(15)
188#define PCI_BARE_DSCS1En PCI__BIT(16)
189#define PCI_BARE_DSCS2En PCI__BIT(17)
190#define PCI_BARE_DSCS3En PCI__BIT(18)
191#define PCI_BARE_DCS0En PCI__BIT(19)
192#define PCI_BARE_DCS1En PCI__BIT(20)
193#define PCI_BARE_DCS2En PCI__BIT(21)
194#define PCI_BARE_DCS3En PCI__BIT(22)
195#define PCI_BARE_DBootCSEn PCI__BIT(23)
196#define PCI_BARE_DP2PMem0En PCI__BIT(24)
197#define PCI_BARE_DP2PMem1En PCI__BIT(25)
198#define PCI_BARE_DCPUEn PCI__BIT(26)
221#define PCI_ADC_RemapWrDis PCI__BIT(0)
222#define PCI_ADC_ExpRomDev PCI__BIT(1)
223#define PCI_ADC_VPDDev PCI__BIT(2)
224#define PCI_ADC_MsgAcc PCI__BIT(3)
225#define PCI_ADC_VPDHighAddr_GET(v) PCI__EXT(v, 8, 16)
334#define PCI_CMD_MByteSwap PCI__BIT(0)
335#define PCI_CMD_MBZ0_2 PCI__BIT(2)
336#define PCI_CMD_MWrCom PCI__BIT(4)
337#define PCI_CMD_MRdCom PCI__BIT(5)
338#define PCI_CMD_MWrTrig PCI__BIT(6)
339#define PCI_CMD_MRdTrig PCI__BIT(7)
340#define PCI_CMD_MRdLine PCI__BIT(8)
341#define PCI_CMD_MRdMul PCI__BIT(9)
342#define PCI_CMD_MWordSwap PCI__BIT(10)
343#define PCI_CMD_SWordSwap PCI__BIT(11)
344#define PCI_CMD_IntBusCtl PCI__BIT(12)
345#define PCI_CMD_SBDis PCI__BIT(13)
346#define PCI_CMD_MBZ0_14 PCI__BIT(14)
347#define PCI_CMD_MReq64 PCI__BIT(15)
348#define PCI_CMD_SByteSwap PCI__BIT(16)
349#define PCI_CMD_MDCAEn PCI__BIT(17)
350#define PCI_CMD_M64Allign PCI__BIT(18)
351#define PCI_CMD_PErrProp PCI__BIT(19)
352#define PCI_CMD_SSwapEn PCI__BIT(20)
353#define PCI_CMD_MSwapEn PCI__BIT(21)
354#define PCI_CMD_MIntSwapEn PCI__BIT(22)
355#define PCI_CMD_LBEn PCI__BIT(23)
356#define PCI_CMD_SIntSwap_GET(v) PCI__EXT(v, 24, 3)
357#define PCI_CMD_MBZ0_27 PCI__BIT(27)
384#define PCI_MODE_PciID_GET(v) PCI__EXT(v, 0, 1)
385#define PCI_MODE_Pci64 PCI__BIT(2)
386#define PCI_MODE_ExpRom PCI__BIT(8)
387#define PCI_MODE_VPD PCI__BIT(9)
388#define PCI_MODE_MSI PCI__BIT(10)
389#define PCI_MODE_PMG PCI__BIT(11)
390#define PCI_MODE_HotSwap PCI__BIT(12)
391#define PCI_MODE_BIST PCI__BIT(13)
392#define PCI_MODE_PRst PCI__BIT(31)
408#define PCI_TMORTRY_Timeout0_GET(v) PCI__EXT(v, 0, 8)
409#define PCI_TMORTRY_Timeout1_GET(v) PCI__EXT(v, 8, 8)
410#define PCI_TMORTRY_RetryCtr_GET(v) PCI__EXT(v, 16, 8)
423#define PCI_RdBufDisTmr_Timer_GET(v) PCI__EXT(v, 0, 16)
424#define PCI_RdBufDisTmr_RdBufEn_GET(v) PCI__EXT(v, 16, 8)
425#define PCI_RdBufDisTmr_RdBufEn0(v) PCI__BIT(16)
426#define PCI_RdBufDisTmr_RdBufEn1(v) PCI__BIT(17)
427#define PCI_RdBufDisTmr_RdBufEn2(v) PCI__BIT(18)
428#define PCI_RdBufDisTmr_RdBufEn3(v) PCI__BIT(19)
429#define PCI_RdBufDisTmr_RdBufEn4(v) PCI__BIT(20)
430#define PCI_RdBufDisTmr_RdBufEn5(v) PCI__BIT(21)
431#define PCI_RdBufDisTmr_RdBufEn6(v) PCI__BIT(22)
432#define PCI_RdBufDisTmr_RdBufEn7(v) PCI__BIT(23)
440#define PCI_MSITrigger_Timer_GET(v) PCI__EXT(v, 0, 16)
498#define PCI_ARBCTL_MBZ0_0 PCI__BIT(0)
499#define PCI_ARBCTL_BDEn PCI__BIT(1)
500#define PCI_ARBCTL_PAEn PCI__BIT(2)
501#define PCI_ARBCTL_BV_GET(v) PCI__EXT(v, 3, 4)
502#define PCI_ARBCTL_P_GET(v) PCI__EXT(v, 7, 7)
503#define PCI_ARBCTL_PD_GET(v) PCI__EXT(v, 14, 7)
504#define PCI_ARBCTL_HPPV_GET(v) PCI__EXT(v, 21, 7)
505#define PCI_ARBCTL_EN PCI__BIT(31)
507#define PCI_ARBPRI_IntPci PCI__BIT(0)
508#define PCI_ARBPRI_ExtReqGnt0 PCI__BIT(1)
509#define PCI_ARBPRI_ExtReqGnt1 PCI__BIT(2)
510#define PCI_ARBPRI_EXtReqGnt2 PCI__BIT(3)
511#define PCI_ARBPRI_EXtReqGnt3 PCI__BIT(4)
512#define PCI_ARBPRI_EXtReqGnt4 PCI__BIT(5)
513#define PCI_ARBPRI_EXtReqGnt5 PCI__BIT(6)
526#define PCI_IFXBRCTL_GET_SLICE(v, n) PCI__EXT(v, (n) * 4, 4)
527#define PCI_IFXBRCTL_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, (n)*4, 4),\
528 (v) |= PCI__INS((n)*4, s)))
541#define PCI_IFXBRCH_GET_SLICE(v, n) PCI__EXT(v, ((n) - 8) * 4, 4)
542#define PCI_IFXBRCH_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, ((n)*-8)4, 4),\
543 (v) |= PCI__INS(((n)-8)*4, s)))
553#define PCI_IFXBRTMO_Timeout_GET(v) PCI__EXT(v, 0, 8)
554#define PCI_IFXBRTMO_TimeoutEn PCI__BIT(16)
567#define PCI_RRXBRCL_GET_SLICE(v, n) PCI__EXT(v, (n) * 4, 4)
568#define PCI_RRXBRCL_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, (n)*4, 4),\
569 (v) |= PCI__INS((n)*4, s)))
583#define PCI_RRXBRCH_GET_SLICE(v, n) PCI__EXT(v, ((n) - 8) * 4, 4)
584#define PCI_RRXBRCH_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, ((n)*-8)4, 4),\
585 (v) |= PCI__INS(((n)-8)*4, s)))
603#define PCI_P2PCFG_2ndBusL_GET(v) PCI__EXT(v, 0, 8)
604#define PCI_P2PCFG_2ndBusH_GET(v) PCI__EXT(v, 8, 8)
605#define PCI_P2PCFG_BusNum_GET(v) PCI__EXT(v, 16, 8)
606#define PCI_P2PCFG_DevNum_GET(v) PCI__EXT(v, 24, 5)
623#define PCI_P2PSWAP_M0Sw_GET(v) PCI__EXT(v, 0, 3)
624#define PCI_P2PSWAP_M0Req64 PCI__BIT(3)
625#define PCI_P2PSWAP_M1Sw_GET(v) PCI__EXT(v, 4, 3)
626#define PCI_P2PSWAP_M1Req64 PCI__BIT(7)
627#define PCI_P2PSWAP_DM0Sw_GET(v) PCI__EXT(v, 8, 3)
628#define PCI_P2PSWAP_DM0Req64 PCI__BIT(11)
629#define PCI_P2PSWAP_DM1Sw_GET(v) PCI__EXT(v, 12, 3)
630#define PCI_P2PSWAP_DM1Req64 PCI__BIT(15)
631#define PCI_P2PSWAP_CfgSw_GET(v) PCI__EXT(v, 20, 3)
673#define PCI_ACCCTLBASEL_Addr_GET(v) PCI__EXT(v, 0, 12)
674#define PCI_ACCCTLBASEL_PrefetchEn PCI__BIT(12)
675#define PCI_ACCCTLBASEL_MBZ0_14 PCI__BIT(14)
676#define PCI_ACCCTLBASEL_RdPrefetch PCI__BIT(16)
677#define PCI_ACCCTLBASEL_RdLinePrefetch PCI__BIT(17)
678#define PCI_ACCCTLBASEL_RdMulPrefetch PCI__BIT(18)
679#define PCI_ACCCTLBASEL_WBurst PCI__EXT(v, 20, 2)
680#define PCI_ACCCTLBASEL_WBurst_8_QW PCI__INS(20, PCI_WBURST_8_QW)
681#define PCI_ACCCTLBASEL_PCISwap PCI__EXT(v, 24, 2)
682#define PCI_ACCCTLBASEL_PCISwap_NoSwap PCI__INS(24, PCI_PCISWAP_NoSwap)
683#define PCI_ACCCTLBASEL_MBZ0_26 PCI__BIT(26)
684#define PCI_ACCCTLBASEL_AccProt PCI__BIT(28)
685#define PCI_ACCCTLBASEL_WrProt PCI__BIT(29)
687#define PCI_WBURST_4_QW 0x00
688#define PCI_WBURST_8_QW 0x01
689#define PCI_WBURST_16_QW 0x02
690#define PCI_WBURST_Reserved 0x04
692#define PCI_PCISWAP_ByteSwap 0x00
693#define PCI_PCISWAP_NoSwap 0x01
694#define PCI_PCISWAP_ByteWordSwap 0x02
695#define PCI_PCISWAP_WordSwap 0x04
703#define PCI_SNOOPCTL_ADDR(v) PCI__EXT(v, 0, 12)
704#define PCI_SNOOPCTL_TYPE(v) PCI__EXT(v, 12, 2)
706#define PCI_SNOOP_None 0
707#define PCI_SNOOP_WT 1
708#define PCI_SNOOP_WB 2
722#define PCI_CFG_MAKE_TAG(bus, dev, fun, reg) (PCI__BIT(31)|\
723 PCI__INS(16, (bus))|\
724 PCI__INS(11, (dev))|\
725 PCI__INS( 8, (fun))|\
727#define PCI_CFG_GET_BUSNO(tag) PCI__EXT(tag, 16, 8)
728#define PCI_CFG_GET_DEVNO(tag) PCI__EXT(tag, 11, 5)
729#define PCI_CFG_GET_FUNCNO(tag) PCI__EXT(tag, 8, 3)
730#define PCI_CFG_GET_REGNO(tag) PCI__EXT(tag, 0, 8)
758#define PCI_SERRMSK_SAPerr PCI__BIT(0)
760#define PCI_SERRMSK_SWrPerr PCI__BIT(1)
762#define PCI_SERRMSK_SRdPerr PCI__BIT(2)
765#define PCI_SERRMSK_MAPerr PCI__BIT(4)
768#define PCI_SERRMSK_MWrPerr PCI__BIT(5)
771#define PCI_SERRMSK_MRdPerr PCI__BIT(6)
774#define PCI_SERRMSK_MMabort PCI__BIT(8)
776#define PCI_SERRMSK_MTabort PCI__BIT(9)
778#define PCI_SERRMSK_MRetry PCI__BIT(11)
780#define PCI_SERRMSK_SMabort PCI__BIT(16)
782#define PCI_SERRMSK_STabort PCI__BIT(17)
785#define PCI_SERRMSK_SAccProt PCI__BIT(18)
787#define PCI_SERRMSK_SWrProt PCI__BIT(19)
789#define PCI_SERRMSK_SRdBuf PCI__BIT(20)
791#define PCI_SERRMSK_Arb PCI__BIT(21)
795#define PCI_SERRMSK_ALL_ERRS \
796 (PCI_SERRMSK_SAPerr|PCI_SERRMSK_SWrPerr|PCI_SERRMSK_SRdPerr \
797 |PCI_SERRMSK_MAPerr|PCI_SERRMSK_MWrPerr|PCI_SERRMSK_MRdPerr \
798 |PCI_SERRMSK_MMabort|PCI_SERRMSK_MTabort|PCI_SERRMSK_MRetry \
799 |PCI_SERRMSK_SMabort|PCI_SERRMSK_STabort|PCI_SERRMSK_SAccProt \
800 |PCI_SERRMSK_SWrProt|PCI_SERRMSK_SRdBuf|PCI_SERRMSK_Arb)
848#define PCI_ERRCMD_Cmd_GET(v) PCI__EXT(v, 0, 4)
849#define PCI_ERRCMD_ByteEn_GET(v) PCI__EXT(v, 8, 8)
850#define PCI_ERRCMD_PAR PCI__BIT(16)
851#define PCI_ERRCMD_PAR64 PCI__BIT(17)
864#define PCI_IC_SAPerr PCI__BIT(0)
866#define PCI_IC_SWrPerr PCI__BIT(1)
868#define PCI_IC_SRdPerr PCI__BIT(2)
870#define PCI_IC_MAPerr PCI__BIT(4)
872#define PCI_IC_MWrPerr PCI__BIT(5)
874#define PCI_IC_MRdPerr PCI__BIT(6)
877#define PCI_IC_MMabort PCI__BIT(8)
879#define PCI_IC_MTabort PCI__BIT(9)
881#define PCI_IC_MMasterEn PCI__BIT(10)
884#define PCI_IC_MRetry PCI__BIT(11)
886#define PCI_IC_SMabort PCI__BIT(16)
888#define PCI_IC_STabort PCI__BIT(17)
891#define PCI_IC_SAccProt PCI__BIT(18)
893#define PCI_IC_SWrProt PCI__BIT(19)
895#define PCI_IC_SRdBuf PCI__BIT(20)
897#define PCI_IC_Arb PCI__BIT(21)
899#define PCI_IC_BIST PCI__BIT(24)
900#define PCI_IC_PMG PCI__BIT(25)
902#define PCI_IC_PRST PCI__BIT(26)
908#define PCI_IC_SEL_GET(v) PCI__EXT((v), 27, 5)
909#define PCI_IC_SEL_SAPerr 0x00
910#define PCI_IC_SEL_SWrPerr 0x01
911#define PCI_IC_SEL_SRdPerr 0x02
912#define PCI_IC_SEL_MAPerr 0x04
913#define PCI_IC_SEL_MWrPerr 0x05
914#define PCI_IC_SEL_MRdPerr 0x06
915#define PCI_IC_SEL_MMabort 0x08
916#define PCI_IC_SEL_MTabort 0x09
917#define PCI_IC_SEL_MMasterEn 0x0a
918#define PCI_IC_SEL_MRetry 0x0b
919#define PCI_IC_SEL_SMabort 0x10
920#define PCI_IC_SEL_STabort 0x11
921#define PCI_IC_SEL_SAccProt 0x12
922#define PCI_IC_SEL_SWrProt 0x13
923#define PCI_IC_SEL_SRdBuf 0x14
924#define PCI_IC_SEL_Arb 0x15
925#define PCI_IC_SEL_BIST 0x18
926#define PCI_IC_SEL_PMG 0x19
927#define PCI_IC_SEL_PRST 0x1a
929#define PCI_IC_SEL_Strings { \
930 "SAPerr", "SWrPerr", "SRdPerr", "Rsvd#03", \
931 "MAPerr", "MWrPerr", "MRdPerr", "Rsvd#07", \
932 "MMabort", "MTabort", "MMasterEn", "MRetry", \
933 "Rsvd#0c", "Rsvd#0d", "Rsvd#0e", "Rsvd#0f", \
934 "SMabort", "STabort", "SAccProt", "SWrProt", \
935 "SRdBuf", "Arb", "Rsvd#16", "Rsvd#17", \
936 "BIST", "PMG", "PRST", "Rsvd#1b", \
937 "Rsvd#1c", "Rsvd#1d", "Rsvd#1e", "Rsvd#1f" }
944#define PCI_ERRMASK_SAPErr PCI__BIT(0)
945#define PCI_ERRMASK_SWrPErr PCI__BIT(1)
946#define PCI_ERRMASK_SRdPErr PCI__BIT(2)
947#define PCI_ERRMASK_MAPErr PCI__BIT(4)
948#define PCI_ERRMASK_MWRPErr PCI__BIT(5)
949#define PCI_ERRMASK_MRDPErr PCI__BIT(6)
950#define PCI_ERRMASK_MMAbort PCI__BIT(8)
951#define PCI_ERRMASK_MTAbort PCI__BIT(9)
952#define PCI_ERRMASK_MMasterEn PCI__BIT(10)
953#define PCI_ERRMASK_MRetry PCI__BIT(11)
954#define PCI_ERRMASK_SMAbort PCI__BIT(16)
955#define PCI_ERRMASK_STAbort PCI__BIT(17)
956#define PCI_ERRMASK_SAccProt PCI__BIT(18)
957#define PCI_ERRMASK_SWrProt PCI__BIT(19)
958#define PCI_ERRMASK_SRdBuf PCI__BIT(20)
959#define PCI_ERRMASK_Arb PCI__BIT(21)
960#define PCI_ERRMASK_BIST PCI__BIT(24)
961#define PCI_ERRMASK_PMG PCI__BIT(25)
962#define PCI_ERRMASK_PRST PCI__BIT(26)