RTEMS 5.2
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boot.h
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1
9/*
10 * Copyright (c) 2010
11 * embedded brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * <rtems@embedded-brains.de>
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http://www.rtems.org/license/LICENSE.
20 */
21
22#ifndef LIBBSP_ARM_LPC32XX_BOOT_H
23#define LIBBSP_ARM_LPC32XX_BOOT_H
24
25#include <stdint.h>
26
27#include <bsp/nand-mlc.h>
28
29#ifdef __cplusplus
30extern "C" {
31#endif /* __cplusplus */
32
58#define LPC32XX_BOOT_BLOCK_0 0
59#define LPC32XX_BOOT_BLOCK_1 1
60
61#define LPC32XX_BOOT_ICR_SP_3AC_8IF 0xf0
62#define LPC32XX_BOOT_ICR_SP_4AC_8IF 0xd2
63#define LPC32XX_BOOT_ICR_LP_4AC_8IF 0xb4
64#define LPC32XX_BOOT_ICR_LP_5AC_8IF 0x96
65
66typedef union {
67 struct {
68 uint8_t d0;
69 uint8_t reserved_0 [3];
70 uint8_t d1;
71 uint8_t reserved_1 [3];
72 uint8_t d2;
73 uint8_t reserved_2 [3];
74 uint8_t d3;
75 uint8_t reserved_3 [3];
76 uint8_t d4;
77 uint8_t reserved_4 [3];
78 uint8_t d5;
79 uint8_t reserved_5 [3];
80 uint8_t d6;
81 uint8_t reserved_6 [3];
82 uint8_t d7;
83 uint8_t reserved_7 [3];
84 uint8_t d8;
85 uint8_t reserved_8 [3];
86 uint8_t d9;
87 uint8_t reserved_9 [3];
88 uint8_t d10;
89 uint8_t reserved_10 [3];
90 uint8_t d11;
91 uint8_t reserved_11 [3];
92 uint8_t d12;
93 uint8_t reserved_12 [463];
94 } field;
95 uint32_t data [MLC_SMALL_DATA_WORD_COUNT];
97
98void lpc32xx_setup_boot_block(
99 lpc32xx_boot_block *boot_block,
100 uint8_t icr,
101 uint8_t page_count
102);
103
104void lpc32xx_set_boot_block_bad(
105 lpc32xx_boot_block *boot_block
106);
107
110#ifdef __cplusplus
111}
112#endif /* __cplusplus */
113
114#endif /* LIBBSP_ARM_LPC32XX_BOOT_H */
NAND MLC controller API.
Definition: boot.h:66