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mmu.h
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1 #ifndef RTEMS_VIRTEX5_MMU_H
2 #define RTEMS_VIRTEX5_MMU_H
3 
10 /*
11  * Authorship
12  * ----------
13  * This software was created by
14  * Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
15  * Stanford Linear Accelerator Center, Stanford University.
16  * and was transcribed for the PPC 440 by
17  * R. Claus <claus@slac.stanford.edu>, 2012,
18  * Stanford Linear Accelerator Center, Stanford University,
19  *
20  * Acknowledgement of sponsorship
21  * ------------------------------
22  * This software was produced by
23  * the Stanford Linear Accelerator Center, Stanford University,
24  * under Contract DE-AC03-76SFO0515 with the Department of Energy.
25  *
26  * Government disclaimer of liability
27  * ----------------------------------
28  * Neither the United States nor the United States Department of Energy,
29  * nor any of their employees, makes any warranty, express or implied, or
30  * assumes any legal liability or responsibility for the accuracy,
31  * completeness, or usefulness of any data, apparatus, product, or process
32  * disclosed, or represents that its use would not infringe privately owned
33  * rights.
34  *
35  * Stanford disclaimer of liability
36  * --------------------------------
37  * Stanford University makes no representations or warranties, express or
38  * implied, nor assumes any liability for the use of this software.
39  *
40  * Stanford disclaimer of copyright
41  * --------------------------------
42  * Stanford University, owner of the copyright, hereby disclaims its
43  * copyright and all other rights in this software. Hence, anyone may
44  * freely use it for any purpose without restriction.
45  *
46  * Maintenance of notices
47  * ----------------------
48  * In the interest of clarity regarding the origin and status of this
49  * SLAC software, this and all the preceding Stanford University notices
50  * are to remain affixed to any copy or derivative of this software made
51  * or distributed by the recipient and are to be affixed to any copy of
52  * software made or distributed by the recipient that contains a copy or
53  * derivative of this software.
54  *
55  * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
56  */
57 
58 #include <rtems.h>
59 #include <inttypes.h>
60 #include <stdio.h>
61 
62 #ifdef __cplusplus
63 extern "C" {
64 #endif
65 
76 /* Some routines require or return an index 'key'.
77  */
78 typedef int bsp_tlb_idx_t;
79 
80 /* Cache the relevant TLB entries so that we can make sure the user cannot
81  * create conflicting (overlapping) entries. Keep them public for informational
82  * purposes.
83  */
84 typedef struct {
85  struct {
86  uint32_t pad:24;
87  uint32_t tid:8;
88  } id;
89  struct {
90  uint32_t epn:22;
91  uint32_t v:1;
92  uint32_t ts:1;
93  uint32_t size:4;
94  uint32_t tpar:4;
95  } w0;
96  struct {
97  uint32_t rpn:22;
98  uint32_t par1:2;
99  uint32_t pad:4;
100  uint32_t erpn:4;
101  } w1;
102  struct {
103  uint32_t par2:2;
104  uint32_t pad1:14;
105  uint32_t att:4;
106  uint32_t wimge:5;
107  uint32_t pad2:1;
108  uint32_t perm:6;
109  } w2;
111 
112 #define NTLBS 64
113 
114 extern bsp_tlb_entry_t* bsp_mmu_cache;
115 
116 // These constants will have to be shifted right by 20 bits before
117 // being inserted the high word of the TLB.
118 
119 #define MMU_M_SIZE_1K (0x00000000U)
120 #define MMU_M_SIZE_4K (0x08000000U)
121 #define MMU_M_SIZE_16K (0x10000000U)
122 #define MMU_M_SIZE_64K (0x18000000U)
123 #define MMU_M_SIZE_256K (0x20000000U)
124 #define MMU_M_SIZE_1M (0x28000000U)
125 #define MMU_M_SIZE_16M (0x38000000U)
126 #define MMU_M_SIZE_256M (0x48000000U)
127 #define MMU_M_SIZE_MIN (MMU_M_SIZE_1K)
128 #define MMU_M_SIZE_MAX (MMU_M_SIZE_256M)
129 #define MMU_M_SIZE (0x78000000U)
130 #define MMU_V_SIZE (27)
131 
132 // These constants have the same bit positions they'll occupy
133 // in low word of the TLB.
134 
135 #define MMU_M_ATTR_USER0 (0x00010000U)
136 #define MMU_M_ATTR_USER1 (0x00008000U)
137 #define MMU_M_ATTR_USER2 (0x00004000U)
138 #define MMU_M_ATTR_USER3 (0x00002000U)
139 #define MMU_M_ATTR (0x0001e000U)
140 #define MMU_V_ATTR (13)
141 
142 #define MMU_M_PROP_WRITE_THROUGH (0x00001000U)
143 #define MMU_M_PROP_UNCACHED (0x00000800U)
144 #define MMU_M_PROP_MEM_COHERENT (0x00000400U)
145 #define MMU_M_PROP_GUARDED (0x00000200U)
146 #define MMU_M_PROP_LITTLE_ENDIAN (0x00000100U)
147 #define MMU_M_PROP (0x00000f00U)
148 #define MMU_V_PROP (8)
149 
150 #define MMU_M_PERM_USER_EXEC (0x00000020U)
151 #define MMU_M_PERM_USER_WRITE (0x00000010U)
152 #define MMU_M_PERM_USER_READ (0x00000008U)
153 #define MMU_M_PERM_SUPER_EXEC (0x00000004U)
154 #define MMU_M_PERM_SUPER_WRITE (0x00000002U)
155 #define MMU_M_PERM_SUPER_READ (0x00000001U)
156 #define MMU_M_PERM (0x0000003fU)
157 #define MMU_V_PERM (0)
158 
159 
160 /*
161  * Dump (cleartext) content info from cached TLB entries
162  * to a file (stdout if f==NULL).
163  */
164 void
165 bsp_mmu_dump_cache(FILE *f);
166 
167 /* Read a TLB entry from the hardware and store the settings in the
168  * bsp_mmu_cache[] structure.
169  *
170  * The routine can perform this operation quietly or
171  * print information to a file.
172  *
173  * 'key': TLB entry index.
174  * 'quiet': perform operation silently (no info printed) if nonzero.
175  * 'f': open FILE where to print information. May be NULL, in
176  * which case 'stdout' is used.
177  *
178  * RETURNS:
179  * 0: success; TLB entry is VALID
180  * +1: success but TLB entry is INVALID
181  * < 0: error (-1: invalid argument)
182  * (-2: driver not initialized)
183  */
184 int
185 bsp_mmu_update(bsp_tlb_idx_t key, bool quiet, FILE *f);
186 
187 /* Initialize cache. Should be done only once although this is not enforced.
188  *
189  * RETURNS: zero on success, nonzero on error; in this case the driver will
190  * refuse to change TLB entries (other than disabling them).
191  */
192 int
193 bsp_mmu_initialize(void);
194 
195 /* Find first free TLB entry by examining all entries' valid bit. The first
196  * entry without the valid bit set is returned.
197  *
198  * RETURNS: A free TLB entry number. -1 if no entry can be found.
199  */
200 bsp_tlb_idx_t
201 bsp_mmu_find_first_free(void);
202 
203 /* Write a TLB entry (can also be used to disable an entry).
204  *
205  * The routine checks against the cached data in bsp_mmu_cache[]
206  * to prevent the user from generating overlapping entries.
207  *
208  * 'idx': TLB entry # to manipulate
209  * 'ea': Effective address (must be page aligned)
210  * 'pa': Physical address (must be page aligned)
211  * 'sz': Page size selector; page size is 1024 * 2^(2*sz) bytes.
212  * 'sz' may also be one of the following:
213  * - page size in bytes ( >= 1024 ); the selector
214  * value is then computed by this routine.
215  * However, 'sz' must be a valid page size
216  * or -1 will be returned.
217  * - a value < 0 to invalidate/disable the
218  * TLB entry.
219  * 'flgs': Page's User-defined flags, permissions and WIMGE page attributes
220  * 'tid': Translation ID
221  * 'ts': Translation Space
222  * 'erpn': Extended Real Page Number
223  *
224  * RETURNS: 0 on success, nonzero on error:
225  *
226  * >0: requested mapping would overlap with
227  * existing mapping in another entry. Return
228  * value gives conflicting entry + 1; i.e.,
229  * if a value of 4 is returned then the request
230  * conflicts with existing mapping in entry 3.
231  * -1: invalid argument
232  * -3: driver not initialized (or initialization failed).
233  * <0: other error
234  */
235 bsp_tlb_idx_t
236 bsp_mmu_write(bsp_tlb_idx_t idx, uint32_t ea, uint32_t pa, int sz,
237  uint32_t flgs, uint32_t tid, uint32_t ts, uint32_t erpn);
238 
239 /* Check if a ea/tid/ts/sz mapping overlaps with an existing entry.
240  *
241  * 'ea': The Effective Address to match against
242  * 'sz': The 'logarithmic' size selector; the page size
243  * is 1024*2^(2*sz).
244  * 'tid': Translation ID
245  * 'ts': Translation Space
246  *
247  * RETURNS:
248  * >= 0: index of TLB entry that already provides a mapping
249  * which overlaps within the ea range.
250  * -1: SUCCESS (no conflicting entry found)
251  * <=-2: ERROR (invalid input)
252  */
253 bsp_tlb_idx_t
254 bsp_mmu_match(uint32_t ea, int sz, uint32_t tid, uint32_t ts);
255 
256 /* Find TLB index that maps 'ea/tid/ts' combination
257  *
258  * 'ea': Effective address to match against
259  * 'tid': Translation ID
260  * 'ts': Translation Space
261  *
262  * RETURNS: index 'key'; i.e., the index number.
263  *
264  * On error (no mapping) -1 is returned.
265  */
266 bsp_tlb_idx_t
267 bsp_mmu_find(uint32_t ea, uint32_t tid, uint32_t ts);
268 
269 /* Mark TLB entry as invalid ('disabled').
270  *
271  * 'key': TLB entry index.
272  *
273  * RETURNS: zero on success, nonzero on error (TLB unchanged).
274  *
275  * NOTE: If a TLB entry is disabled the associated
276  * entry in bsp_tlb_cache[] is also marked as disabled.
277  */
278 int
279 bsp_mmu_invalidate(bsp_tlb_idx_t key);
280 
283 #ifdef __cplusplus
284 };
285 #endif
286 
287 #endif
uint32_t ts
Definition: mmu.h:92
uint32_t pad1
Definition: mmu.h:104
uint32_t tpar
Definition: mmu.h:94
uint32_t pad2
Definition: mmu.h:107
Definition: mmu.h:84
uint32_t wimge
Definition: mmu.h:106
Provide printf() PRIxxx Constante Beyond Standards.
unsigned size
Definition: tte.h:74
unsigned v
Definition: tte.h:73
uint32_t par1
Definition: mmu.h:98