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sh7_pfc.h
1 /*
2  * Bit values for the pin function controller of the Hitachi SH704x
3  *
4  * From Hitachi tutorials
5  *
6  * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
7  * Bernd Becker (becker@faw.uni-ulm.de)
8  *
9  * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14  *
15  *
16  * COPYRIGHT (c) 1998.
17  * On-Line Applications Research Corporation (OAR).
18  *
19  * The license and distribution terms for this file may be
20  * found in the file LICENSE in this distribution or at
21  * http://www.rtems.org/license/LICENSE.
22  */
23 
24 #ifndef _sh7_pfc_h
25 #define _sh7_pfc_h
26 
27 #include <rtems/score/iosh7045.h>
28 
29 /*
30  * Port A IO Registers (PAIORH, PAIORL)
31  * 1 => OUTPUT
32  * 0 => INPUT
33  */
34 #define PAIORH PFC_PAIORH
35 #define PAIORL PFC_PAIORL
36 
37 /* PAIORH */
38 #define PA23IOR 0x0080
39 #define PA22IOR 0x0040
40 #define PA21IOR 0x0020
41 #define PA20IOR 0x0010
42 #define PA19IOR 0x0008
43 #define PA18IOR 0x0004
44 #define PA17IOR 0x0002
45 #define PA16IOR 0x0001
46 
47 /* PAIORL */
48 #define PA15IOR 0x8000
49 #define PA14IOR 0x4000
50 #define PA13IOR 0x2000
51 #define PA12IOR 0x1000
52 #define PA11IOR 0x0800
53 #define PA10IOR 0x0400
54 #define PA9IOR 0x0200
55 #define PA8IOR 0x0100
56 #define PA7IOR 0x0080
57 #define PA6IOR 0x0040
58 #define PA5IOR 0x0020
59 #define PA4IOR 0x0010
60 #define PA3IOR 0x0008
61 #define PA2IOR 0x0004
62 #define PA1IOR 0x0002
63 #define PA0IOR 0x0001
64 
65 /*
66  * Port A Control Registers (PACRH, PACRL1, PACRL2)
67  * and mode bits
68  */
69 #define PACRH PFC_PACRH
70 #define PACRL1 PFC_PACRL1
71 #define PACRL2 PFC_PACRL2
72 
73 /* PACRH */
74 #define PA23MD0 0x4000
75 #define PA22MD0 0x1000
76 #define PA21MD0 0x0400
77 #define PA20MD0 0x0100
78 #define PA19MD1 0x0080
79 #define PA19MD0 0x0040
80 #define PA18MD1 0x0020
81 #define PA18MD0 0x0010
82 #define PA17MD0 0x0004
83 #define PA16MD0 0x0001
84 
85 /* PACRL1 */
86 #define PA15MD0 0x4000
87 #define PA14MD0 0x1000
88 #define PA13MD0 0x0400
89 #define PA12MD0 0x0100
90 #define PA11MD0 0x0040
91 #define PA10MD0 0x0010
92 #define PA9MD1 0x0008
93 #define PA9MD0 0x0004
94 #define PA8MD1 0x0002
95 #define PA8MD0 0x0001
96 
97 /* PACRL2 */
98 #define PA7MD1 0x8000
99 #define PA7MD0 0x4000
100 #define PA6MD1 0x2000
101 #define PA6MD0 0x1000
102 #define PA5MD1 0x0800
103 #define PA5MD0 0x0400
104 #define PA4MD0 0x0100
105 #define PA3MD0 0x0040
106 #define PA2MD1 0x0020
107 #define PA2MD0 0x0010
108 #define PA1MD0 0x0004
109 #define PA0MD0 0x0001
110 
111 #define PA_TXD1 PA4MD0
112 #define PA_RXD1 PA3MD0
113 #define PA_TXD0 PA1MD0
114 #define PA_RXD0 PA0MD0
115 
116 /*
117  * Port B IO Register (PBIOR)
118  */
119 #define PBIOR PFC_PBIOR
120 #define PB15IOR 0x8000
121 #define PB14IOR 0x4000
122 #define PB13IOR 0x2000
123 #define PB12IOR 0x1000
124 #define PB11IOR 0x0800
125 #define PB10IOR 0x0400
126 #define PB9IOR 0x0200
127 #define PB8IOR 0x0100
128 #define PB7IOR 0x0080
129 #define PB6IOR 0x0040
130 #define PB5IOR 0x0020
131 #define PB4IOR 0x0010
132 #define PB3IOR 0x0008
133 #define PB2IOR 0x0004
134 #define PB1IOR 0x0002
135 #define PB0IOR 0x0001
136 
137 /*
138  * Port B Control Register (PBCR1)
139  */
140 #define PBCR1 PFC_PBCR1
141 #define PB15MD1 0x8000
142 #define PB15MD0 0x4000
143 #define PB14MD1 0x2000
144 #define PB14MD0 0x1000
145 #define PB13MD1 0x0800
146 #define PB13MD0 0x0400
147 #define PB12MD1 0x0200
148 #define PB12MD0 0x0100
149 #define PB11MD1 0x0080
150 #define PB11MD0 0x0040
151 #define PB10MD1 0x0020
152 #define PB10MD0 0x0010
153 #define PB9MD1 0x0008
154 #define PB9MD0 0x0004
155 #define PB8MD1 0x0002
156 #define PB8MD0 0x0001
157 
158 #define PB15MD PB15MD1|PB14MD0
159 #define PB14MD PB14MD1|PB14MD0
160 #define PB13MD PB13MD1|PB13MD0
161 #define PB12MD PB12MD1|PB12MD0
162 #define PB11MD PB11MD1|PB11MD0
163 #define PB10MD PB10MD1|PB10MD0
164 #define PB9MD PB9MD1|PB9MD0
165 #define PB8MD PB8MD1|PB8MD0
166 
167 #define PB_TXD1 PB11MD1
168 #define PB_RXD1 PB10MD1
169 #define PB_TXD0 PB9MD1
170 #define PB_RXD0 PB8MD1
171 
172 /*
173  * Port B Control Register (PBCR2)
174  */
175 #define PBCR2 PFC_PBCR2
176 #define PB7MD1 0x8000
177 #define PB7MD0 0x4000
178 #define PB6MD1 0x2000
179 #define PB6MD0 0x1000
180 #define PB5MD1 0x0800
181 #define PB5MD0 0x0400
182 #define PB4MD1 0x0200
183 #define PB4MD0 0x0100
184 #define PB3MD1 0x0080
185 #define PB3MD0 0x0040
186 #define PB2MD1 0x0020
187 #define PB2MD0 0x0010
188 #define PB1MD1 0x0008
189 #define PB1MD0 0x0004
190 #define PB0MD1 0x0002
191 #define PB0MD0 0x0001
192 
193 #define PB7MD PB7MD1|PB7MD0
194 #define PB6MD PB6MD1|PB6MD0
195 #define PB5MD PB5MD1|PB5MD0
196 #define PB4MD PB4MD1|PB4MD0
197 #define PB3MD PB3MD1|PB3MD0
198 #define PB2MD PB2MD1|PB2MD0
199 #define PB1MD PB1MD1|PB1MD0
200 #define PB0MD PB0MD1|PB0MD0
201 
202 #endif /* _sh7_pfc_h */